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Diffstat (limited to 'gcc/config/mips/sr71k.md')
| -rw-r--r-- | gcc/config/mips/sr71k.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/config/mips/sr71k.md b/gcc/config/mips/sr71k.md index faeeebc..82162e3 100644 --- a/gcc/config/mips/sr71k.md +++ b/gcc/config/mips/sr71k.md @@ -4,7 +4,7 @@ ;; ;; The SR3 is describeds as: ;; - nine-stage pipeline, insn buffering with out-of-order issue to -;; multiple function units, with a average dispatch rate of 2 +;; multiple function units, with an average dispatch rate of 2 ;; insn.s per cycle (max 6 insns: 2 fpu, 4 cpu). ;; ;; The details on this are scant except for a diagram in |