diff options
Diffstat (limited to 'gcc/config/m68k/m68k.md')
| -rw-r--r-- | gcc/config/m68k/m68k.md | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md index a46b3fa..3191aec 100644 --- a/gcc/config/m68k/m68k.md +++ b/gcc/config/m68k/m68k.md @@ -5487,7 +5487,7 @@ if (REG_P (operands[0])) { if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32) - return "bfins %3,%0{%b2:%b1}"; + return "bfins %3,%0%{%b2:%b1%}"; } else operands[0] = adjust_address (operands[0], @@ -5542,7 +5542,7 @@ if (REG_P (operands[1])) { if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32) - return "bfextu %1{%b3:%b2},%0"; + return "bfextu %1%{%b3:%b2%},%0"; } else operands[1] @@ -5595,7 +5595,7 @@ if (REG_P (operands[1])) { if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32) - return "bfexts %1{%b3:%b2},%0"; + return "bfexts %1%{%b3:%b2%},%0"; } else operands[1] @@ -5626,7 +5626,7 @@ (match_operand:SI 2 "nonmemory_operand" "dn") (match_operand:SI 3 "nonmemory_operand" "dn")))] "TARGET_68020 && TARGET_BITFIELD" - "bfexts %1{%b3:%b2},%0") + "bfexts %1%{%b3:%b2%},%0") (define_expand "extzv" [(set (match_operand:SI 0 "register_operand" "") @@ -5652,7 +5652,7 @@ { CC_STATUS_INIT; } - return "bfextu %1{%b3:%b2},%0"; + return "bfextu %1%{%b3:%b2%},%0"; }) (define_insn "" @@ -5667,7 +5667,7 @@ && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))" { CC_STATUS_INIT; - return "bfchg %0{%b2:%b1}"; + return "bfchg %0%{%b2:%b1%}"; }) (define_insn "" @@ -5678,7 +5678,7 @@ "TARGET_68020 && TARGET_BITFIELD" { CC_STATUS_INIT; - return "bfclr %0{%b2:%b1}"; + return "bfclr %0%{%b2:%b1%}"; }) (define_insn "" @@ -5689,7 +5689,7 @@ "TARGET_68020 && TARGET_BITFIELD" { CC_STATUS_INIT; - return "bfset %0{%b2:%b1}"; + return "bfset %0%{%b2:%b1%}"; }) (define_expand "insv" @@ -5706,7 +5706,7 @@ (match_operand:SI 2 "nonmemory_operand" "dn")) (match_operand:SI 3 "register_operand" "d"))] "TARGET_68020 && TARGET_BITFIELD" - "bfins %3,%0{%b2:%b1}") + "bfins %3,%0%{%b2:%b1%}") ;; Now recognize bit-field insns that operate on registers ;; (or at least were intended to do so). @@ -5717,7 +5717,7 @@ (match_operand:SI 2 "const_int_operand" "n") (match_operand:SI 3 "const_int_operand" "n")))] "TARGET_68020 && TARGET_BITFIELD" - "bfexts %1{%b3:%b2},%0") + "bfexts %1%{%b3:%b2%},%0") (define_insn "" [(set (match_operand:SI 0 "nonimmediate_operand" "=d") @@ -5735,7 +5735,7 @@ { CC_STATUS_INIT; } - return "bfextu %1{%b3:%b2},%0"; + return "bfextu %1%{%b3:%b2%},%0"; }) (define_insn "" @@ -5746,7 +5746,7 @@ "TARGET_68020 && TARGET_BITFIELD" { CC_STATUS_INIT; - return "bfclr %0{%b2:%b1}"; + return "bfclr %0%{%b2:%b1%}"; }) (define_insn "" @@ -5757,7 +5757,7 @@ "TARGET_68020 && TARGET_BITFIELD" { CC_STATUS_INIT; - return "bfset %0{%b2:%b1}"; + return "bfset %0%{%b2:%b1%}"; }) (define_insn "" @@ -5776,7 +5776,7 @@ && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8) return "move%.b %3,%0"; #endif - return "bfins %3,%0{%b2:%b1}"; + return "bfins %3,%0%{%b2:%b1%}"; }) ;; Special patterns for optimizing bit-field instructions. @@ -5801,7 +5801,7 @@ } if (INTVAL (operands[1]) != 32) cc_status.flags = CC_NOT_NEGATIVE; - return "bftst %0{%b2:%b1}"; + return "bftst %0%{%b2:%b1%}"; }) @@ -5825,7 +5825,7 @@ } if (INTVAL (operands[1]) != 32) cc_status.flags = CC_NOT_NEGATIVE; - return "bftst %0{%b2:%b1}"; + return "bftst %0%{%b2:%b1%}"; }) (define_insn "scc0_di" |