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Diffstat (limited to 'gcc/config/m68k/m68k.md')
-rw-r--r--gcc/config/m68k/m68k.md104
1 files changed, 64 insertions, 40 deletions
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index bfe5e58..e120ed8 100644
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -658,7 +658,7 @@
;; Recognizers for btst instructions.
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "do")
+ [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
(const_int 1)
(minus:SI (const_int 7)
(match_operand:SI 1 "general_operand" "di"))))]
@@ -666,7 +666,7 @@
"* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "d")
+ [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
(const_int 1)
(minus:SI (const_int 31)
(match_operand:SI 1 "general_operand" "di"))))]
@@ -678,7 +678,7 @@
;; are automatically masked to 3 or 5 bits.
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "do")
+ [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
(const_int 1)
(minus:SI (const_int 7)
(and:SI
@@ -688,7 +688,7 @@
"* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "d")
+ [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
(const_int 1)
(minus:SI (const_int 31)
(and:SI
@@ -700,7 +700,7 @@
;; Nonoffsettable mem refs are ok in this one pattern
;; since we don't try to adjust them.
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "md")
+ [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
(const_int 1)
(match_operand:SI 1 "const_int_operand" "n")))]
"(unsigned) INTVAL (operands[1]) < 8"
@@ -711,7 +711,7 @@
}")
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "do")
+ [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
(const_int 1)
(match_operand:SI 1 "const_int_operand" "n")))]
""
@@ -4770,7 +4770,7 @@
; than an odd byte aligned bit field instruction.
;
(define_insn ""
- [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o")
+ [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
(const_int 32)
(match_operand:SI 2 "const_int_operand" "n"))
(match_operand:SI 3 "general_operand" "rmi"))]
@@ -4786,7 +4786,7 @@
}")
(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+do")
+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
(match_operand:SI 1 "const_int_operand" "n")
(match_operand:SI 2 "const_int_operand" "n"))
(match_operand:SI 3 "register_operand" "d"))]
@@ -4824,7 +4824,7 @@
;
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=rm")
- (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o")
+ (zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
(const_int 32)
(match_operand:SI 3 "const_int_operand" "n")))]
"TARGET_68020 && TARGET_BITFIELD
@@ -4840,7 +4840,7 @@
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=&d")
- (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do")
+ (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
(match_operand:SI 2 "const_int_operand" "n")
(match_operand:SI 3 "const_int_operand" "n")))]
"TARGET_68020 && TARGET_BITFIELD
@@ -4878,7 +4878,7 @@
;
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=rm")
- (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o")
+ (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
(const_int 32)
(match_operand:SI 3 "const_int_operand" "n")))]
"TARGET_68020 && TARGET_BITFIELD
@@ -4894,7 +4894,7 @@
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=d")
- (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do")
+ (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
(match_operand:SI 2 "const_int_operand" "n")
(match_operand:SI 3 "const_int_operand" "n")))]
"TARGET_68020 && TARGET_BITFIELD
@@ -4922,17 +4922,33 @@
;; "o,d" constraint causes a nonoffsettable memref to match the "o"
;; so that its address is reloaded.
-(define_insn "extv"
- [(set (match_operand:SI 0 "general_operand" "=d,d")
- (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d")
- (match_operand:SI 2 "general_operand" "di,di")
- (match_operand:SI 3 "general_operand" "di,di")))]
+(define_expand "extv"
+ [(set (match_operand:SI 0 "general_operand" "")
+ (sign_extract:SI (match_operand:SI 1 "general_operand" "")
+ (match_operand:SI 2 "general_operand" "")
+ (match_operand:SI 3 "general_operand" "")))]
+ "TARGET_68020 && TARGET_BITFIELD"
+ "")
+
+(define_insn ""
+ [(set (match_operand:SI 0 "general_operand" "=d")
+ (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
+ (match_operand:SI 2 "general_operand" "di")
+ (match_operand:SI 3 "general_operand" "di")))]
"TARGET_68020 && TARGET_BITFIELD"
"bfexts %1{%b3:%b2},%0")
-(define_insn "extzv"
+(define_expand "extzv"
+ [(set (match_operand:SI 0 "general_operand" "")
+ (zero_extract:SI (match_operand:SI 1 "general_operand" "")
+ (match_operand:SI 2 "general_operand" "")
+ (match_operand:SI 3 "general_operand" "")))]
+ "TARGET_68020 && TARGET_BITFIELD"
+ "")
+
+(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=d,d")
- (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d")
+ (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
(match_operand:SI 2 "general_operand" "di,di")
(match_operand:SI 3 "general_operand" "di,di")))]
"TARGET_68020 && TARGET_BITFIELD"
@@ -4951,11 +4967,11 @@
}")
(define_insn ""
- [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
- (match_operand:SI 1 "general_operand" "di,di")
- (match_operand:SI 2 "general_operand" "di,di"))
+ [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
+ (match_operand:SI 1 "general_operand" "di")
+ (match_operand:SI 2 "general_operand" "di"))
(xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
- (match_operand 3 "const_int_operand" "n,n")))]
+ (match_operand 3 "const_int_operand" "n")))]
"TARGET_68020 && TARGET_BITFIELD
&& (INTVAL (operands[3]) == -1
|| (GET_CODE (operands[1]) == CONST_INT
@@ -4967,9 +4983,9 @@
}")
(define_insn ""
- [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
- (match_operand:SI 1 "general_operand" "di,di")
- (match_operand:SI 2 "general_operand" "di,di"))
+ [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
+ (match_operand:SI 1 "general_operand" "di")
+ (match_operand:SI 2 "general_operand" "di"))
(const_int 0))]
"TARGET_68020 && TARGET_BITFIELD"
"*
@@ -4979,9 +4995,9 @@
}")
(define_insn ""
- [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
- (match_operand:SI 1 "general_operand" "di,di")
- (match_operand:SI 2 "general_operand" "di,di"))
+ [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
+ (match_operand:SI 1 "general_operand" "di")
+ (match_operand:SI 2 "general_operand" "di"))
(const_int -1))]
"TARGET_68020 && TARGET_BITFIELD"
"*
@@ -4990,11 +5006,19 @@
return \"bfset %0{%b2:%b1}\";
}")
-(define_insn "insv"
- [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
- (match_operand:SI 1 "general_operand" "di,di")
- (match_operand:SI 2 "general_operand" "di,di"))
- (match_operand:SI 3 "register_operand" "d,d"))]
+(define_expand "insv"
+ [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
+ (match_operand:SI 1 "general_operand" "")
+ (match_operand:SI 2 "general_operand" ""))
+ (match_operand:SI 3 "register_operand" ""))]
+ "TARGET_68020 && TARGET_BITFIELD"
+ "")
+
+(define_insn ""
+ [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
+ (match_operand:SI 1 "general_operand" "di")
+ (match_operand:SI 2 "general_operand" "di"))
+ (match_operand:SI 3 "register_operand" "d"))]
"TARGET_68020 && TARGET_BITFIELD"
"bfins %3,%0{%b2:%b1}")
@@ -5003,7 +5027,7 @@
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=d")
- (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d")
+ (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "general_operand" "di")
(match_operand:SI 3 "general_operand" "di")))]
"TARGET_68020 && TARGET_BITFIELD"
@@ -5011,7 +5035,7 @@
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=d")
- (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d")
+ (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "general_operand" "di")
(match_operand:SI 3 "general_operand" "di")))]
"TARGET_68020 && TARGET_BITFIELD"
@@ -5030,7 +5054,7 @@
}")
(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")
+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
(match_operand:SI 1 "general_operand" "di")
(match_operand:SI 2 "general_operand" "di"))
(const_int 0))]
@@ -5042,7 +5066,7 @@
}")
(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")
+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
(match_operand:SI 1 "general_operand" "di")
(match_operand:SI 2 "general_operand" "di"))
(const_int -1))]
@@ -5054,7 +5078,7 @@
}")
(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")
+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
(match_operand:SI 1 "general_operand" "di")
(match_operand:SI 2 "general_operand" "di"))
(match_operand:SI 3 "register_operand" "d"))]
@@ -5105,7 +5129,7 @@
;;; now handle the register cases
(define_insn ""
[(set (cc0)
- (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "d")
+ (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
(match_operand:SI 1 "const_int_operand" "n")
(match_operand:SI 2 "general_operand" "di")))]
"TARGET_68020 && TARGET_BITFIELD"
generated by cgit v1.1 at 2025-02-07 05:21:09 +0000