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-rw-r--r--gcc/config/m32r/m32r-protos.h5
-rw-r--r--gcc/config/m32r/m32r.c63
-rw-r--r--gcc/config/m32r/m32r.h61
3 files changed, 51 insertions, 78 deletions
diff --git a/gcc/config/m32r/m32r-protos.h b/gcc/config/m32r/m32r-protos.h
index f0a1a5b..fd93040 100644
--- a/gcc/config/m32r/m32r-protos.h
+++ b/gcc/config/m32r/m32r-protos.h
@@ -31,7 +31,6 @@ extern int m32r_first_insn_address PARAMS ((void));
extern void m32r_expand_prologue PARAMS ((void));
extern void m32r_finalize_pic PARAMS ((void));
extern void m32r_asm_file_start PARAMS ((FILE *));
-extern void m32r_sched_init PARAMS ((FILE *, int));
extern int direct_return PARAMS ((void));
#ifdef TREE_CODE
extern void m32r_select_section PARAMS ((tree, int));
@@ -60,10 +59,6 @@ extern void m32r_expand_block_move PARAMS ((rtx *));
extern void m32r_print_operand PARAMS ((FILE *, rtx, int));
extern void m32r_print_operand_address PARAMS ((FILE *, rtx));
extern int m32r_address_cost PARAMS ((rtx));
-extern int m32r_adjust_cost PARAMS ((rtx, rtx, rtx, int));
-extern int m32r_adjust_priority PARAMS ((rtx, int));
-extern void m32r_sched_reorder PARAMS ((FILE *, int, rtx *, int));
-extern int m32r_sched_variable_issue PARAMS ((FILE *, int, rtx, int));
extern int m32r_not_same_reg PARAMS ((rtx, rtx));
#ifdef HAVE_MACHINE_MODES
diff --git a/gcc/config/m32r/m32r.c b/gcc/config/m32r/m32r.c
index a37ed65..a9ca24f 100644
--- a/gcc/config/m32r/m32r.c
+++ b/gcc/config/m32r/m32r.c
@@ -56,7 +56,7 @@ const char * m32r_sdata_string = M32R_SDATA_DEFAULT;
enum m32r_sdata m32r_sdata;
/* Scheduler support */
-int m32r_sched_odd_word_p;
+static int m32r_sched_odd_word_p;
/* Forward declaration. */
static void init_reg_tables PARAMS ((void));
@@ -66,6 +66,14 @@ static int m32r_valid_decl_attribute PARAMS ((tree, tree,
tree, tree));
static void m32r_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
static void m32r_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
+
+static int m32r_adjust_cost PARAMS ((rtx, rtx, rtx, int));
+static int m32r_adjust_priority PARAMS ((rtx, int));
+static void m32r_sched_init PARAMS ((FILE *, int));
+static int m32r_sched_reorder PARAMS ((FILE *, int, rtx *, int *, int));
+static int m32r_variable_issue PARAMS ((FILE *, int, rtx, int));
+static int m32r_issue_rate PARAMS ((void));
+
/* Initialize the GCC target structure. */
#undef TARGET_VALID_DECL_ATTRIBUTE
@@ -76,6 +84,19 @@ static void m32r_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
#undef TARGET_ASM_FUNCTION_EPILOGUE
#define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
+#undef TARGET_SCHED_ADJUST_COST
+#define TARGET_SCHED_ADJUST_COST m32r_adjust_cost
+#undef TARGET_SCHED_ADJUST_PRIORITY
+#define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
+#undef TARGET_SCHED_ISSUE_RATE
+#define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
+#undef TARGET_SCHED_VARIABLE_ISSUE
+#define TARGET_SCHED_VARIABLE_ISSUE m32r_variable_issue
+#undef TARGET_SCHED_INIT
+#define TARGET_SCHED_INIT m32r_sched_init
+#undef TARGET_SCHED_REORDER
+#define TARGET_SCHED_REORDER m32r_sched_reorder
+
struct gcc_target targetm = TARGET_INITIALIZER;
/* Called by OVERRIDE_OPTIONS to initialize various things. */
@@ -1471,7 +1492,7 @@ m32r_va_arg (valist, type)
return addr_rtx;
}
-int
+static int
m32r_adjust_cost (insn, link, dep_insn, cost)
rtx insn ATTRIBUTE_UNUSED;
rtx link ATTRIBUTE_UNUSED;
@@ -1497,7 +1518,7 @@ m32r_is_insn (insn)
/* Increase the priority of long instructions so that the
short instructions are scheduled ahead of the long ones. */
-int
+static int
m32r_adjust_priority (insn, priority)
rtx insn;
int priority;
@@ -1512,7 +1533,7 @@ m32r_adjust_priority (insn, priority)
/* Initialize for scheduling a group of instructions. */
-void
+static void
m32r_sched_init (stream, verbose)
FILE * stream ATTRIBUTE_UNUSED;
int verbose ATTRIBUTE_UNUSED;
@@ -1523,15 +1544,18 @@ m32r_sched_init (stream, verbose)
/* Reorder the schedulers priority list if needed */
-void
-m32r_sched_reorder (stream, verbose, ready, n_ready)
+static int
+m32r_sched_reorder (stream, verbose, ready, n_readyp, clock)
FILE * stream;
int verbose;
rtx * ready;
- int n_ready;
+ int *n_readyp;
+ int clock ATTRIBUTE_UNUSED;
{
+ int n_ready = *n_readyp;
+
if (TARGET_DEBUG)
- return;
+ return m32r_issue_rate ();
if (verbose <= 7)
stream = (FILE *)0;
@@ -1605,11 +1629,8 @@ m32r_sched_reorder (stream, verbose, ready, n_ready)
memcpy (ready, new_head, sizeof (rtx) * n_ready);
if (stream)
{
-#ifdef HAIFA
- fprintf (stream, ";;\t\t::: New ready list: ");
- debug_ready_list (ready, n_ready);
-#else
int i;
+ fprintf (stream, ";;\t\t::: New ready list: ");
for (i = 0; i < n_ready; i++)
{
rtx insn = ready[i];
@@ -1627,17 +1648,27 @@ m32r_sched_reorder (stream, verbose, ready, n_ready)
}
fprintf (stream, "\n");
-#endif
}
}
+ return m32r_issue_rate ();
+}
+
+/* Indicate how many instructions can be issued at the same time.
+ This is sort of a lie. The m32r can issue only 1 long insn at
+ once, but it can issue 2 short insns. The default therefore is
+ set at 2, but this can be overridden by the command line option
+ -missue-rate=1 */
+static int
+m32r_issue_rate ()
+{
+ return ((TARGET_LOW_ISSUE_RATE) ? 1 : 2);
}
-
/* If we have a machine that can issue a variable # of instructions
per cycle, indicate how many more instructions can be issued
after the current one. */
-int
-m32r_sched_variable_issue (stream, verbose, insn, how_many)
+static int
+m32r_variable_issue (stream, verbose, insn, how_many)
FILE * stream;
int verbose;
rtx insn;
diff --git a/gcc/config/m32r/m32r.h b/gcc/config/m32r/m32r.h
index 692249b..5ef9951 100644
--- a/gcc/config/m32r/m32r.h
+++ b/gcc/config/m32r/m32r.h
@@ -154,8 +154,8 @@ extern int target_flags;
#define TARGET_ALIGN_LOOPS (target_flags & TARGET_ALIGN_LOOPS_MASK)
/* Change issue rate. */
-#define TARGET_ISSUE_RATE_MASK (1 << 3)
-#define TARGET_ISSUE_RATE (target_flags & TARGET_ISSUE_RATE_MASK)
+#define TARGET_LOW_ISSUE_RATE_MASK (1 << 3)
+#define TARGET_LOW_ISSUE_RATE (target_flags & TARGET_LOW_ISSUE_RATE_MASK)
/* Change branch cost */
#define TARGET_BRANCH_COST_MASK (1 << 4)
@@ -187,9 +187,9 @@ extern int target_flags;
{ "align-loops", TARGET_ALIGN_LOOPS_MASK, \
N_("Align all loops to 32 byte boundary") }, \
{ "no-align-loops", -TARGET_ALIGN_LOOPS_MASK, "" }, \
- { "issue-rate=1", TARGET_ISSUE_RATE_MASK, \
+ { "issue-rate=1", TARGET_LOW_ISSUE_RATE_MASK, \
N_("Only issue one instruction per cycle") }, \
- { "issue-rate=2", -TARGET_ISSUE_RATE_MASK, "" }, \
+ { "issue-rate=2", -TARGET_LOW_ISSUE_RATE_MASK, "" }, \
{ "branch-cost=1", TARGET_BRANCH_COST_MASK, \
N_("Prefer branches over conditional execution") }, \
{ "branch-cost=2", -TARGET_BRANCH_COST_MASK, "" }, \
@@ -1473,59 +1473,6 @@ do { \
register. */
#define NO_RECURSIVE_FUNCTION_CSE
-/* A C statement (sans semicolon) to update the integer variable COST based on
- the relationship between INSN that is dependent on DEP_INSN through the
- dependence LINK. The default is to make no adjustment to COST. This can be
- used for example to specify to the scheduler that an output- or
- anti-dependence does not incur the same cost as a data-dependence. */
-
-#define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
- (COST) = m32r_adjust_cost (INSN, LINK, DEP_INSN, COST)
-
-/* A C statement (sans semicolon) to update the integer scheduling
- priority `INSN_PRIORITY(INSN)'. Reduce the priority to execute
- the INSN earlier, increase the priority to execute INSN later.
- Do not define this macro if you do not need to adjust the
- scheduling priorities of insns. */
-#define ADJUST_PRIORITY(INSN) \
- INSN_PRIORITY (INSN) = m32r_adjust_priority (INSN, INSN_PRIORITY (INSN))
-
-/* Macro to determine whether the Haifa scheduler is used. */
-#ifdef HAIFA
-#define HAIFA_P 1
-#else
-#define HAIFA_P 0
-#endif
-
-/* Indicate how many instructions can be issued at the same time.
- This is sort of a lie. The m32r can issue only 1 long insn at
- once, but it can issue 2 short insns. The default therefore is
- set at 2, but this can be overridden by the command line option
- -missue-rate=1 */
-#define ISSUE_RATE ((TARGET_ISSUE_RATE) ? 1 : 2)
-
-/* If we have a machine that can issue a variable # of instructions
- per cycle, indicate how many more instructions can be issued
- after the current one. */
-#define MD_SCHED_VARIABLE_ISSUE(STREAM, VERBOSE, INSN, HOW_MANY) \
-(HOW_MANY) = m32r_sched_variable_issue (STREAM, VERBOSE, INSN, HOW_MANY)
-
-/* Whether we are on an odd word boundary while scheduling. */
-extern int m32r_sched_odd_word_p;
-
-/* Hook to run before scheduling a block of insns. */
-#define MD_SCHED_INIT(STREAM, VERBOSE, MAX_READY) \
- m32r_sched_init (STREAM, VERBOSE)
-
-/* Hook to reorder the list of ready instructions. */
-#define MD_SCHED_REORDER(STREAM, VERBOSE, READY, N_READY, CLOCK, CIM) \
- do \
- { \
- m32r_sched_reorder (STREAM, VERBOSE, READY, N_READY); \
- CIM = issue_rate; \
- } \
- while (0)
-
/* When the `length' insn attribute is used, this macro specifies the
value to be assigned to the address of the first insn in a
function. If not specified, 0 is used. */
generated by cgit v1.1 at 2025-04-02 21:57:15 +0000