diff options
Diffstat (limited to 'gcc/config/ia64/ia64.md')
| -rw-r--r-- | gcc/config/ia64/ia64.md | 640 |
1 files changed, 20 insertions, 620 deletions
diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md index d20ae69..f9c6de2d 100644 --- a/gcc/config/ia64/ia64.md +++ b/gcc/config/ia64/ia64.md @@ -1234,6 +1234,13 @@ ;; Convert between signed integer types and floating point. +(define_insn "floatdirf2" + [(set (match_operand:RF 0 "fr_register_operand" "=f") + (float:RF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))] + "" + "fcvt.xf %0 = %F1" + [(set_attr "itanium_class" "fcvtfx")]) + (define_insn "floatdixf2" [(set (match_operand:XF 0 "fr_register_operand" "=f") (float:XF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))] @@ -1262,12 +1269,11 @@ "fcvt.fx.trunc %0 = %F1" [(set_attr "itanium_class" "fcvtfx")]) -(define_insn "fix_truncxfdi2_alts" +(define_insn "fix_truncrfdi2" [(set (match_operand:DI 0 "fr_register_operand" "=f") - (fix:DI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG"))) - (use (match_operand:SI 2 "const_int_operand" ""))] + (fix:DI (match_operand:RF 1 "fr_reg_or_fp01_operand" "fG")))] "" - "fcvt.fx.trunc.s%2 %0 = %F1" + "fcvt.fx.trunc %0 = %F1" [(set_attr "itanium_class" "fcvtfx")]) ;; Convert between unsigned integer types and floating point. @@ -1293,6 +1299,13 @@ "fcvt.xuf %0 = %F1" [(set_attr "itanium_class" "fcvtfx")]) +(define_insn "floatunsdirf2" + [(set (match_operand:RF 0 "fr_register_operand" "=f") + (unsigned_float:RF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))] + "" + "fcvt.xuf %0 = %F1" + [(set_attr "itanium_class" "fcvtfx")]) + (define_insn "fixuns_truncsfdi2" [(set (match_operand:DI 0 "fr_register_operand" "=f") (unsigned_fix:DI (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))] @@ -1314,12 +1327,11 @@ "fcvt.fxu.trunc %0 = %F1" [(set_attr "itanium_class" "fcvtfx")]) -(define_insn "fixuns_truncxfdi2_alts" +(define_insn "fixuns_truncrfdi2" [(set (match_operand:DI 0 "fr_register_operand" "=f") - (unsigned_fix:DI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG"))) - (use (match_operand:SI 2 "const_int_operand" ""))] + (unsigned_fix:DI (match_operand:RF 1 "fr_reg_or_fp01_operand" "fG")))] "" - "fcvt.fxu.trunc.s%2 %0 = %F1" + "fcvt.fxu.trunc %0 = %F1" [(set_attr "itanium_class" "fcvtfx")]) ;; :::::::::::::::::::: @@ -2176,169 +2188,6 @@ (match_dup 1) (match_dup 2)))] "" { operands[3] = gen_reg_rtx (BImode); }) - -(define_expand "divsi3" - [(set (match_operand:SI 0 "register_operand" "") - (div:SI (match_operand:SI 1 "general_operand" "") - (match_operand:SI 2 "general_operand" "")))] - "TARGET_INLINE_INT_DIV" -{ - rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp; - - op0_xf = gen_reg_rtx (XFmode); - op0_di = gen_reg_rtx (DImode); - - if (CONSTANT_P (operands[1])) - operands[1] = force_reg (SImode, operands[1]); - op1_xf = gen_reg_rtx (XFmode); - expand_float (op1_xf, operands[1], 0); - - if (CONSTANT_P (operands[2])) - operands[2] = force_reg (SImode, operands[2]); - op2_xf = gen_reg_rtx (XFmode); - expand_float (op2_xf, operands[2], 0); - - /* 2^-34 */ - twon34_exp = gen_reg_rtx (DImode); - emit_move_insn (twon34_exp, GEN_INT (65501)); - twon34 = gen_reg_rtx (XFmode); - emit_insn (gen_setf_exp_xf (twon34, twon34_exp)); - - emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (SImode), - CONST1_RTX (SImode))); - - emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34)); - - emit_insn (gen_fix_truncxfdi2_alts (op0_di, op0_xf, const1_rtx)); - emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); - DONE; -}) - -(define_expand "modsi3" - [(set (match_operand:SI 0 "register_operand" "") - (mod:SI (match_operand:SI 1 "general_operand" "") - (match_operand:SI 2 "general_operand" "")))] - "TARGET_INLINE_INT_DIV" -{ - rtx op2_neg, op1_di, div; - - div = gen_reg_rtx (SImode); - emit_insn (gen_divsi3 (div, operands[1], operands[2])); - - op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0); - - /* This is a trick to get us to reuse the value that we're sure to - have already copied to the FP regs. */ - op1_di = gen_reg_rtx (DImode); - convert_move (op1_di, operands[1], 0); - - emit_insn (gen_maddsi4 (operands[0], div, op2_neg, - gen_lowpart (SImode, op1_di))); - DONE; -}) - -(define_expand "udivsi3" - [(set (match_operand:SI 0 "register_operand" "") - (udiv:SI (match_operand:SI 1 "general_operand" "") - (match_operand:SI 2 "general_operand" "")))] - "TARGET_INLINE_INT_DIV" -{ - rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp; - - op0_xf = gen_reg_rtx (XFmode); - op0_di = gen_reg_rtx (DImode); - - if (CONSTANT_P (operands[1])) - operands[1] = force_reg (SImode, operands[1]); - op1_xf = gen_reg_rtx (XFmode); - expand_float (op1_xf, operands[1], 1); - - if (CONSTANT_P (operands[2])) - operands[2] = force_reg (SImode, operands[2]); - op2_xf = gen_reg_rtx (XFmode); - expand_float (op2_xf, operands[2], 1); - - /* 2^-34 */ - twon34_exp = gen_reg_rtx (DImode); - emit_move_insn (twon34_exp, GEN_INT (65501)); - twon34 = gen_reg_rtx (XFmode); - emit_insn (gen_setf_exp_xf (twon34, twon34_exp)); - - emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (SImode), - CONST1_RTX (SImode))); - - emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34)); - - emit_insn (gen_fixuns_truncxfdi2_alts (op0_di, op0_xf, const1_rtx)); - emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); - DONE; -}) - -(define_expand "umodsi3" - [(set (match_operand:SI 0 "register_operand" "") - (umod:SI (match_operand:SI 1 "general_operand" "") - (match_operand:SI 2 "general_operand" "")))] - "TARGET_INLINE_INT_DIV" -{ - rtx op2_neg, op1_di, div; - - div = gen_reg_rtx (SImode); - emit_insn (gen_udivsi3 (div, operands[1], operands[2])); - - op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0); - - /* This is a trick to get us to reuse the value that we're sure to - have already copied to the FP regs. */ - op1_di = gen_reg_rtx (DImode); - convert_move (op1_di, operands[1], 1); - - emit_insn (gen_maddsi4 (operands[0], div, op2_neg, - gen_lowpart (SImode, op1_di))); - DONE; -}) - -(define_insn_and_split "divsi3_internal" - [(set (match_operand:XF 0 "fr_register_operand" "=&f") - (float:XF (div:SI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") - (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")))) - (clobber (match_scratch:XF 4 "=&f")) - (clobber (match_scratch:XF 5 "=&f")) - (clobber (match_scratch:BI 6 "=c")) - (use (match_operand:XF 3 "fr_register_operand" "f"))] - "TARGET_INLINE_INT_DIV" - "#" - "&& reload_completed" - [(parallel [(set (match_dup 0) (unspec:XF [(const_int 1) (match_dup 2)] - UNSPEC_FR_RECIP_APPROX_RES)) - (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] - UNSPEC_FR_RECIP_APPROX)) - (use (const_int 1))]) - (cond_exec (ne (match_dup 6) (const_int 0)) - (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0))) - (use (const_int 1))])) - (cond_exec (ne (match_dup 6) (const_int 0)) - (parallel [(set (match_dup 5) - (minus:XF (match_dup 7) - (mult:XF (match_dup 2) (match_dup 0)))) - (use (const_int 1))])) - (cond_exec (ne (match_dup 6) (const_int 0)) - (parallel [(set (match_dup 4) - (plus:XF (mult:XF (match_dup 5) (match_dup 4)) - (match_dup 4))) - (use (const_int 1))])) - (cond_exec (ne (match_dup 6) (const_int 0)) - (parallel [(set (match_dup 5) - (plus:XF (mult:XF (match_dup 5) (match_dup 5)) - (match_dup 3))) - (use (const_int 1))])) - (cond_exec (ne (match_dup 6) (const_int 0)) - (parallel [(set (match_dup 0) - (plus:XF (mult:XF (match_dup 5) (match_dup 4)) - (match_dup 4))) - (use (const_int 1))])) - ] - "operands[7] = CONST1_RTX (XFmode);" - [(set_attr "predicable" "no")]) ;; :::::::::::::::::::: ;; :: @@ -2612,215 +2461,6 @@ "" "getf.exp %0 = %F1" [(set_attr "itanium_class" "frfr")]) - -(define_expand "divdi3" - [(set (match_operand:DI 0 "register_operand" "") - (div:DI (match_operand:DI 1 "general_operand" "") - (match_operand:DI 2 "general_operand" "")))] - "TARGET_INLINE_INT_DIV" -{ - rtx op1_xf, op2_xf, op0_xf; - - op0_xf = gen_reg_rtx (XFmode); - - if (CONSTANT_P (operands[1])) - operands[1] = force_reg (DImode, operands[1]); - op1_xf = gen_reg_rtx (XFmode); - expand_float (op1_xf, operands[1], 0); - - if (CONSTANT_P (operands[2])) - operands[2] = force_reg (DImode, operands[2]); - op2_xf = gen_reg_rtx (XFmode); - expand_float (op2_xf, operands[2], 0); - - emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (DImode), - CONST1_RTX (DImode))); - - if (TARGET_INLINE_INT_DIV == INL_MIN_LAT) - emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf)); - else - emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf)); - - emit_insn (gen_fix_truncxfdi2_alts (operands[0], op0_xf, const1_rtx)); - DONE; -}) - -(define_expand "moddi3" - [(set (match_operand:DI 0 "register_operand" "") - (mod:SI (match_operand:DI 1 "general_operand" "") - (match_operand:DI 2 "general_operand" "")))] - "TARGET_INLINE_INT_DIV" -{ - rtx op2_neg, div; - - div = gen_reg_rtx (DImode); - emit_insn (gen_divdi3 (div, operands[1], operands[2])); - - op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0); - - emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); - DONE; -}) - -(define_expand "udivdi3" - [(set (match_operand:DI 0 "register_operand" "") - (udiv:DI (match_operand:DI 1 "general_operand" "") - (match_operand:DI 2 "general_operand" "")))] - "TARGET_INLINE_INT_DIV" -{ - rtx op1_xf, op2_xf, op0_xf; - - op0_xf = gen_reg_rtx (XFmode); - - if (CONSTANT_P (operands[1])) - operands[1] = force_reg (DImode, operands[1]); - op1_xf = gen_reg_rtx (XFmode); - expand_float (op1_xf, operands[1], 1); - - if (CONSTANT_P (operands[2])) - operands[2] = force_reg (DImode, operands[2]); - op2_xf = gen_reg_rtx (XFmode); - expand_float (op2_xf, operands[2], 1); - - emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (DImode), - CONST1_RTX (DImode))); - - if (TARGET_INLINE_INT_DIV == INL_MIN_LAT) - emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf)); - else - emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf)); - - emit_insn (gen_fixuns_truncxfdi2_alts (operands[0], op0_xf, const1_rtx)); - DONE; -}) - -(define_expand "umoddi3" - [(set (match_operand:DI 0 "register_operand" "") - (umod:DI (match_operand:DI 1 "general_operand" "") - (match_operand:DI 2 "general_operand" "")))] - "TARGET_INLINE_INT_DIV" -{ - rtx op2_neg, div; - - div = gen_reg_rtx (DImode); - emit_insn (gen_udivdi3 (div, operands[1], operands[2])); - - op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0); - - emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); - DONE; -}) - -(define_insn_and_split "divdi3_internal_lat" - [(set (match_operand:XF 0 "fr_register_operand" "=&f") - (float:XF (div:SI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") - (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")))) - (clobber (match_scratch:XF 3 "=&f")) - (clobber (match_scratch:XF 4 "=&f")) - (clobber (match_scratch:XF 5 "=&f")) - (clobber (match_scratch:BI 6 "=c"))] - "TARGET_INLINE_INT_DIV == INL_MIN_LAT" - "#" - "&& reload_completed" - [(parallel [(set (match_dup 0) (unspec:XF [(const_int 1) (match_dup 2)] - UNSPEC_FR_RECIP_APPROX_RES)) - (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] - UNSPEC_FR_RECIP_APPROX)) - (use (const_int 1))]) - (cond_exec (ne (match_dup 6) (const_int 0)) - (parallel [(set (match_dup 3) - (minus:XF (match_dup 7) - (mult:XF (match_dup 2) (match_dup 0)))) - (use (const_int 1))])) - (cond_exec (ne (match_dup 6) (const_int 0)) - (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0))) - (use (const_int 1))])) - (cond_exec (ne (match_dup 6) (const_int 0)) - (parallel [(set (match_dup 5) (mult:XF (match_dup 3) (match_dup 3))) - (use (const_int 1))])) - (cond_exec (ne (match_dup 6) (const_int 0)) - (parallel [(set (match_dup 4) - (plus:XF (mult:XF (match_dup 3) (match_dup 4)) - (match_dup 4))) - (use (const_int 1))])) - (cond_exec (ne (match_dup 6) (const_int 0)) - (parallel [(set (match_dup 0) - (plus:XF (mult:XF (match_dup 3) (match_dup 0)) - (match_dup 0))) - (use (const_int 1))])) - (cond_exec (ne (match_dup 6) (const_int 0)) - (parallel [(set (match_dup 3) - (plus:XF (mult:XF (match_dup 5) (match_dup 4)) - (match_dup 4))) - (use (const_int 1))])) - (cond_exec (ne (match_dup 6) (const_int 0)) - (parallel [(set (match_dup 0) - (plus:XF (mult:XF (match_dup 5) (match_dup 0)) - (match_dup 0))) - (use (const_int 1))])) - (cond_exec (ne (match_dup 6) (const_int 0)) - (parallel [(set (match_dup 4) - (minus:XF (match_dup 1) - (mult:XF (match_dup 2) (match_dup 3)))) - (use (const_int 1))])) - (cond_exec (ne (match_dup 6) (const_int 0)) - (parallel [(set (match_dup 0) - (plus:XF (mult:XF (match_dup 4) (match_dup 0)) - (match_dup 3))) - (use (const_int 1))])) - ] - "operands[7] = CONST1_RTX (XFmode);" - [(set_attr "predicable" "no")]) - -(define_insn_and_split "divdi3_internal_thr" - [(set (match_operand:XF 0 "fr_register_operand" "=&f") - (float:XF (div:SI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") - (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")))) - (clobber (match_scratch:XF 3 "=&f")) - (clobber (match_scratch:XF 4 "=f")) - (clobber (match_scratch:BI 5 "=c"))] - "TARGET_INLINE_INT_DIV == INL_MAX_THR" - "#" - "&& reload_completed" - [(parallel [(set (match_dup 0) (unspec:XF [(const_int 1) (match_dup 2)] - UNSPEC_FR_RECIP_APPROX_RES)) - (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] - UNSPEC_FR_RECIP_APPROX)) - (use (const_int 1))]) - (cond_exec (ne (match_dup 5) (const_int 0)) - (parallel [(set (match_dup 3) - (minus:XF (match_dup 6) - (mult:XF (match_dup 2) (match_dup 0)))) - (use (const_int 1))])) - (cond_exec (ne (match_dup 5) (const_int 0)) - (parallel [(set (match_dup 0) - (plus:XF (mult:XF (match_dup 3) (match_dup 0)) - (match_dup 0))) - (use (const_int 1))])) - (cond_exec (ne (match_dup 5) (const_int 0)) - (parallel [(set (match_dup 3) (mult:XF (match_dup 3) (match_dup 3))) - (use (const_int 1))])) - (cond_exec (ne (match_dup 5) (const_int 0)) - (parallel [(set (match_dup 0) - (plus:XF (mult:XF (match_dup 3) (match_dup 0)) - (match_dup 0))) - (use (const_int 1))])) - (cond_exec (ne (match_dup 5) (const_int 0)) - (parallel [(set (match_dup 3) (mult:XF (match_dup 0) (match_dup 1))) - (use (const_int 1))])) - (cond_exec (ne (match_dup 5) (const_int 0)) - (parallel [(set (match_dup 4) - (minus:XF (match_dup 1) - (mult:XF (match_dup 2) (match_dup 3)))) - (use (const_int 1))])) - (cond_exec (ne (match_dup 5) (const_int 0)) - (parallel [(set (match_dup 0) - (plus:XF (mult:XF (match_dup 4) (match_dup 0)) - (match_dup 3))) - (use (const_int 1))])) - ] - "operands[6] = CONST1_RTX (XFmode);" - [(set_attr "predicable" "no")]) ;; :::::::::::::::::::: ;; :: @@ -3135,56 +2775,6 @@ "TARGET_FUSED_MADD" "fnma.s %0 = %F1, %F2, %F3" [(set_attr "itanium_class" "fmac")]) - -(define_insn "*nmaddsf4_alts" - [(set (match_operand:SF 0 "fr_register_operand" "=f") - (minus:SF (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG") - (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") - (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))) - (use (match_operand:SI 4 "const_int_operand" ""))] - "" - "fnma.s.s%4 %0 = %F1, %F2, %F3" - [(set_attr "itanium_class" "fmac")]) - -(define_expand "divsf3" - [(set (match_operand:SF 0 "fr_register_operand" "") - (div:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "") - (match_operand:SF 2 "fr_reg_or_fp01_operand" "")))] - "TARGET_INLINE_FLOAT_DIV" -{ - rtx insn; - if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT) - insn = gen_divsf3_internal_lat (operands[0], operands[1], operands[2]); - else - insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]); - emit_insn (insn); - DONE; -}) - -(define_insn "setf_exp_xf" - [(set (match_operand:XF 0 "fr_register_operand" "=f") - (unspec:XF [(match_operand:DI 1 "register_operand" "r")] - UNSPEC_SETF_EXP))] - "" - "setf.exp %0 = %1" - [(set_attr "itanium_class" "frfr")]) - - -;; Inline square root. - -(define_expand "sqrtsf2" - [(set (match_operand:SF 0 "fr_register_operand" "=&f") - (sqrt:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))] - "TARGET_INLINE_SQRT" -{ - rtx insn; - if (TARGET_INLINE_SQRT == INL_MIN_LAT) - insn = gen_sqrtsf2_internal_lat (operands[0], operands[1]); - else - insn = gen_sqrtsf2_internal_thr (operands[0], operands[1]); - emit_insn (insn); - DONE; -}) ;; :::::::::::::::::::: ;; :: @@ -3362,16 +2952,6 @@ "fnma.d %0 = %F1, %F2, %F3" [(set_attr "itanium_class" "fmac")]) -(define_insn "*nmadddf4_alts" - [(set (match_operand:DF 0 "fr_register_operand" "=f") - (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") - (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") - (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))) - (use (match_operand:SI 4 "const_int_operand" ""))] - "" - "fnma.d.s%4 %0 = %F1, %F2, %F3" - [(set_attr "itanium_class" "fmac")]) - (define_insn "*nmadddf4_truncsf" [(set (match_operand:SF 0 "fr_register_operand" "=f") (float_truncate:SF @@ -3381,50 +2961,6 @@ "TARGET_FUSED_MADD" "fnma.s %0 = %F1, %F2, %F3" [(set_attr "itanium_class" "fmac")]) - -(define_insn "*nmadddf4_truncsf_alts" - [(set (match_operand:SF 0 "fr_register_operand" "=f") - (float_truncate:SF - (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") - (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") - (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))) - (use (match_operand:SI 4 "const_int_operand" ""))] - "" - "fnma.s.s%4 %0 = %F1, %F2, %F3" - [(set_attr "itanium_class" "fmac")]) - -(define_expand "divdf3" - [(set (match_operand:DF 0 "fr_register_operand" "") - (div:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "") - (match_operand:DF 2 "fr_reg_or_fp01_operand" "")))] - "TARGET_INLINE_FLOAT_DIV" -{ - rtx insn; - if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT) - insn = gen_divdf3_internal_lat (operands[0], operands[1], operands[2]); - else - insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]); - emit_insn (insn); - DONE; -}) - -;; Inline square root. - -(define_expand "sqrtdf2" - [(set (match_operand:DF 0 "fr_register_operand" "=&f") - (sqrt:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))] - "TARGET_INLINE_SQRT" -{ - rtx insn; -#if 0 - if (TARGET_INLINE_SQRT == INL_MIN_LAT) - insn = gen_sqrtdf2_internal_lat (operands[0], operands[1]); - else -#endif - insn = gen_sqrtdf2_internal_thr (operands[0], operands[1]); - emit_insn (insn); - DONE; -}) ;; :::::::::::::::::::: ;; :: @@ -3510,35 +3046,6 @@ "fmpy.d %0 = %F1, %F2" [(set_attr "itanium_class" "fmac")]) -(define_insn "*mulxf3_alts" - [(set (match_operand:XF 0 "fr_register_operand" "=f") - (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") - (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))) - (use (match_operand:SI 3 "const_int_operand" ""))] - "" - "fmpy.s%3 %0 = %F1, %F2" - [(set_attr "itanium_class" "fmac")]) - -(define_insn "*mulxf3_truncsf_alts" - [(set (match_operand:SF 0 "fr_register_operand" "=f") - (float_truncate:SF - (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") - (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))) - (use (match_operand:SI 3 "const_int_operand" ""))] - "" - "fmpy.s.s%3 %0 = %F1, %F2" - [(set_attr "itanium_class" "fmac")]) - -(define_insn "*mulxf3_truncdf_alts" - [(set (match_operand:DF 0 "fr_register_operand" "=f") - (float_truncate:DF - (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") - (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))) - (use (match_operand:SI 3 "const_int_operand" ""))] - "" - "fmpy.d.s%3 %0 = %F1, %F2" - [(set_attr "itanium_class" "fmac")]) - (define_insn "absxf2" [(set (match_operand:XF 0 "fr_register_operand" "=f") (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))] @@ -3623,38 +3130,6 @@ "fma.d %0 = %F1, %F2, %F3" [(set_attr "itanium_class" "fmac")]) -(define_insn "*maddxf4_alts" - [(set (match_operand:XF 0 "fr_register_operand" "=f") - (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") - (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) - (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))) - (use (match_operand:SI 4 "const_int_operand" ""))] - "" - "fma.s%4 %0 = %F1, %F2, %F3" - [(set_attr "itanium_class" "fmac")]) - -(define_insn "*maddxf4_alts_truncsf" - [(set (match_operand:SF 0 "fr_register_operand" "=f") - (float_truncate:SF - (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") - (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) - (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))) - (use (match_operand:SI 4 "const_int_operand" ""))] - "" - "fma.s.s%4 %0 = %F1, %F2, %F3" - [(set_attr "itanium_class" "fmac")]) - -(define_insn "*maddxf4_alts_truncdf" - [(set (match_operand:DF 0 "fr_register_operand" "=f") - (float_truncate:DF - (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") - (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) - (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))) - (use (match_operand:SI 4 "const_int_operand" ""))] - "" - "fma.d.s%4 %0 = %F1, %F2, %F3" - [(set_attr "itanium_class" "fmac")]) - (define_insn "*msubxf4" [(set (match_operand:XF 0 "fr_register_operand" "=f") (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") @@ -3743,81 +3218,6 @@ "TARGET_FUSED_MADD" "fnma.d %0 = %F1, %F2, %F3" [(set_attr "itanium_class" "fmac")]) - -(define_insn "*nmaddxf4_alts" - [(set (match_operand:XF 0 "fr_register_operand" "=f") - (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") - (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") - (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") - ))) - (use (match_operand:SI 4 "const_int_operand" ""))] - "" - "fnma.s%4 %0 = %F1, %F2, %F3" - [(set_attr "itanium_class" "fmac")]) - -(define_insn "*nmaddxf4_truncsf_alts" - [(set (match_operand:SF 0 "fr_register_operand" "=f") - (float_truncate:SF - (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") - (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") - (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") - )))) - (use (match_operand:SI 4 "const_int_operand" ""))] - "" - "fnma.s.s%4 %0 = %F1, %F2, %F3" - [(set_attr "itanium_class" "fmac")]) - -(define_insn "*nmaddxf4_truncdf_alts" - [(set (match_operand:DF 0 "fr_register_operand" "=f") - (float_truncate:DF - (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") - (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") - (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") - )))) - (use (match_operand:SI 4 "const_int_operand" ""))] - "" - "fnma.d.s%4 %0 = %F1, %F2, %F3" - [(set_attr "itanium_class" "fmac")]) - -(define_expand "divxf3" - [(set (match_operand:XF 0 "fr_register_operand" "") - (div:XF (match_operand:XF 1 "fr_reg_or_fp01_operand" "") - (match_operand:XF 2 "fr_reg_or_fp01_operand" "")))] - "TARGET_INLINE_FLOAT_DIV" -{ - /* There is only one divxf3 sequence, not two like for divsf and divdf. */ - emit_insn (gen_divxf3_internal (operands[0], operands[1], operands[2])); - DONE; -}) - -;; Inline square root. - -(define_expand "sqrtxf2" - [(set (match_operand:XF 0 "fr_register_operand" "=&f") - (sqrt:XF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))] - "TARGET_INLINE_SQRT" -{ - rtx insn; - insn = gen_sqrtxf2_internal (operands[0], operands[1]); - emit_insn (insn); - DONE; -}) - -;; ??? frcpa works like cmp.foo.unc. - -(define_insn "*recip_approx" - [(set (match_operand:XF 0 "fr_register_operand" "=f") - (unspec:XF [(const_int 1) - (match_operand:XF 3 "fr_reg_or_fp01_operand" "fG")] - UNSPEC_FR_RECIP_APPROX_RES)) - (set (match_operand:BI 1 "register_operand" "=c") - (unspec:BI [(match_operand:XF 2 "fr_reg_or_fp01_operand" "fG") - (match_dup 3)] UNSPEC_FR_RECIP_APPROX)) - (use (match_operand:SI 4 "const_int_operand" ""))] - "" - "frcpa.s%4 %0, %1 = %F2, %F3" - [(set_attr "itanium_class" "fmisc") - (set_attr "predicable" "no")]) ;; :::::::::::::::::::: ;; :: |