aboutsummaryrefslogtreecommitdiff
path: root/gcc/config/i386/sse.md
diff options
context:
space:
mode:
Diffstat (limited to 'gcc/config/i386/sse.md')
-rw-r--r--gcc/config/i386/sse.md525
1 files changed, 251 insertions, 274 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 70c2cf3..ed5ac1a 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -382,8 +382,8 @@
(V2DF "TARGET_AVX512DQ && TARGET_AVX512VL")])
(define_mode_iterator VF1_VF2_AVX10_2
- [(V16SF "TARGET_AVX10_2_512") V8SF V4SF
- (V8DF "TARGET_AVX10_2_512") V4DF V2DF])
+ [(V16SF "TARGET_AVX10_2") V8SF V4SF
+ (V8DF "TARGET_AVX10_2") V4DF V2DF])
(define_mode_iterator VFH
[(V32HF "TARGET_AVX512FP16 && TARGET_EVEX512")
@@ -401,9 +401,9 @@
(V8SF "TARGET_AVX") V4SF
(V8DF "TARGET_AVX512F && TARGET_EVEX512")
(V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")
- (V32BF "TARGET_AVX10_2_512")
- (V16BF "TARGET_AVX10_2_256")
- (V8BF "TARGET_AVX10_2_256")
+ (V32BF "TARGET_AVX10_2")
+ (V16BF "TARGET_AVX10_2")
+ (V8BF "TARGET_AVX10_2")
])
;; 128-, 256- and 512-bit float vector modes for bitwise operations
@@ -447,13 +447,13 @@
[(V8DF "TARGET_AVX512F && TARGET_EVEX512") (V4DF "TARGET_AVX") V2DF])
(define_mode_iterator VF2_AVX10_2
- [(V8DF "TARGET_AVX10_2_512") V4DF V2DF])
+ [(V8DF "TARGET_AVX10_2") V4DF V2DF])
;; All DFmode & HFmode & BFmode vector float modes
(define_mode_iterator VF2HB
- [(V32BF "TARGET_AVX10_2_512")
- (V16BF "TARGET_AVX10_2_256")
- (V8BF "TARGET_AVX10_2_256")
+ [(V32BF "TARGET_AVX10_2")
+ (V16BF "TARGET_AVX10_2")
+ (V8BF "TARGET_AVX10_2")
(V32HF "TARGET_AVX512FP16 && TARGET_EVEX512")
(V16HF "TARGET_AVX512FP16 && TARGET_AVX512VL")
(V8HF "TARGET_AVX512FP16 && TARGET_AVX512VL")
@@ -511,10 +511,10 @@
(V8DI "TARGET_EVEX512") (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")])
(define_mode_iterator VI1248_AVX10_2
- [(V64QI "TARGET_AVX10_2_512") V32QI V16QI
- (V32HI "TARGET_AVX10_2_512") V16HI V8HI
- (V16SI "TARGET_AVX10_2_512") V8SI V4SI
- (V8DI "TARGET_AVX10_2_512") V4DI V2DI])
+ [(V64QI "TARGET_AVX10_2") V32QI V16QI
+ (V32HI "TARGET_AVX10_2") V16HI V8HI
+ (V16SI "TARGET_AVX10_2") V8SI V4SI
+ (V8DI "TARGET_AVX10_2") V4DI V2DI])
(define_mode_iterator VF_AVX512VL
[(V16SF "TARGET_EVEX512") (V8SF "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL")
@@ -528,9 +528,9 @@
(V8DF "TARGET_EVEX512") (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")])
(define_mode_iterator VFH_AVX10_2
- [(V32HF "TARGET_AVX10_2_512") V16HF V8HF
- (V16SF "TARGET_AVX10_2_512") V8SF V4SF
- (V8DF "TARGET_AVX10_2_512") V4DF V2DF])
+ [(V32HF "TARGET_AVX10_2") V16HF V8HF
+ (V16SF "TARGET_AVX10_2") V8SF V4SF
+ (V8DF "TARGET_AVX10_2") V4DF V2DF])
(define_mode_iterator VF2_AVX512VL
[(V8DF "TARGET_EVEX512") (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")])
@@ -542,7 +542,7 @@
[(V16SF "TARGET_AVX512BW && TARGET_EVEX512") (V8SF "TARGET_AVX2") V4SF])
(define_mode_iterator VF1_AVX10_2
- [(V16SF "TARGET_AVX10_2_512") V8SF V4SF])
+ [(V16SF "TARGET_AVX10_2") V8SF V4SF])
(define_mode_iterator VHFBF
[(V32HF "TARGET_EVEX512") V16HF V8HF
@@ -558,10 +558,10 @@
(V32BF "TARGET_EVEX512") (V16BF "TARGET_AVX512VL") (V8BF "TARGET_AVX512VL")])
(define_mode_iterator VHF_AVX10_2
- [(V32HF "TARGET_AVX10_2_512") V16HF V8HF])
+ [(V32HF "TARGET_AVX10_2") V16HF V8HF])
(define_mode_iterator VBF_AVX10_2
- [(V32BF "TARGET_AVX10_2_512") V16BF V8BF])
+ [(V32BF "TARGET_AVX10_2") V16BF V8BF])
;; All vector integer modes
(define_mode_iterator VI
@@ -614,7 +614,7 @@
[(V8DI "TARGET_AVX512F && TARGET_EVEX512") (V4DI "TARGET_AVX") V2DI])
(define_mode_iterator VI8_AVX10_2
- [(V8DI "TARGET_AVX10_2_512") V4DI V2DI])
+ [(V8DI "TARGET_AVX10_2") V4DI V2DI])
(define_mode_iterator VI8_FVL
[(V8DI "TARGET_AVX512F && TARGET_EVEX512") V4DI (V2DI "TARGET_AVX512VL")])
@@ -659,7 +659,7 @@
(V16HI "TARGET_AVX2") V8HI])
(define_mode_iterator VI2_AVX10_2
- [(V32HI "TARGET_AVX10_2_512") V16HI V8HI])
+ [(V32HI "TARGET_AVX10_2") V16HI V8HI])
(define_mode_iterator VI4_AVX
[(V8SI "TARGET_AVX") V4SI])
@@ -674,7 +674,7 @@
[(V16SI "TARGET_EVEX512") (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL")])
(define_mode_iterator VI4_AVX10_2
- [(V16SI "TARGET_AVX10_2_512") V8SI V4SI])
+ [(V16SI "TARGET_AVX10_2") V8SI V4SI])
(define_mode_iterator VI48_AVX512F_AVX512VL
[V4SI V8SI (V16SI "TARGET_AVX512F && TARGET_EVEX512")
@@ -2649,7 +2649,7 @@
(plusminus:VF_BHSD
(match_operand:VF_BHSD 1 "<round_nimm_predicate>")
(match_operand:VF_BHSD 2 "<round_nimm_predicate>")))]
- "TARGET_SSE && <mask_mode512bit_condition> && <round_mode_condition>"
+ "TARGET_SSE && <mask_mode512bit_condition> && <round_mode512bit_condition>"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(define_insn "*<insn><mode>3<mask_name><round_name>"
@@ -2658,7 +2658,7 @@
(match_operand:VFH 1 "<bcst_round_nimm_predicate>" "<comm>0,v")
(match_operand:VFH 2 "<bcst_round_nimm_predicate>" "xBm,<bcst_round_constraint>")))]
"TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
- && <mask_mode512bit_condition> && <round_mode_condition>"
+ && <mask_mode512bit_condition> && <round_mode512bit_condition>"
"@
<plusminus_mnemonic><ssemodesuffix>\t{%2, %0|%0, %2}
v<plusminus_mnemonic><ssemodesuffix>\t{<round_mask_op3>%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2<round_mask_op3>}"
@@ -2738,7 +2738,7 @@
(mult:VF_BHSD
(match_operand:VF_BHSD 1 "<round_nimm_predicate>")
(match_operand:VF_BHSD 2 "<round_nimm_predicate>")))]
- "TARGET_SSE && <mask_mode512bit_condition> && <round_mode_condition>"
+ "TARGET_SSE && <mask_mode512bit_condition> && <round_mode512bit_condition>"
"ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);")
(define_insn "*mul<mode>3<mask_name><round_name>"
@@ -2747,7 +2747,7 @@
(match_operand:VFH 1 "<bcst_round_nimm_predicate>" "%0,v")
(match_operand:VFH 2 "<bcst_round_nimm_predicate>" "xBm,<bcst_round_constraint>")))]
"TARGET_SSE && ix86_binary_operator_ok (MULT, <MODE>mode, operands)
- && <mask_mode512bit_condition> && <round_mode_condition>"
+ && <mask_mode512bit_condition> && <round_mode512bit_condition>"
"@
mul<ssemodesuffix>\t{%2, %0|%0, %2}
vmul<ssemodesuffix>\t{<round_mask_op3>%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2<round_mask_op3>}"
@@ -2857,7 +2857,7 @@
(div:VBF_AVX10_2
(match_operand:VBF_AVX10_2 1 "register_operand")
(match_operand:VBF_AVX10_2 2 "vector_operand")))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
{
if (TARGET_RECIP_VEC_DIV
&& optimize_insn_for_speed_p ()
@@ -2895,7 +2895,7 @@
(div:VFH
(match_operand:VFH 1 "register_operand" "0,v")
(match_operand:VFH 2 "<bcst_round_nimm_predicate>" "xBm,<bcst_round_constraint>")))]
- "TARGET_SSE && <mask_mode512bit_condition> && <round_mode_condition>"
+ "TARGET_SSE && <mask_mode512bit_condition> && <round_mode512bit_condition>"
"@
div<ssemodesuffix>\t{%2, %0|%0, %2}
vdiv<ssemodesuffix>\t{<round_mask_op3>%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2<round_mask_op3>}"
@@ -3061,7 +3061,7 @@
(define_insn "<sse>_sqrt<mode>2<mask_name><round_name>"
[(set (match_operand:VFH 0 "register_operand" "=x,v")
(sqrt:VFH (match_operand:VFH 1 "<round_nimm_predicate>" "xBm,<round_constraint>")))]
- "TARGET_SSE && <mask_mode512bit_condition> && <round_mode_condition>"
+ "TARGET_SSE && <mask_mode512bit_condition> && <round_mode512bit_condition>"
"@
sqrt<ssemodesuffix>\t{%1, %0|%0, %1}
vsqrt<ssemodesuffix>\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
@@ -3277,7 +3277,7 @@
(match_operand:VFH 1 "<round_saeonly_nimm_predicate>")
(match_operand:VFH 2 "<round_saeonly_nimm_predicate>")))]
"TARGET_SSE && <mask_mode512bit_condition>
- && <round_saeonly_mode_condition>"
+ && <round_saeonly_mode512bit_condition>"
{
if (!flag_finite_math_only || flag_signed_zeros)
{
@@ -3305,7 +3305,7 @@
"TARGET_SSE
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))
&& <mask_mode512bit_condition>
- && <round_saeonly_mode_condition>"
+ && <round_saeonly_mode512bit_condition>"
"@
<maxmin_float><ssemodesuffix>\t{%2, %0|%0, %2}
v<maxmin_float><ssemodesuffix>\t{<round_saeonly_mask_op3>%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2<round_saeonly_mask_op3>}"
@@ -3392,7 +3392,7 @@
IEEE_MAXMIN))]
"TARGET_SSE
&& <mask_mode512bit_condition>
- && <round_saeonly_mode_condition>"
+ && <round_saeonly_mode512bit_condition>"
"@
<ieee_maxmin><ssemodesuffix>\t{%2, %0|%0, %2}
v<ieee_maxmin><ssemodesuffix>\t{<round_saeonly_mask_op3>%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2<round_saeonly_mask_op3>}"
@@ -4021,7 +4021,7 @@
[(match_operand:VFH_AVX512VL 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")
(match_operand:SI 2 "const_0_to_255_operand")]
UNSPEC_REDUCE))]
- "(TARGET_AVX512DQ || (VALID_AVX512FP16_REG_MODE (<MODE>mode))) && <round_saeonly_mode_condition>"
+ "TARGET_AVX512DQ || (VALID_AVX512FP16_REG_MODE (<MODE>mode))"
"vreduce<ssemodesuffix>\t{%2, <round_saeonly_mask_op3>%1, %0<mask_operand3>|%0<mask_operand3>, %1<round_saeonly_mask_op3>, %2}"
[(set_attr "type" "sse")
(set_attr "prefix" "evex")
@@ -4391,7 +4391,7 @@
(match_operand:V48H_AVX512VL 2 "nonimmediate_operand" "<round_saeonly_constraint>")
(match_operand:SI 3 "<cmp_imm_predicate>" "n")]
UNSPEC_PCMP))]
- "TARGET_AVX512F && <round_saeonly_mode_condition>"
+ "TARGET_AVX512F && <round_saeonly_mode512bit_condition>"
"v<ssecmpintprefix>cmp<ssemodesuffix>\t{%3, <round_saeonly_mask_scalar_merge_op4>%2, %1, %0<mask_scalar_merge_operand4>|%0<mask_scalar_merge_operand4>, %1, %2<round_saeonly_mask_scalar_merge_op4>, %3}"
[(set_attr "type" "ssecmp")
(set_attr "length_immediate" "1")
@@ -4850,7 +4850,7 @@
(match_operand:<ssevecmode> 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>")
(parallel [(const_int 0)]))]
UNSPEC_COMX))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"v<unord>comx<ssemodesuffix>\t{<round_saeonly_op2>%1, %0|%0, %<iptr>1<round_saeonly_op2>}"
[(set_attr "type" "ssecomi")
(set_attr "prefix" "evex")
@@ -4885,7 +4885,7 @@
(vec_select:BF
(match_operand:V8BF 1 "nonimmediate_operand" "vm")
(parallel [(const_int 0)]))))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vcomisbf16\t{%1, %0|%0, %1}"
[(set_attr "prefix" "evex")
(set_attr "type" "ssecomi")])
@@ -4921,7 +4921,7 @@
(match_operator:<avx512fmaskmode> 1 ""
[(match_operand:VBF_AVX10_2 2 "register_operand")
(match_operand:VBF_AVX10_2 3 "nonimmediate_operand")]))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
{
bool ok = ix86_expand_mask_vec_cmp (operands[0], GET_CODE (operands[1]),
operands[2], operands[3]);
@@ -5813,9 +5813,9 @@
(V8HF "TARGET_AVX512FP16 && TARGET_AVX512VL")
(V16HF "TARGET_AVX512FP16 && TARGET_AVX512VL")
(V32HF "TARGET_AVX512FP16 && TARGET_EVEX512")
- (V8BF "TARGET_AVX10_2_256")
- (V16BF "TARGET_AVX10_2_256")
- (V32BF "TARGET_AVX10_2_512")])
+ (V8BF "TARGET_AVX10_2")
+ (V16BF "TARGET_AVX10_2")
+ (V32BF "TARGET_AVX10_2")])
(define_expand "fma<mode>4"
[(set (match_operand:FMAMODEM 0 "register_operand")
@@ -5897,7 +5897,7 @@
(match_operand:VFH_AVX512VL 2 "<round_expand_nimm_predicate>")
(match_operand:VFH_AVX512VL 3 "<round_expand_nimm_predicate>")
(match_operand:<avx512fmaskmode> 4 "register_operand")]
- "TARGET_AVX512F && <round_mode_condition>"
+ "TARGET_AVX512F && <round_mode512bit_condition>"
{
emit_insn (gen_fma_fmadd_<mode>_maskz_1<round_expand_name> (
operands[0], operands[1], operands[2], operands[3],
@@ -5939,7 +5939,7 @@
(match_operand:VFH_SF_AVX512VL 1 "<bcst_round_nimm_predicate>" "%0,0,v")
(match_operand:VFH_SF_AVX512VL 2 "<bcst_round_nimm_predicate>" "<bcst_round_constraint>,v,<bcst_round_constraint>")
(match_operand:VFH_SF_AVX512VL 3 "<bcst_round_nimm_predicate>" "v,<bcst_round_constraint>,0")))]
- "TARGET_AVX512F && <sd_mask_mode512bit_condition> && <round_mode_condition>"
+ "TARGET_AVX512F && <sd_mask_mode512bit_condition> && <round_mode512bit_condition>"
"@
vfmadd132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>}
vfmadd213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>}
@@ -5980,7 +5980,7 @@
(match_operand:VFH_AVX512VL 3 "<round_nimm_predicate>" "v,<round_constraint>"))
(match_dup 1)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk,Yk")))]
- "TARGET_AVX512F && <round_mode_condition>"
+ "TARGET_AVX512F && <round_mode512bit_condition>"
"@
vfmadd132<ssemodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %3, %2<round_op5>}
vfmadd213<ssemodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %2, %3<round_op5>}"
@@ -5997,7 +5997,7 @@
(match_operand:VFH_AVX512VL 3 "nonimmediate_operand" "0"))
(match_dup 3)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
- "TARGET_AVX512F && <round_mode_condition>"
+ "TARGET_AVX512F"
"vfmadd231<ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
[(set_attr "type" "ssemuladd")
(set_attr "prefix" "evex")
@@ -6027,7 +6027,7 @@
(match_operand:VFH_AVX512VL 2 "<round_expand_nimm_predicate>")
(match_operand:VFH_AVX512VL 3 "<round_expand_nimm_predicate>")
(match_operand:<avx512fmaskmode> 4 "register_operand")]
- "TARGET_AVX512F && <round_mode_condition>"
+ "TARGET_AVX512F && <round_mode512bit_condition>"
{
emit_insn (gen_fma_fmsub_<mode>_maskz_1<round_expand_name> (
operands[0], operands[1], operands[2], operands[3],
@@ -6042,7 +6042,7 @@
(match_operand:VFH_SF_AVX512VL 2 "<bcst_round_nimm_predicate>" "<bcst_round_constraint>,v,<bcst_round_constraint>")
(neg:VFH_SF_AVX512VL
(match_operand:VFH_SF_AVX512VL 3 "<bcst_round_nimm_predicate>" "v,<bcst_round_constraint>,0"))))]
- "TARGET_AVX512F && <sd_mask_mode512bit_condition> && <round_mode_condition>"
+ "TARGET_AVX512F && <sd_mask_mode512bit_condition> && <round_mode512bit_condition>"
"@
vfmsub132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>}
vfmsub213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>}
@@ -6085,7 +6085,7 @@
(match_operand:VFH_AVX512VL 3 "<round_nimm_predicate>" "v,<round_constraint>")))
(match_dup 1)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk,Yk")))]
- "TARGET_AVX512F && <round_mode_condition>"
+ "TARGET_AVX512F"
"@
vfmsub132<ssemodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %3, %2<round_op5>}
vfmsub213<ssemodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %2, %3<round_op5>}"
@@ -6103,7 +6103,7 @@
(match_operand:VFH_AVX512VL 3 "nonimmediate_operand" "0")))
(match_dup 3)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
- "TARGET_AVX512F && <round_mode_condition>"
+ "TARGET_AVX512F && <round_mode512bit_condition>"
"vfmsub231<ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
[(set_attr "type" "ssemuladd")
(set_attr "prefix" "evex")
@@ -6133,7 +6133,7 @@
(match_operand:VFH_AVX512VL 2 "<round_expand_nimm_predicate>")
(match_operand:VFH_AVX512VL 3 "<round_expand_nimm_predicate>")
(match_operand:<avx512fmaskmode> 4 "register_operand")]
- "TARGET_AVX512F && <round_mode_condition>"
+ "TARGET_AVX512F && <round_mode512bit_condition>"
{
emit_insn (gen_fma_fnmadd_<mode>_maskz_1<round_expand_name> (
operands[0], operands[1], operands[2], operands[3],
@@ -6148,7 +6148,7 @@
(match_operand:VFH_SF_AVX512VL 1 "<bcst_round_nimm_predicate>" "%0,0,v"))
(match_operand:VFH_SF_AVX512VL 2 "<bcst_round_nimm_predicate>" "<bcst_round_constraint>,v,<bcst_round_constraint>")
(match_operand:VFH_SF_AVX512VL 3 "<bcst_round_nimm_predicate>" "v,<bcst_round_constraint>,0")))]
- "TARGET_AVX512F && <sd_mask_mode512bit_condition> && <round_mode_condition>"
+ "TARGET_AVX512F && <sd_mask_mode512bit_condition> && <round_mode512bit_condition>"
"@
vfnmadd132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>}
vfnmadd213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>}
@@ -6191,7 +6191,7 @@
(match_operand:VFH_AVX512VL 3 "<round_nimm_predicate>" "v,<round_constraint>"))
(match_dup 1)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk,Yk")))]
- "TARGET_AVX512F && <round_mode_condition>"
+ "TARGET_AVX512F && <round_mode512bit_condition>"
"@
vfnmadd132<ssemodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %3, %2<round_op5>}
vfnmadd213<ssemodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %2, %3<round_op5>}"
@@ -6209,7 +6209,7 @@
(match_operand:VFH_AVX512VL 3 "nonimmediate_operand" "0"))
(match_dup 3)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
- "TARGET_AVX512F && <round_mode_condition>"
+ "TARGET_AVX512F && <round_mode512bit_condition>"
"vfnmadd231<ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
[(set_attr "type" "ssemuladd")
(set_attr "prefix" "evex")
@@ -6240,7 +6240,7 @@
(match_operand:VFH_AVX512VL 2 "<round_expand_nimm_predicate>")
(match_operand:VFH_AVX512VL 3 "<round_expand_nimm_predicate>")
(match_operand:<avx512fmaskmode> 4 "register_operand")]
- "TARGET_AVX512F && <round_mode_condition>"
+ "TARGET_AVX512F && <round_mode512bit_condition>"
{
emit_insn (gen_fma_fnmsub_<mode>_maskz_1<round_expand_name> (
operands[0], operands[1], operands[2], operands[3],
@@ -6256,7 +6256,7 @@
(match_operand:VFH_SF_AVX512VL 2 "<bcst_round_nimm_predicate>" "<bcst_round_constraint>,v,<bcst_round_constraint>")
(neg:VFH_SF_AVX512VL
(match_operand:VFH_SF_AVX512VL 3 "<bcst_round_nimm_predicate>" "v,<bcst_round_constraint>,0"))))]
- "TARGET_AVX512F && <sd_mask_mode512bit_condition> && <round_mode_condition>"
+ "TARGET_AVX512F && <sd_mask_mode512bit_condition> && <round_mode512bit_condition>"
"@
vfnmsub132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>}
vfnmsub213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>}
@@ -6301,7 +6301,7 @@
(match_operand:VFH_AVX512VL 3 "<round_nimm_predicate>" "v,<round_constraint>")))
(match_dup 1)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk,Yk")))]
- "TARGET_AVX512F && <round_mode_condition>"
+ "TARGET_AVX512F && <round_mode512bit_condition>"
"@
vfnmsub132<ssemodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %3, %2<round_op5>}
vfnmsub213<ssemodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %2, %3<round_op5>}"
@@ -6320,7 +6320,7 @@
(match_operand:VFH_AVX512VL 3 "nonimmediate_operand" "0")))
(match_dup 3)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
- "TARGET_AVX512F && <round_mode_condition>"
+ "TARGET_AVX512F"
"vfnmsub231<ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
[(set_attr "type" "ssemuladd")
(set_attr "prefix" "evex")
@@ -6418,7 +6418,7 @@
(match_operand:VFH_AVX512VL 2 "<round_nimm_predicate>" "<round_constraint>,v,<round_constraint>")
(match_operand:VFH_AVX512VL 3 "<round_nimm_predicate>" "v,<round_constraint>,0")]
UNSPEC_FMADDSUB))]
- "TARGET_AVX512F && <sd_mask_mode512bit_condition> && <round_mode_condition>"
+ "TARGET_AVX512F && <sd_mask_mode512bit_condition> && <round_mode512bit_condition>"
"@
vfmaddsub132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>}
vfmaddsub213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>}
@@ -6437,7 +6437,7 @@
UNSPEC_FMADDSUB)
(match_dup 1)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk,Yk")))]
- "TARGET_AVX512F && <round_mode_condition>"
+ "TARGET_AVX512F"
"@
vfmaddsub132<ssemodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %3, %2<round_op5>}
vfmaddsub213<ssemodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %2, %3<round_op5>}"
@@ -6455,7 +6455,7 @@
UNSPEC_FMADDSUB)
(match_dup 3)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
- "TARGET_AVX512F && <round_mode_condition>"
+ "TARGET_AVX512F"
"vfmaddsub231<ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
[(set_attr "type" "ssemuladd")
(set_attr "prefix" "evex")
@@ -6488,7 +6488,7 @@
(neg:VFH_AVX512VL
(match_operand:VFH_AVX512VL 3 "<round_nimm_predicate>" "v,<round_constraint>,0"))]
UNSPEC_FMADDSUB))]
- "TARGET_AVX512F && <sd_mask_mode512bit_condition> && <round_mode_condition>"
+ "TARGET_AVX512F && <sd_mask_mode512bit_condition> && <round_mode512bit_condition>"
"@
vfmsubadd132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>}
vfmsubadd213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>}
@@ -7057,7 +7057,7 @@
(match_operand:VHF_AVX512VL 2 "<round_expand_nimm_predicate>")
(match_operand:VHF_AVX512VL 3 "<round_expand_nimm_predicate>")
(match_operand:<avx512fmaskcmode> 4 "register_operand")]
- "TARGET_AVX512FP16 && <round_mode_condition>"
+ "TARGET_AVX512FP16 && <round_mode512bit_condition>"
{
rtx op0, op1, dest;
if (<round_embedded_complex>)
@@ -7087,7 +7087,7 @@
(match_operand:VHF_AVX512VL 2 "<round_expand_nimm_predicate>")
(match_operand:VHF_AVX512VL 3 "<round_expand_nimm_predicate>")
(match_operand:<avx512fmaskcmode> 4 "register_operand")]
- "TARGET_AVX512FP16 && <round_mode_condition>"
+ "TARGET_AVX512FP16 && <round_mode512bit_condition>"
{
emit_insn (gen_fma_fmaddc_<mode>_maskz_1<round_expand_name> (
operands[0], operands[1], operands[2], operands[3],
@@ -7101,7 +7101,7 @@
(match_operand:VHF_AVX512VL 2 "<round_expand_nimm_predicate>")
(match_operand:VHF_AVX512VL 3 "<round_expand_nimm_predicate>")
(match_operand:<avx512fmaskcmode> 4 "register_operand")]
- "TARGET_AVX512FP16 && <round_mode_condition>"
+ "TARGET_AVX512FP16 && <round_mode512bit_condition>"
{
rtx op0, op1, dest;
if (<round_embedded_complex>)
@@ -7133,7 +7133,7 @@
(match_operand:VHF_AVX512VL 2 "<round_expand_nimm_predicate>")
(match_operand:VHF_AVX512VL 3 "<round_expand_nimm_predicate>")
(match_operand:<avx512fmaskcmode> 4 "register_operand")]
- "TARGET_AVX512FP16 && <round_mode_condition>"
+ "TARGET_AVX512FP16 && <round_mode512bit_condition>"
{
emit_insn (gen_fma_fcmaddc_<mode>_maskz_1<round_expand_name> (
operands[0], operands[1], operands[2], operands[3],
@@ -7157,7 +7157,7 @@
(match_operand:VHF_AVX512VL 2 "<round_nimm_predicate>" "<round_constraint>")
(match_operand:VHF_AVX512VL 3 "<round_nimm_predicate>" "0")]
UNSPEC_COMPLEX_F_C_MA))]
- "TARGET_AVX512FP16 && <sdc_mask_mode512bit_condition> && <round_mode_condition>"
+ "TARGET_AVX512FP16 && <sdc_mask_mode512bit_condition> && <round_mode512bit_condition>"
"v<complexopname><ssemodesuffix>\t{<round_sdc_mask_op4>%2, %1, %0<sdc_mask_op4>|%0<sdc_mask_op4>, %1, %2<round_sdc_mask_op4>}"
[(set_attr "type" "ssemuladd")
(set_attr "prefix" "evex")
@@ -7295,7 +7295,7 @@
(unspec:<avx512fmaskmode>
[(match_operand:<avx512fmaskcmode> 4 "register_operand" "Yk")]
UNSPEC_COMPLEX_MASK)))]
- "TARGET_AVX512FP16 && <round_mode_condition>"
+ "TARGET_AVX512FP16 && <round_mode512bit_condition>"
"v<complexopname><ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
[(set_attr "type" "ssemuladd")
(set_attr "prefix" "evex")
@@ -7315,7 +7315,7 @@
[(match_operand:VHF_AVX512VL 1 "<round_nimm_predicate>" "<int_comm>v")
(match_operand:VHF_AVX512VL 2 "<round_nimm_predicate>" "<round_constraint>")]
UNSPEC_COMPLEX_F_C_MUL))]
- "TARGET_AVX512FP16 && <round_mode_condition>"
+ "TARGET_AVX512FP16 && <round_mode512bit_condition>"
{
if (TARGET_DEST_FALSE_DEP_FOR_GLC
&& <maskc_dest_false_dep_for_glc_cond>)
@@ -7332,7 +7332,7 @@
(match_operand:V8HF 2 "<round_expand_nimm_predicate>")
(match_operand:V8HF 3 "<round_expand_nimm_predicate>")
(match_operand:QI 4 "register_operand")]
- "TARGET_AVX512FP16 && <round_mode_condition>"
+ "TARGET_AVX512FP16 && <round_mode512bit_condition>"
{
emit_insn (gen_avx512fp16_fma_fmaddcsh_v8hf_maskz<round_expand_name> (
operands[0], operands[1], operands[2], operands[3],
@@ -7346,7 +7346,7 @@
(match_operand:V8HF 2 "<round_expand_nimm_predicate>")
(match_operand:V8HF 3 "<round_expand_nimm_predicate>")
(match_operand:QI 4 "register_operand")]
- "TARGET_AVX512FP16 && <round_mode_condition>"
+ "TARGET_AVX512FP16 && <round_mode512bit_condition>"
{
rtx op0, op1, dest;
@@ -7376,7 +7376,7 @@
(match_operand:V8HF 2 "<round_expand_nimm_predicate>")
(match_operand:V8HF 3 "<round_expand_nimm_predicate>")
(match_operand:QI 4 "register_operand")]
- "TARGET_AVX512FP16 && <round_mode_condition>"
+ "TARGET_AVX512FP16 && <round_mode512bit_condition>"
{
emit_insn (gen_avx512fp16_fma_fcmaddcsh_v8hf_maskz<round_expand_name> (
operands[0], operands[1], operands[2], operands[3],
@@ -7390,7 +7390,7 @@
(match_operand:V8HF 2 "<round_expand_nimm_predicate>")
(match_operand:V8HF 3 "<round_expand_nimm_predicate>")
(match_operand:QI 4 "register_operand")]
- "TARGET_AVX512FP16 && <round_mode_condition>"
+ "TARGET_AVX512FP16 && <round_mode512bit_condition>"
{
rtx op0, op1, dest;
@@ -7420,7 +7420,7 @@
(match_operand:V8HF 2 "<round_expand_nimm_predicate>")
(match_operand:V8HF 3 "<round_expand_nimm_predicate>")
(match_operand:QI 4 "register_operand")]
- "TARGET_AVX512FP16 && <round_mode_condition>"
+ "TARGET_AVX512FP16 && <round_mode512bit_condition>"
{
rtx dest, op0, op1;
@@ -7450,7 +7450,7 @@
(match_operand:V8HF 2 "<round_expand_nimm_predicate>")
(match_operand:V8HF 3 "<round_expand_nimm_predicate>")
(match_operand:QI 4 "register_operand")]
- "TARGET_AVX512FP16 && <round_mode_condition>"
+ "TARGET_AVX512FP16 && <round_mode512bit_condition>"
{
rtx dest, op0, op1;
@@ -7627,7 +7627,7 @@
(unspec:VI248_AVX512VL
[(match_operand:<ssePHmode> 1 "<round_nimm_predicate>" "<round_constraint>")]
UNSPEC_US_FIX_NOTRUNC))]
- "TARGET_AVX512FP16 && <round_mode_condition>"
+ "TARGET_AVX512FP16"
"vcvtph2<sseintconvertsignprefix><sseintconvert>\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %<iptrh>1<round_mask_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
@@ -7643,7 +7643,7 @@
[(set (match_operand:<ssePHmode> 0 "register_operand" "=v")
(any_float:<ssePHmode>
(match_operand:VI2H_AVX512VL 1 "<round_nimm_predicate>" "<round_constraint>")))]
- "TARGET_AVX512FP16 && <round_mode_condition>"
+ "TARGET_AVX512FP16"
"vcvt<floatsuffix><sseintconvert>2ph<round_qq2phsuff>\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
@@ -7681,19 +7681,6 @@
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
-(define_expand "avx512fp16_vcvt<floatsuffix>qq2ph_v4di_mask_round"
- [(match_operand:V8HF 0 "register_operand")
- (any_float:V4HF (match_operand:V4DI 1 "register_operand"))
- (match_operand:V8HF 2 "nonimm_or_0_operand")
- (match_operand:QI 3 "register_operand")
- (unspec [(match_operand:SI 4 "const_4_or_8_to_11_operand")] UNSPEC_EMBEDDED_ROUNDING)]
- "TARGET_AVX10_2_256"
-{
- emit_insn (gen_avx512fp16_vcvt<floatsuffix>qq2ph_v4di_mask_round_1 (
- operands[0], operands[1], operands[2], operands[3], CONST0_RTX (V4HFmode), operands[4]));
- DONE;
-})
-
(define_expand "avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode>_mask"
[(set (match_operand:V8HF 0 "register_operand" "=v")
(vec_concat:V8HF
@@ -7707,18 +7694,18 @@
"TARGET_AVX512FP16 && TARGET_AVX512VL"
"operands[4] = CONST0_RTX (V4HFmode);")
-(define_insn "avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode>_mask<round_name>_1"
+(define_insn "*avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode>_mask"
[(set (match_operand:V8HF 0 "register_operand" "=v")
(vec_concat:V8HF
(vec_merge:V4HF
- (any_float:V4HF (match_operand:VI4_128_8_256 1 "<round_nimm_predicate>" "<round_constraint>"))
+ (any_float:V4HF (match_operand:VI4_128_8_256 1 "vector_operand" "vm"))
(vec_select:V4HF
(match_operand:V8HF 2 "nonimm_or_0_operand" "0C")
(parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)]))
(match_operand:QI 3 "register_operand" "Yk"))
(match_operand:V4HF 4 "const0_operand")))]
- "TARGET_AVX512FP16 && TARGET_AVX512VL && <round_mode_condition>"
- "vcvt<floatsuffix><sseintconvert>2ph<round_qq2phsuff>\t{<round_op5>%1, %0%{%3%}%N2|%0%{%3%}%N2, %1<round_op5>}"
+ "TARGET_AVX512FP16 && TARGET_AVX512VL"
+ "vcvt<floatsuffix><sseintconvert>2ph<qq2phsuff>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -7865,7 +7852,7 @@
(unspec:VI2H_AVX512VL
[(match_operand:<ssePHmode> 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")]
UNSPEC_VCVTT_U))]
- "TARGET_AVX512FP16 && <round_saeonly_mode_condition>"
+ "TARGET_AVX512FP16"
"vcvttph2<vcvtt_suffix><sseintconvert>\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
@@ -7875,7 +7862,7 @@
[(set (match_operand:VI2H_AVX512VL 0 "register_operand" "=v")
(any_fix:VI2H_AVX512VL
(match_operand:<ssePHmode> 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")))]
- "TARGET_AVX512FP16 && <round_saeonly_mode_condition>"
+ "TARGET_AVX512FP16"
"vcvttph2<fixsuffix><sseintconvert>\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
@@ -7898,13 +7885,13 @@
}
})
-(define_insn "unspec_avx512fp16_fix<vcvtt_uns_suffix>_trunc<mode>2<mask_name><round_saeonly_name>"
+(define_insn "unspec_avx512fp16_fix<vcvtt_uns_suffix>_trunc<mode>2<mask_name>"
[(set (match_operand:VI4_128_8_256 0 "register_operand" "=v")
(unspec:VI4_128_8_256
[(match_operand:V8HF 1 "register_operand" "v")]
UNSPEC_VCVTT_U))]
- "TARGET_AVX512FP16 && TARGET_AVX512VL && <round_saeonly_mode_condition>"
- "vcvttph2<vcvtt_suffix><sseintconvert>\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
+ "TARGET_AVX512FP16 && TARGET_AVX512VL"
+ "vcvttph2<vcvtt_suffix><sseintconvert>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -8028,7 +8015,7 @@
[(set (match_operand:VF48H_AVX512VL 0 "register_operand" "=v")
(float_extend:VF48H_AVX512VL
(match_operand:<ssePHmode> 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")))]
- "TARGET_AVX512FP16 && <round_saeonly_mode_condition>"
+ "TARGET_AVX512FP16"
"vcvtph2<castmode><ph2pssuffix>\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
@@ -8051,14 +8038,14 @@
}
})
-(define_insn "avx512fp16_float_extend_ph<mode>2<mask_name><round_saeonly_name>"
+(define_insn "avx512fp16_float_extend_ph<mode>2<mask_name>"
[(set (match_operand:VF4_128_8_256 0 "register_operand" "=v")
(float_extend:VF4_128_8_256
(vec_select:V4HF
(match_operand:V8HF 1 "register_operand" "v")
(parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)]))))]
- "TARGET_AVX512FP16 && TARGET_AVX512VL && <round_saeonly_mode_condition>"
- "vcvtph2<castmode><ph2pssuffix>\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %q1<round_saeonly_mask_op2>}"
+ "TARGET_AVX512FP16 && TARGET_AVX512VL"
+ "vcvtph2<castmode><ph2pssuffix>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -8122,7 +8109,7 @@
[(set (match_operand:<ssePHmode> 0 "register_operand" "=v")
(float_truncate:<ssePHmode>
(match_operand:VF48H_AVX512VL 1 "<round_nimm_predicate>" "<round_constraint>")))]
- "TARGET_AVX512FP16 && <round_mode_condition>"
+ "TARGET_AVX512FP16"
"vcvt<castmode>2ph<ph2pssuffix><round_qq2phsuff>\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
@@ -8161,19 +8148,6 @@
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
-(define_expand "avx512fp16_vcvtpd2ph_v4df_mask_round"
- [(match_operand:V8HF 0 "register_operand")
- (match_operand:V4DF 1 "register_operand")
- (match_operand:V8HF 2 "nonimm_or_0_operand")
- (match_operand:QI 3 "register_operand")
- (unspec [(match_operand:SI 4 "const_4_or_8_to_11_operand")] UNSPEC_EMBEDDED_ROUNDING)]
- "TARGET_AVX10_2_256"
-{
- emit_insn (gen_avx512fp16_vcvtpd2ph_v4df_mask_round_1 (
- operands[0], operands[1], operands[2], operands[3], CONST0_RTX (V4HFmode), operands[4]));
- DONE;
-})
-
(define_expand "avx512fp16_vcvt<castmode>2ph_<mode>_mask"
[(set (match_operand:V8HF 0 "register_operand" "=v")
(vec_concat:V8HF
@@ -8189,20 +8163,20 @@
"TARGET_AVX512FP16 && TARGET_AVX512VL"
"operands[4] = CONST0_RTX (V4HFmode);")
-(define_insn "avx512fp16_vcvt<castmode>2ph_<mode>_mask<round_name>_1"
+(define_insn "*avx512fp16_vcvt<castmode>2ph_<mode>_mask"
[(set (match_operand:V8HF 0 "register_operand" "=v")
(vec_concat:V8HF
(vec_merge:V4HF
(float_truncate:V4HF
- (match_operand:VF4_128_8_256 1 "<round_nimm_predicate>" "<round_constraint>"))
+ (match_operand:VF4_128_8_256 1 "vector_operand" "vm"))
(vec_select:V4HF
(match_operand:V8HF 2 "nonimm_or_0_operand" "0C")
(parallel [(const_int 0) (const_int 1)
(const_int 2) (const_int 3)]))
(match_operand:QI 3 "register_operand" "Yk"))
(match_operand:V4HF 4 "const0_operand")))]
- "TARGET_AVX512FP16 && TARGET_AVX512VL && <round_mode_condition>"
- "vcvt<castmode>2ph<ph2pssuffix><round_qq2phsuff>\t{<round_op5>%1, %0%{%3%}%N2|%0%{%3%}%N2, %1<round_op5>}"
+ "TARGET_AVX512FP16 && TARGET_AVX512VL"
+ "vcvt<castmode>2ph<ph2pssuffix><qq2phsuff>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -8647,7 +8621,7 @@
[(set (match_operand:VF1 0 "register_operand" "=x,v")
(float:VF1
(match_operand:<sseintvecmode> 1 "<round_nimm_predicate>" "xBm,<round_constraint>")))]
- "TARGET_SSE2 && <mask_mode512bit_condition> && <round_mode_condition>"
+ "TARGET_SSE2 && <mask_mode512bit_condition> && <round_mode512bit_condition>"
"@
cvtdq2ps\t{%1, %0|%0, %1}
vcvtdq2ps\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
@@ -8660,7 +8634,7 @@
[(set (match_operand:VF1_AVX512VL 0 "register_operand" "=v")
(unsigned_float:VF1_AVX512VL
(match_operand:<sseintvecmode> 1 "nonimmediate_operand" "<round_constraint>")))]
- "TARGET_AVX512F && <round_mode_condition>"
+ "TARGET_AVX512F"
"vcvtudq2ps\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
@@ -8684,13 +8658,13 @@
(define_mode_attr sf2simodelower
[(V16SI "v16sf") (V8SI "v8sf") (V4SI "v4sf")])
-(define_insn "<sse2_avx_avx512f>_fix_notrunc<sf2simodelower><mode><mask_name><round_name>"
+(define_insn "<sse2_avx_avx512f>_fix_notrunc<sf2simodelower><mode><mask_name>"
[(set (match_operand:VI4_AVX 0 "register_operand" "=v")
(unspec:VI4_AVX
- [(match_operand:<ssePSmode> 1 "<round_nimm_predicate>" "<round_constraint4>")]
+ [(match_operand:<ssePSmode> 1 "vector_operand" "vBm")]
UNSPEC_FIX_NOTRUNC))]
- "TARGET_SSE2 && <mask_mode512bit_condition> && <round_mode_condition>"
- "%vcvtps2dq\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
+ "TARGET_SSE2 && <mask_mode512bit_condition>"
+ "%vcvtps2dq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssecvt")
(set (attr "prefix_data16")
(if_then_else
@@ -8716,7 +8690,7 @@
(unspec:VI4_AVX512VL
[(match_operand:<ssePSmode> 1 "nonimmediate_operand" "<round_constraint>")]
UNSPEC_UNSIGNED_FIX_NOTRUNC))]
- "TARGET_AVX512F && <round_mode_condition>"
+ "TARGET_AVX512F"
"vcvtps2udq\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
@@ -8726,7 +8700,7 @@
[(set (match_operand:VI8_256_512 0 "register_operand" "=v")
(unspec:VI8_256_512 [(match_operand:<ssePSmode2> 1 "nonimmediate_operand" "<round_constraint>")]
UNSPEC_FIX_NOTRUNC))]
- "TARGET_AVX512DQ && <round_mode_condition>"
+ "TARGET_AVX512DQ && <round_mode512bit_condition>"
"vcvtps2qq\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
@@ -8749,7 +8723,7 @@
[(set (match_operand:VI8_256_512 0 "register_operand" "=v")
(unspec:VI8_256_512 [(match_operand:<ssePSmode2> 1 "nonimmediate_operand" "<round_constraint>")]
UNSPEC_UNSIGNED_FIX_NOTRUNC))]
- "TARGET_AVX512DQ && <round_mode_condition>"
+ "TARGET_AVX512DQ && <round_mode512bit_condition>"
"vcvtps2uqq\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
@@ -8789,13 +8763,12 @@
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
-(define_insn "unspec_fix_truncv8sfv8si2<mask_name><round_saeonly_name>"
+(define_insn "unspec_fix_truncv8sfv8si2<mask_name>"
[(set (match_operand:V8SI 0 "register_operand" "=v")
- (unspec:V8SI [(match_operand:V8SF 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")]
+ (unspec:V8SI [(match_operand:V8SF 1 "nonimmediate_operand" "vm")]
UNSPEC_VCVTT))]
- "TARGET_AVX && <mask_avx512vl_condition>
- && (!<round_saeonly_applied> || TARGET_AVX10_2_256)"
- "vcvttps2dq\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
+ "TARGET_AVX && <mask_avx512vl_condition>"
+ "vcvttps2dq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "<mask_prefix>")
(set_attr "mode" "OI")])
@@ -9181,7 +9154,7 @@
[(set (match_operand:VF2_AVX512VL 0 "register_operand" "=v")
(any_float:VF2_AVX512VL
(match_operand:<sseintvecmode> 1 "nonimmediate_operand" "<round_constraint>")))]
- "TARGET_AVX512DQ && <round_mode_condition>"
+ "TARGET_AVX512DQ"
"vcvt<floatsuffix>qq2pd\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
@@ -9195,8 +9168,8 @@
[(set (match_operand:<ssePSmode2> 0 "register_operand" "=v")
(any_float:<ssePSmode2>
(match_operand:VI8_256_512 1 "nonimmediate_operand" "<round_constraint>")))]
- "TARGET_AVX512DQ && <round_mode_condition>"
- "vcvt<floatsuffix>qq2ps<round_qq2pssuff>\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
+ "TARGET_AVX512DQ && <round_mode512bit_condition>"
+ "vcvt<floatsuffix>qq2ps<qq2pssuff>\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -9414,13 +9387,12 @@
(set_attr "prefix" "evex")
(set_attr "mode" "OI")])
-(define_insn "avx_cvtpd2dq256<mask_name><round_name>"
+(define_insn "avx_cvtpd2dq256<mask_name>"
[(set (match_operand:V4SI 0 "register_operand" "=v")
- (unspec:V4SI [(match_operand:V4DF 1 "<round_nimm_predicate>" "<round_constraint>")]
+ (unspec:V4SI [(match_operand:V4DF 1 "nonimmediate_operand" "vm")]
UNSPEC_FIX_NOTRUNC))]
- "TARGET_AVX && <mask_avx512vl_condition>
- && (!<round_applied> || TARGET_AVX10_2_256)"
- "vcvtpd2dq<round_suff>\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
+ "TARGET_AVX && <mask_avx512vl_condition>"
+ "vcvtpd2dq{y}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "<mask_prefix>")
(set_attr "mode" "OI")])
@@ -9510,8 +9482,8 @@
(unspec:<si2dfmode>
[(match_operand:VF2_512_256VL 1 "nonimmediate_operand" "<round_constraint>")]
UNSPEC_UNSIGNED_FIX_NOTRUNC))]
- "TARGET_AVX512F && <round_mode_condition>"
- "vcvtpd2udq<round_pd2udqsuff>\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
+ "TARGET_AVX512F"
+ "vcvtpd2udq<pd2udqsuff>\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -9654,13 +9626,12 @@
(set_attr "prefix" "evex")
(set_attr "mode" "TI")])
-(define_insn "unspec_fix_truncv4dfv4si2<mask_name><round_saeonly_name>"
+(define_insn "unspec_fix_truncv4dfv4si2<mask_name>"
[(set (match_operand:V4SI 0 "register_operand" "=v")
- (unspec:V4SI [(match_operand:V4DF 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")]
+ (unspec:V4SI [(match_operand:V4DF 1 "nonimmediate_operand" "vm")]
UNSPEC_VCVTT))]
- "TARGET_AVX && <mask_avx512vl_condition>
- && (!<round_saeonly_applied> || TARGET_AVX10_2_256)"
- "vcvttpd2dq<round_saeonly_suff>\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
+ "TARGET_AVX || (TARGET_AVX512VL && TARGET_AVX512F)"
+ "vcvttpd2dq{y}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "maybe_evex")
(set_attr "mode" "OI")])
@@ -9674,13 +9645,12 @@
(set_attr "prefix" "maybe_evex")
(set_attr "mode" "OI")])
-(define_insn "unspec_fixuns_truncv4dfv4si2<mask_name><round_saeonly_name>"
+(define_insn "unspec_fixuns_truncv4dfv4si2<mask_name>"
[(set (match_operand:V4SI 0 "register_operand" "=v")
- (unspec:V4SI [(match_operand:V4DF 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")]
+ (unspec:V4SI [(match_operand:V4DF 1 "nonimmediate_operand" "vm")]
UNSPEC_VCVTTU))]
- "TARGET_AVX512VL && TARGET_AVX512F
- && (!<round_saeonly_applied> || TARGET_AVX10_2_256)"
- "vcvttpd2udq<round_saeonly_suff>\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
+ "TARGET_AVX512VL && TARGET_AVX512F"
+ "vcvttpd2udq{y}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "maybe_evex")
(set_attr "mode" "OI")])
@@ -9699,7 +9669,7 @@
(unspec:<sseintvecmode>
[(match_operand:VF2_AVX512VL 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")]
UNSPEC_VCVTT_U))]
- "TARGET_AVX512DQ && <round_saeonly_mode_condition>"
+ "TARGET_AVX512DQ && <round_saeonly_mode512bit_condition>"
"vcvttpd2<vcvtt_suffix>qq\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
@@ -9709,7 +9679,7 @@
[(set (match_operand:<sseintvecmode> 0 "register_operand" "=v")
(any_fix:<sseintvecmode>
(match_operand:VF2_AVX512VL 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")))]
- "TARGET_AVX512DQ && <round_saeonly_mode_condition>"
+ "TARGET_AVX512DQ && <round_saeonly_mode512bit_condition>"
"vcvttpd2<fixsuffix>qq\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
@@ -9720,7 +9690,7 @@
(unspec:<sseintvecmode>
[(match_operand:VF2_AVX512VL 1 "<round_nimm_predicate>" "<round_constraint>")]
UNSPEC_FIX_NOTRUNC))]
- "TARGET_AVX512DQ && <round_mode_condition>"
+ "TARGET_AVX512DQ && <round_mode512bit_condition>"
"vcvtpd2qq\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
@@ -9731,7 +9701,7 @@
(unspec:<sseintvecmode>
[(match_operand:VF2_AVX512VL 1 "nonimmediate_operand" "<round_constraint>")]
UNSPEC_UNSIGNED_FIX_NOTRUNC))]
- "TARGET_AVX512DQ && <round_mode_condition>"
+ "TARGET_AVX512DQ && <round_mode512bit_condition>"
"vcvtpd2uqq\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
@@ -9742,18 +9712,18 @@
(unspec:VI8_256_512
[(match_operand:<ssePSmode2> 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")]
UNSPEC_VCVTT_U))]
- "TARGET_AVX512DQ && <round_saeonly_mode_condition>"
+ "TARGET_AVX512DQ && <round_saeonly_mode512bit_condition>"
"vcvttps2<vcvtt_suffix>qq\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
-(define_insn "fix<fixunssuffix>_trunc<ssePSmode2lower><mode>2<mask_name>"
+(define_insn "fix<fixunssuffix>_trunc<ssePSmode2lower><mode>2<mask_name><round_saeonly_name>"
[(set (match_operand:VI8_256_512 0 "register_operand" "=v")
(any_fix:VI8_256_512
- (match_operand:<ssePSmode2> 1 "nonimmediate_operand" "vm")))]
- "TARGET_AVX512DQ"
- "vcvttps2<fixsuffix>qq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
+ (match_operand:<ssePSmode2> 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")))]
+ "TARGET_AVX512DQ && <round_saeonly_mode512bit_condition>"
+ "vcvttps2<fixsuffix>qq\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -9908,13 +9878,13 @@
DONE;
})
-(define_insn "<mask_codefor>unspec_fixuns_trunc<mode><sseintvecmodelower>2<mask_name><round_saeonly_name>"
+(define_insn "<mask_codefor>unspec_fixuns_trunc<mode><sseintvecmodelower>2<mask_name>"
[(set (match_operand:<sseintvecmode> 0 "register_operand" "=v")
(unspec:<sseintvecmode>
- [(match_operand:VF1_128_256 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")]
+ [(match_operand:VF1_128_256 1 "nonimmediate_operand" "vm")]
UNSPEC_VCVTTU))]
- "TARGET_AVX512VL && <round_saeonly_mode_condition>"
- "vcvttps2udq\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
+ "TARGET_AVX512VL"
+ "vcvttps2udq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseintvecmode2>")])
@@ -10102,13 +10072,12 @@
(set_attr "prefix" "evex")
(set_attr "mode" "V8SF")])
-(define_insn "avx_cvtpd2ps256<mask_name><round_name>"
+(define_insn "avx_cvtpd2ps256<mask_name>"
[(set (match_operand:V4SF 0 "register_operand" "=v")
(float_truncate:V4SF
- (match_operand:V4DF 1 "<round_nimm_predicate>" "<round_constraint>")))]
- "TARGET_AVX && <mask_avx512vl_condition>
- && (!<round_applied> || TARGET_AVX10_2_256)"
- "vcvtpd2ps<round_suff>\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
+ (match_operand:V4DF 1 "nonimmediate_operand" "vm")))]
+ "TARGET_AVX && <mask_avx512vl_condition>"
+ "vcvtpd2ps{y}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "maybe_evex")
(set_attr "btver2_decode" "vector")
@@ -10231,7 +10200,7 @@
[(set (match_operand:VF2_512_256 0 "register_operand" "=v")
(float_extend:VF2_512_256
(match_operand:<sf2dfmode> 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")))]
- "TARGET_AVX && <mask_mode512bit_condition> && <round_saeonly_mode_condition>"
+ "TARGET_AVX && <mask_mode512bit_condition> && <round_saeonly_mode512bit_condition>"
"vcvtps2pd\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "maybe_vex")
@@ -11935,7 +11904,7 @@
]
(const_string "ssemov")))
(set (attr "addr")
- (if_then_else (eq_attr "alternative" "8,9")
+ (if_then_else (eq_attr "alternative" "9,10")
(const_string "gpr16")
(const_string "*")))
(set (attr "prefix_extra")
@@ -12126,7 +12095,7 @@
(match_operand:V8_128 1 "reg_or_0_operand" "v,C")
(const_int 1)))]
"TARGET_AVX512FP16
- || (TARGET_AVX10_2_256 && const0_operand (operands[1], <MODE>mode))"
+ || (TARGET_AVX10_2 && const0_operand (operands[1], <MODE>mode))"
"@
vmovsh\t{%2, %1, %0|%0, %1, %2}
vmovw\t{%2, %0|%2, %0}"
@@ -13633,7 +13602,7 @@
[(match_operand:VFH_AVX512VL 1 "register_operand" "v")
(match_operand:VFH_AVX512VL 2 "nonimmediate_operand" "<round_constraint>")]
UNSPEC_SCALEF))]
- "TARGET_AVX512F && <round_mode_condition>"
+ "TARGET_AVX512F"
"vscalef<ssemodesuffix>\t{<round_mask_op3>%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2<round_mask_op3>}"
[(set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
@@ -14041,7 +14010,7 @@
[(set (match_operand:VFH_AVX512VL 0 "register_operand" "=v")
(unspec:VFH_AVX512VL [(match_operand:VFH_AVX512VL 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")]
UNSPEC_GETEXP))]
- "TARGET_AVX512F && <round_saeonly_mode_condition>"
+ "TARGET_AVX512F"
"vgetexp<ssemodesuffix>\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}";
[(set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
@@ -14156,7 +14125,7 @@
(match_operand:<sseintvecmode> 3 "nonimmediate_operand" "<round_saeonly_constraint>")
(match_operand:SI 4 "const_0_to_255_operand")]
UNSPEC_FIXUPIMM))]
- "TARGET_AVX512F && <round_saeonly_mode_condition>"
+ "TARGET_AVX512F"
"vfixupimm<ssemodesuffix>\t{%4, <round_saeonly_sd_mask_op5>%3, %2, %0<sd_mask_op5>|%0<sd_mask_op5>, %2, %3<round_saeonly_sd_mask_op5>, %4}";
[(set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
@@ -14172,7 +14141,7 @@
UNSPEC_FIXUPIMM)
(match_dup 1)
(match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
- "TARGET_AVX512F && <round_saeonly_mode_condition>"
+ "TARGET_AVX512F"
"vfixupimm<ssemodesuffix>\t{%4, <round_saeonly_op6>%3, %2, %0%{%5%}|%0%{%5%}, %2, %3<round_saeonly_op6>, %4}";
[(set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
@@ -14234,7 +14203,7 @@
[(match_operand:VFH_AVX512VL 1 "nonimmediate_operand" "<round_saeonly_constraint>")
(match_operand:SI 2 "const_0_to_255_operand")]
UNSPEC_ROUND))]
- "TARGET_AVX512F && <round_saeonly_mode_condition>"
+ "TARGET_AVX512F"
"vrndscale<ssemodesuffix>\t{%2, <round_saeonly_mask_op3>%1, %0<mask_operand3>|%0<mask_operand3>, %1<round_saeonly_mask_op3>, %2}"
[(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
@@ -20204,6 +20173,7 @@
return "vshuf<shuffletype>64x2\t{%3, %2, %1, %0<mask_operand7>|%0<mask_operand7>, %1, %2, %3}";
}
[(set_attr "type" "sselog")
+ (set_attr "addr" "gpr16,*")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
@@ -20365,6 +20335,7 @@
return "vshuf<shuffletype>32x4\t{%3, %2, %1, %0<mask_operand11>|%0<mask_operand11>, %1, %2, %3}";
}
[(set_attr "type" "sselog")
+ (set_attr "addr" "gpr16,*")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -23829,7 +23800,7 @@
(match_operand:V64QI 2 "vector_operand" "vm")
(match_operand:SI 3 "const_0_to_255_operand" "n")]
UNSPEC_MPSADBW))]
- "TARGET_AVX10_2_512"
+ "TARGET_AVX10_2"
"vmpsadbw\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3}"
[(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")])
@@ -23841,7 +23812,7 @@
(match_operand:VI1 2 "vector_operand" "vm")
(match_operand:SI 3 "const_0_to_255_operand" "n")]
UNSPEC_MPSADBW))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vmpsadbw\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3}"
[(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
@@ -24107,6 +24078,7 @@
"TARGET_AVX2"
"vpblendd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemov")
+ (set_attr "addr" "gpr16")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
@@ -27116,7 +27088,7 @@
vaesenc\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx,vaes_avx512vl")
(set_attr "type" "sselog1")
- (set_attr "addr" "gpr16,*,*")
+ (set_attr "addr" "gpr16,gpr16,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex,evex")
(set_attr "btver2_decode" "double,double,double")
@@ -27134,7 +27106,7 @@
vaesenclast\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx,vaes_avx512vl")
(set_attr "type" "sselog1")
- (set_attr "addr" "gpr16,*,*")
+ (set_attr "addr" "gpr16,gpr16,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex,evex")
(set_attr "btver2_decode" "double,double,double")
@@ -27152,7 +27124,7 @@
vaesdec\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx,vaes_avx512vl")
(set_attr "type" "sselog1")
- (set_attr "addr" "gpr16,*,*")
+ (set_attr "addr" "gpr16,gpr16,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex,evex")
(set_attr "btver2_decode" "double,double,double")
@@ -27169,7 +27141,7 @@
* return TARGET_AES ? \"vaesdeclast\t{%2, %1, %0|%0, %1, %2}\" : \"%{evex%} vaesdeclast\t{%2, %1, %0|%0, %1, %2}\";
vaesdeclast\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx,vaes_avx512vl")
- (set_attr "addr" "gpr16,*,*")
+ (set_attr "addr" "gpr16,gpr16,*")
(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex,evex")
@@ -29104,13 +29076,12 @@
(set_attr "prefix" "vex")
(set_attr "mode" "V8SF")])
-(define_insn "vcvtph2ps256<mask_name><round_saeonly_name>"
+(define_insn "vcvtph2ps256<mask_name>"
[(set (match_operand:V8SF 0 "register_operand" "=v")
- (unspec:V8SF [(match_operand:V8HI 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>")]
+ (unspec:V8SF [(match_operand:V8HI 1 "nonimmediate_operand" "vm")]
UNSPEC_VCVTPH2PS))]
- "(TARGET_F16C || TARGET_AVX512VL)
- && (!<round_saeonly_applied> || TARGET_AVX10_2_256)"
- "vcvtph2ps\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
+ "TARGET_F16C || TARGET_AVX512VL"
+ "vcvtph2ps\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "vex")
(set_attr "btver2_decode" "double")
@@ -29824,7 +29795,7 @@
(match_operand:VF_AVX512VL 2 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")
(match_operand:SI 3 "const_0_to_15_operand")]
UNSPEC_RANGE))]
- "TARGET_AVX512DQ && <round_saeonly_mode_condition>"
+ "TARGET_AVX512DQ && <round_saeonly_mode512bit_condition>"
{
if (TARGET_DEST_FALSE_DEP_FOR_GLC
&& <mask4_dest_false_dep_for_glc_cond>
@@ -29894,7 +29865,7 @@
[(match_operand:VFH_AVX512VL 1 "nonimmediate_operand" "<round_saeonly_constraint>")
(match_operand:SI 2 "const_0_to_15_operand")]
UNSPEC_GETMANT))]
- "TARGET_AVX512F && <round_saeonly_mode_condition>"
+ "TARGET_AVX512F"
{
if (TARGET_DEST_FALSE_DEP_FOR_GLC
&& <mask3_dest_false_dep_for_glc_cond>
@@ -30873,7 +30844,8 @@
return "%{evex%} vaesdec\t{%2, %1, %0|%0, %1, %2}";
else
return "vaesdec\t{%2, %1, %0|%0, %1, %2}";
-})
+}
+[(set_attr "addr" "gpr16,*")])
(define_insn "vaesdeclast_<mode>"
[(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=x,v")
@@ -30887,7 +30859,8 @@
return "%{evex%} vaesdeclast\t{%2, %1, %0|%0, %1, %2}";
else
return "vaesdeclast\t{%2, %1, %0|%0, %1, %2}";
-})
+}
+[(set_attr "addr" "gpr16,*")])
(define_insn "vaesenc_<mode>"
[(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=x,v")
@@ -30901,7 +30874,8 @@
return "%{evex%} vaesenc\t{%2, %1, %0|%0, %1, %2}";
else
return "vaesenc\t{%2, %1, %0|%0, %1, %2}";
-})
+}
+[(set_attr "addr" "gpr16,*")])
(define_insn "vaesenclast_<mode>"
[(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=x,v")
@@ -30915,7 +30889,8 @@
return "%{evex%} vaesenclast\t{%2, %1, %0|%0, %1, %2}";
else
return "vaesenclast\t{%2, %1, %0|%0, %1, %2}";
-})
+}
+[(set_attr "addr" "gpr16,*")])
(define_insn "vpclmulqdq_<mode>"
[(set (match_operand:VI8_FVL 0 "register_operand" "=v")
@@ -31362,7 +31337,8 @@
(unspec_volatile:CCZ [(match_dup 1) (match_dup 2)] AESDECENCKL))]
"TARGET_KL"
"aes<aesklvariant>\t{%2, %0|%0, %2}"
- [(set_attr "type" "other")])
+ [(set_attr "type" "other")
+ (set_attr "addr" "gpr16")])
(define_int_iterator AESDECENCWIDEKL
[UNSPECV_AESDECWIDE128KLU8 UNSPECV_AESDECWIDE256KLU8
@@ -31424,7 +31400,8 @@
AESDECENCWIDEKL))])]
"TARGET_WIDEKL"
"aes<aeswideklvariant>\t%0"
- [(set_attr "type" "other")])
+ [(set_attr "type" "other")
+ (set_attr "addr" "gpr16")])
;; Modes handled by broadcast patterns. NB: Allow V64QI and V32HI with
;; TARGET_AVX512F since ix86_expand_vector_init_duplicate can expand
@@ -31477,8 +31454,8 @@
(match_operand:<ssedvecmode> 3 "register_operand")]
"TARGET_SSE2"
{
- if ((<MODE_SIZE> == 64 && TARGET_AVX10_2_512)
- || (<MODE_SIZE> < 64 && (TARGET_AVXVNNIINT8 || TARGET_AVX10_2_256)))
+ if ((<MODE_SIZE> == 64 && TARGET_AVX10_2)
+ || (<MODE_SIZE> < 64 && (TARGET_AVXVNNIINT8 || TARGET_AVX10_2)))
{
operands[1] = lowpart_subreg (<ssedvecmode>mode,
force_reg (<MODE>mode, operands[1]),
@@ -31525,8 +31502,8 @@
(match_operand:<ssedvecmode> 3 "register_operand")]
"TARGET_SSE2"
{
- if ((<MODE_SIZE> == 64 && TARGET_AVX10_2_512)
- || (<MODE_SIZE> < 64 && (TARGET_AVXVNNIINT8 || TARGET_AVX10_2_256)))
+ if ((<MODE_SIZE> == 64 && TARGET_AVX10_2)
+ || (<MODE_SIZE> < 64 && (TARGET_AVXVNNIINT8 || TARGET_AVX10_2)))
{
operands[1] = lowpart_subreg (<ssedvecmode>mode,
force_reg (<MODE>mode, operands[1]),
@@ -31573,7 +31550,7 @@
(match_operand:VI4_AVX 2 "register_operand" "v")
(match_operand:VI4_AVX 3 "nonimmediate_operand" "vm")]
VPDOTPROD))]
- "TARGET_AVXVNNIINT8 || TARGET_AVX10_2_256"
+ "TARGET_AVXVNNIINT8 || TARGET_AVX10_2"
"vpdp<vpdotprodtype>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "prefix" "maybe_evex")])
@@ -31584,7 +31561,7 @@
(match_operand:V16SI 2 "register_operand" "v")
(match_operand:V16SI 3 "nonimmediate_operand" "vm")]
VPDOTPROD))]
- "TARGET_AVX10_2_512"
+ "TARGET_AVX10_2"
"vpdp<vpdotprodtype>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "prefix" "evex")])
@@ -31598,7 +31575,7 @@
VPDOTPROD)
(match_dup 1)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vpdp<vpdotprodtype>\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}"
[(set_attr "prefix" "evex")])
@@ -31612,7 +31589,7 @@
VPDOTPROD)
(match_dup 5)
(match_operand:<avx512fmaskmode> 4 "register_operand")))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"operands[5] = CONST0_RTX (<MODE>mode);")
(define_insn "*vpdp<vpdotprodtype>_<mode>_maskz"
@@ -31625,7 +31602,7 @@
VPDOTPROD)
(match_operand:VI4_AVX10_2 5 "const0_operand" "C")
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vpdp<vpdotprodtype>\t{%3, %2, %0%{%4%}%N5|%0%{%4%}%N5, %2, %3}"
[(set_attr "prefix" "evex")])
@@ -31718,7 +31695,7 @@
(match_operand:<ssePSmode> 2 "<round_nimm_predicate>" "<round_constraint>"))
(float_truncate:<ssehalfvecmode>
(match_operand:<ssePSmode> 1 "register_operand" "v"))))]
- "TARGET_AVX10_2_256 && <round_mode_condition>"
+ "TARGET_AVX10_2 && <round_mode512bit_condition>"
"vcvt2ps2phx\t{<round_mask_op3>%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2<round_mask_op3>}")
(define_mode_attr ssebvecmode
@@ -31740,7 +31717,7 @@
[(match_operand:VHF_AVX10_2 1 "register_operand" "v")
(match_operand:VHF_AVX10_2 2 "nonimmediate_operand" "vm")]
UNSPEC_CONVERTFP8_PACK))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vcvt<convertfp8_pack>\t{%2, %1, %0<mask_operand3>|%0<mask_operand2>, %1, %2}"
[(set_attr "prefix" "evex")])
@@ -31765,7 +31742,7 @@
(match_operand:V8HF 2 "nonimmediate_operand")]
UNSPEC_VCVTBIASPH2FP8_PACK)
(match_dup 3)))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"operands[3] = CONST0_RTX (V8QImode);")
(define_insn "*vcvt<biasph2fp8_pack>v8hf"
@@ -31776,7 +31753,7 @@
(match_operand:V8HF 2 "nonimmediate_operand" "vm")]
UNSPEC_VCVTBIASPH2FP8_PACK)
(match_operand:V8QI 3 "const0_operand")))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vcvt<biasph2fp8_pack>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "prefix" "evex")
(set_attr "mode" "HF")])
@@ -31797,7 +31774,7 @@
(const_int 6) (const_int 7)]))
(match_operand:QI 4 "register_operand" "C"))
(match_dup 5)))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"operands[5] = CONST0_RTX (V8QImode);")
(define_insn "*vcvt<biasph2fp8_pack>v8hf_mask"
@@ -31816,12 +31793,12 @@
(const_int 6) (const_int 7)]))
(match_operand:QI 4 "register_operand" "Yk"))
(match_operand:V8QI 5 "const0_operand")))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vcvt<biasph2fp8_pack>\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}"
[(set_attr "prefix" "evex")])
(define_mode_iterator VHF_AVX10_2_2
- [(V32HF "TARGET_AVX10_2_512") V16HF])
+ [(V32HF "TARGET_AVX10_2") V16HF])
(define_insn "vcvt<biasph2fp8_pack><mode><mask_name>"
[(set (match_operand:<ssebvecmode_2> 0 "register_operand" "=v")
@@ -31829,12 +31806,12 @@
[(match_operand:<ssebvecmode> 1 "register_operand" "v")
(match_operand:VHF_AVX10_2_2 2 "nonimmediate_operand" "vm")]
UNSPEC_VCVTBIASPH2FP8_PACK))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vcvt<biasph2fp8_pack>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "prefix" "evex")])
(define_mode_iterator VHF_256_512
- [V16HF (V32HF "TARGET_AVX10_2_512")])
+ [V16HF (V32HF "TARGET_AVX10_2")])
(define_mode_attr ph2fp8suff
[(V32HF "") (V16HF "{y}") (V8HF "{x}")])
@@ -31856,7 +31833,7 @@
[(match_operand:V8HF 1 "nonimmediate_operand")]
UNSPEC_CONVERTPH2FP8)
(match_dup 2)))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"operands[2] = CONST0_RTX (V8QImode);")
(define_insn "*vcvt<convertph2fp8>v8hf"
@@ -31866,7 +31843,7 @@
[(match_operand:V8HF 1 "nonimmediate_operand" "vm")]
UNSPEC_CONVERTPH2FP8)
(match_operand:V8QI 2 "const0_operand")))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vcvt<convertph2fp8>{x}\t{%1, %0|%0, %1}"
[(set_attr "prefix" "evex")
(set_attr "mode" "HF")])
@@ -31886,7 +31863,7 @@
(const_int 6) (const_int 7)]))
(match_operand:QI 3 "register_operand"))
(match_dup 4)))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"operands[4] = CONST0_RTX (V8QImode);")
(define_insn "*vcvt<convertph2fp8>v8hf_mask"
@@ -31904,7 +31881,7 @@
(const_int 6) (const_int 7)]))
(match_operand:QI 3 "register_operand" "Yk"))
(match_operand:V8QI 4 "const0_operand")))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vcvt<convertph2fp8>{x}\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
[(set_attr "prefix" "evex")])
@@ -31913,7 +31890,7 @@
(unspec:<ssebvecmode_2>
[(match_operand:VHF_256_512 1 "nonimmediate_operand" "vm")]
UNSPEC_CONVERTPH2FP8))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vcvt<convertph2fp8><ph2fp8suff>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "prefix" "evex")])
@@ -31922,7 +31899,7 @@
(unspec:VHF_AVX10_2
[(match_operand:<ssebvecmode_2> 1 "nonimmediate_operand" "vm")]
UNSPEC_VCVTHF82PH))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vcvthf82ph\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "prefix" "evex")])
@@ -31944,7 +31921,7 @@
(match_operand:VI2_AVX10_2 1 "register_operand")
(match_operand:VI2_AVX10_2 2 "register_operand")
(match_operand:<sseunpackmode> 3 "register_operand")]
- "TARGET_AVXVNNIINT16 || TARGET_AVX10_2_256"
+ "TARGET_AVXVNNIINT16 || TARGET_AVX10_2"
{
operands[1] = lowpart_subreg (<sseunpackmode>mode,
force_reg (<MODE>mode, operands[1]),
@@ -31962,7 +31939,7 @@
(match_operand:VI2_AVX10_2 1 "register_operand")
(match_operand:VI2_AVX10_2 2 "register_operand")
(match_operand:<sseunpackmode> 3 "register_operand")]
- "TARGET_AVXVNNIINT16 || TARGET_AVX10_2_256"
+ "TARGET_AVXVNNIINT16 || TARGET_AVX10_2"
{
operands[1] = lowpart_subreg (<sseunpackmode>mode,
force_reg (<MODE>mode, operands[1]),
@@ -31982,7 +31959,7 @@
(match_operand:VI4_AVX 2 "register_operand" "v")
(match_operand:VI4_AVX 3 "nonimmediate_operand" "vm")]
VPDPWPROD))]
- "TARGET_AVXVNNIINT16 || TARGET_AVX10_2_256"
+ "TARGET_AVXVNNIINT16 || TARGET_AVX10_2"
"vpdp<vpdpwprodtype>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "prefix" "maybe_evex")])
@@ -31993,7 +31970,7 @@
(match_operand:V16SI 2 "register_operand" "v")
(match_operand:V16SI 3 "nonimmediate_operand" "vm")]
VPDPWPROD))]
- "TARGET_AVX10_2_512"
+ "TARGET_AVX10_2"
"vpdp<vpdpwprodtype>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "prefix" "evex")])
@@ -32007,7 +31984,7 @@
VPDPWPROD)
(match_dup 1)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vpdp<vpdpwprodtype>\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}"
[(set_attr "prefix" "evex")])
@@ -32021,7 +31998,7 @@
VPDPWPROD)
(match_dup 5)
(match_operand:<avx512fmaskmode> 4 "register_operand")))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"operands[5] = CONST0_RTX (<MODE>mode);")
(define_insn "*vpdp<vpdpwprodtype>_<mode>_maskz"
@@ -32034,7 +32011,7 @@
VPDPWPROD)
(match_operand:VI4_AVX10_2 5 "const0_operand" "C")
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vpdp<vpdpwprodtype>\t{%3, %2, %0%{%4%}%N5|%0%{%4%}%N5, %2, %3}"
[(set_attr "prefix" "evex")])
@@ -32045,7 +32022,7 @@
(match_operand:VF1_AVX10_2 2 "register_operand" "v")
(match_operand:VF1_AVX10_2 3 "nonimmediate_operand" "vm")]
UNSPEC_VDPPHPS))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vdpphps\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "prefix" "evex")])
@@ -32059,7 +32036,7 @@
UNSPEC_VDPPHPS)
(match_dup 1)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vdpphps\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}"
[(set_attr "prefix" "evex")])
@@ -32069,7 +32046,7 @@
(match_operand:VF1_AVX10_2 2 "register_operand")
(match_operand:VF1_AVX10_2 3 "nonimmediate_operand")
(match_operand:<avx512fmaskmode> 4 "register_operand")]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
{
emit_insn (gen_vdpphps_<mode>_maskz_1 (operands[0], operands[1],
operands[2], operands[3], CONST0_RTX(<MODE>mode), operands[4]));
@@ -32086,7 +32063,7 @@
UNSPEC_VDPPHPS)
(match_operand:VF1_AVX10_2 4 "const0_operand" "C")
(match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vdpphps\t{%3, %2, %0%{%5%}%N4|%0%{%5%}%N4, %2, %3}"
[(set_attr "prefix" "evex")])
@@ -32096,7 +32073,7 @@
[(match_operand:VBF_AVX10_2 1 "register_operand" "v")
(match_operand:VBF_AVX10_2 2 "nonimmediate_operand" "vm")]
UNSPEC_VSCALEFBF16))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vscalefbf16\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "prefix" "evex")])
@@ -32105,14 +32082,14 @@
(smaxmin:VBF_AVX10_2
(match_operand:VBF_AVX10_2 1 "register_operand")
(match_operand:VBF_AVX10_2 2 "nonimmediate_operand")))]
- "TARGET_AVX10_2_256")
+ "TARGET_AVX10_2")
(define_insn "avx10_2_<code>bf16_<mode><mask_name>"
[(set (match_operand:VBF_AVX10_2 0 "register_operand" "=v")
(smaxmin:VBF_AVX10_2
(match_operand:VBF_AVX10_2 1 "register_operand" "v")
(match_operand:VBF_AVX10_2 2 "nonimmediate_operand" "vm")))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"v<maxmin_float>bf16\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
@@ -32122,7 +32099,7 @@
(plusminusmultdiv:VBF_AVX10_2
(match_operand:VBF_AVX10_2 1 "register_operand" "v")
(match_operand:VBF_AVX10_2 2 "nonimmediate_operand" "vm")))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"v<insn>bf16\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "prefix" "evex")])
@@ -32132,7 +32109,7 @@
(match_operand:VBF_AVX10_2 2 "nonimmediate_operand")
(match_operand:VBF_AVX10_2 3 "nonimmediate_operand")
(match_operand:<avx512fmaskmode> 4 "register_operand")]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
{
emit_insn (gen_avx10_2_fmaddbf16_<mode>_maskz_1 (operands[0], operands[1],
operands[2], operands[3],
@@ -32147,7 +32124,7 @@
(match_operand:VBF_AVX10_2 1 "nonimmediate_operand" "%0,0,v")
(match_operand:VBF_AVX10_2 2 "nonimmediate_operand" "vm,v,vm")
(match_operand:VBF_AVX10_2 3 "nonimmediate_operand" "v,vm,0")))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"@
vfmadd132bf16\t{%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2}
vfmadd213bf16\t{%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3}
@@ -32165,7 +32142,7 @@
(match_operand:VBF_AVX10_2 3 "nonimmediate_operand" "v,vm"))
(match_dup 1)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk,Yk")))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"@
vfmadd132bf16\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2}
vfmadd213bf16\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}"
@@ -32182,7 +32159,7 @@
(match_operand:VBF_AVX10_2 3 "nonimmediate_operand" "0"))
(match_dup 3)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vfmadd231bf16\t{%2, %1, %0%{%4%}|%0%{%4%}, %1, %2}"
[(set_attr "prefix" "evex")
(set_attr "type" "ssemuladd")
@@ -32194,7 +32171,7 @@
(match_operand:VBF_AVX10_2 2 "nonimmediate_operand")
(match_operand:VBF_AVX10_2 3 "nonimmediate_operand")
(match_operand:<avx512fmaskmode> 4 "register_operand")]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
{
emit_insn (gen_avx10_2_fnmaddbf16_<mode>_maskz_1 (operands[0], operands[1],
operands[2], operands[3],
@@ -32210,7 +32187,7 @@
(match_operand:VBF_AVX10_2 1 "nonimmediate_operand" "%0,0,v"))
(match_operand:VBF_AVX10_2 2 "nonimmediate_operand" "vm,v,vm")
(match_operand:VBF_AVX10_2 3 "nonimmediate_operand" "v,vm,0")))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"@
vfnmadd132bf16\t{%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2}
vfnmadd213bf16\t{%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3}
@@ -32229,7 +32206,7 @@
(match_operand:VBF_AVX10_2 3 "nonimmediate_operand" "v,vm"))
(match_dup 1)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk,Yk")))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"@
vfnmadd132bf16\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2}
vfnmadd213bf16\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}"
@@ -32247,7 +32224,7 @@
(match_operand:VBF_AVX10_2 3 "nonimmediate_operand" "0"))
(match_dup 3)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vfnmadd231bf16\t{%2, %1, %0%{%4%}|%0%{%4%}, %1, %2}"
[(set_attr "prefix" "evex")
(set_attr "type" "ssemuladd")
@@ -32259,7 +32236,7 @@
(match_operand:VBF_AVX10_2 2 "nonimmediate_operand")
(match_operand:VBF_AVX10_2 3 "nonimmediate_operand")
(match_operand:<avx512fmaskmode> 4 "register_operand")]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
{
emit_insn (gen_avx10_2_fmsubbf16_<mode>_maskz_1 (operands[0], operands[1],
operands[2], operands[3],
@@ -32275,7 +32252,7 @@
(match_operand:VBF_AVX10_2 2 "nonimmediate_operand" "vm,v,vm")
(neg:VBF_AVX10_2
(match_operand:VBF_AVX10_2 3 "nonimmediate_operand" "v,vm,0"))))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"@
vfmsub132bf16\t{%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2}
vfmsub213bf16\t{%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3}
@@ -32294,7 +32271,7 @@
(match_operand:VBF_AVX10_2 3 "nonimmediate_operand" "v,vm")))
(match_dup 1)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk,Yk")))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"@
vfmsub132bf16\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2}
vfmsub213bf16\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}"
@@ -32312,7 +32289,7 @@
(match_operand:VBF_AVX10_2 3 "nonimmediate_operand" "0")))
(match_dup 3)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vfmsub231bf16\t{%2, %1, %0%{%4%}|%0%{%4%}, %1, %2}"
[(set_attr "prefix" "evex")
(set_attr "type" "ssemuladd")
@@ -32324,7 +32301,7 @@
(match_operand:VBF_AVX10_2 2 "nonimmediate_operand")
(match_operand:VBF_AVX10_2 3 "nonimmediate_operand")
(match_operand:<avx512fmaskmode> 4 "register_operand")]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
{
emit_insn (gen_avx10_2_fnmsubbf16_<mode>_maskz_1 (operands[0], operands[1],
operands[2], operands[3],
@@ -32341,7 +32318,7 @@
(match_operand:VBF_AVX10_2 2 "nonimmediate_operand" "vm,v,vm")
(neg:VBF_AVX10_2
(match_operand:VBF_AVX10_2 3 "nonimmediate_operand" "v,vm,0"))))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"@
vfnmsub132bf16\t{%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2}
vfnmsub213bf16\t{%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3}
@@ -32361,7 +32338,7 @@
(match_operand:VBF_AVX10_2 3 "nonimmediate_operand" "v,vm")))
(match_dup 1)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk,Yk")))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"@
vfnmsub132bf16\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2}
vfnmsub213bf16\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}"
@@ -32380,7 +32357,7 @@
(match_operand:VBF_AVX10_2 3 "nonimmediate_operand" "0")))
(match_dup 3)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vfnmsub231bf16\t{%2, %1, %0%{%4%}|%0%{%4%}, %1, %2}"
[(set_attr "prefix" "evex")
(set_attr "type" "ssemuladd")
@@ -32391,7 +32368,7 @@
(unspec:VBF_AVX10_2
[(match_operand:VBF_AVX10_2 1 "nonimmediate_operand" "vm")]
UNSPEC_RSQRT))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vrsqrtbf16\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "prefix" "evex")])
@@ -32399,7 +32376,7 @@
[(set (match_operand:VBF_AVX10_2 0 "register_operand" "=v")
(sqrt:VBF_AVX10_2
(match_operand:VBF_AVX10_2 1 "nonimmediate_operand" "vm")))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vsqrtbf16\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "prefix" "evex")])
@@ -32408,7 +32385,7 @@
(unspec:VBF_AVX10_2
[(match_operand:VBF_AVX10_2 1 "nonimmediate_operand" "vm")]
UNSPEC_RCP))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vrcpbf16\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "prefix" "evex")])
@@ -32417,7 +32394,7 @@
(unspec:VBF_AVX10_2
[(match_operand:VBF_AVX10_2 1 "nonimmediate_operand" "vm")]
UNSPEC_GETEXP))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vgetexpbf16\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "prefix" "evex")])
@@ -32437,7 +32414,7 @@
[(match_operand:VBF_AVX10_2 1 "nonimmediate_operand" "vm")
(match_operand:SI 2 "const_0_to_255_operand")]
BF16IMMOP))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"v<bf16immop>bf16\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "prefix" "evex")])
@@ -32447,7 +32424,7 @@
[(match_operand:VBF_AVX10_2 1 "nonimmediate_operand" "vm")
(match_operand 2 "const_0_to_255_operand")]
UNSPEC_VFPCLASSBF16))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vfpclassbf16<vecmemsuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
[(set_attr "prefix" "evex")])
@@ -32458,7 +32435,7 @@
(match_operand:VBF_AVX10_2 2 "nonimmediate_operand" "vm")
(match_operand 3 "const_0_to_31_operand" "n")]
UNSPEC_PCMP))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vcmpbf16\t{%3, %2, %1, %0<mask_scalar_merge_operand4>|%0<mask_scalar_merge_operand4>, %1, %2, %3}"
[(set_attr "prefix" "evex")])
@@ -32495,7 +32472,7 @@
(unspec:<sseintvecmode>
[(match_operand:VBF_AVX10_2 1 "vector_operand" "vm")]
UNSPEC_CVT_BF16_IBS_ITER))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vcvt<sat_cvt_trunc_prefix>bf162i<sat_cvt_sign_prefix>bs\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
@@ -32510,7 +32487,7 @@
(unspec:<sseintvecmode>
[(match_operand:VHF_AVX10_2 1 "<round_nimm_predicate>" "<round_constraint>")]
UNSPEC_CVT_PH_IBS_ITER))]
- "TARGET_AVX10_2_256 && <round_mode_condition>"
+ "TARGET_AVX10_2 && <round_mode512bit_condition>"
"vcvtph2i<sat_cvt_sign_prefix>bs\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
@@ -32525,7 +32502,7 @@
(unspec:<sseintvecmode>
[(match_operand:VHF_AVX10_2 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")]
UNSPEC_CVTT_PH_IBS_ITER))]
- "TARGET_AVX10_2_256 && <round_saeonly_mode_condition>"
+ "TARGET_AVX10_2 && <round_saeonly_mode512bit_condition>"
"vcvttph2i<sat_cvt_sign_prefix>bs\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
@@ -32540,7 +32517,7 @@
(unspec:<sseintvecmode>
[(match_operand:VF1_AVX10_2 1 "<round_nimm_predicate>" "<round_constraint>")]
UNSPEC_CVT_PS_IBS_ITER))]
- "TARGET_AVX10_2_256 && <round_mode_condition>"
+ "TARGET_AVX10_2 && <round_mode512bit_condition>"
"vcvtps2i<sat_cvt_sign_prefix>bs\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
@@ -32555,7 +32532,7 @@
(unspec:<sseintvecmode>
[(match_operand:VF1_AVX10_2 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")]
UNSPEC_CVTT_PS_IBS_ITER))]
- "TARGET_AVX10_2_256 && <round_saeonly_mode_condition>"
+ "TARGET_AVX10_2 && <round_saeonly_mode512bit_condition>"
"vcvttps2i<sat_cvt_sign_prefix>bs\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
@@ -32574,7 +32551,7 @@
(unspec:<VEC_GATHER_IDXSI>
[(match_operand:VF1_VF2_AVX10_2 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")]
UNSPEC_SAT_CVT_DS_SIGN_ITER))]
- "TARGET_AVX10_2_256 && <round_saeonly_mode_condition>"
+ "TARGET_AVX10_2 && <round_saeonly_mode512bit_condition>"
"vcvtt<castmode>2<sat_cvt_sign_prefix>dqs<pd2dqssuff>\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
@@ -32585,7 +32562,7 @@
(unspec:<VEC_GATHER_IDXDI>
[(match_operand:VF2_AVX10_2 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")]
UNSPEC_SAT_CVT_DS_SIGN_ITER))]
- "TARGET_AVX10_2_256 && <round_saeonly_mode_condition>"
+ "TARGET_AVX10_2 && <round_saeonly_mode512bit_condition>"
"vcvttpd2<sat_cvt_sign_prefix>qqs\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
@@ -32596,7 +32573,7 @@
(unspec:VI8_AVX10_2
[(match_operand:<vpckfloat_temp_mode> 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")]
UNSPEC_SAT_CVT_DS_SIGN_ITER))]
- "TARGET_AVX10_2_256 && <round_saeonly_mode_condition>"
+ "TARGET_AVX10_2 && <round_saeonly_mode512bit_condition>"
"vcvttps2<sat_cvt_sign_prefix>qqs\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
@@ -32609,7 +32586,7 @@
(match_operand:V2DF 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>")
(parallel [(const_int 0)]))]
UNSPEC_SAT_CVT_DS_SIGN_ITER))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vcvttsd2<sat_cvt_sign_prefix>sis\t{<round_saeonly_op2>%1, %0|%0, %1<round_saeonly_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
@@ -32622,7 +32599,7 @@
(match_operand:V4SF 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>")
(parallel [(const_int 0)]))]
UNSPEC_SAT_CVT_DS_SIGN_ITER))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vcvttss2<sat_cvt_sign_prefix>sis\t{<round_saeonly_op2>%1, %0|%0, %1<round_saeonly_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
@@ -32635,7 +32612,7 @@
(match_operand:VBF_AVX10_2 2 "bcst_vector_operand" "vmBr")
(match_operand:SI 3 "const_0_to_255_operand")]
UNSPEC_MINMAXBF16))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vminmaxbf16\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3}"
[(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -32647,7 +32624,7 @@
(match_operand:VFH_AVX10_2 2 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")
(match_operand:SI 3 "const_0_to_255_operand")]
UNSPEC_MINMAX))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vminmax<ssemodesuffix>\t{%3, <round_saeonly_mask_op4>%2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2<round_saeonly_mask_op4>, %3}"
[(set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
@@ -32662,7 +32639,7 @@
UNSPEC_MINMAX)
(match_dup 1)
(const_int 1)))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
"vminmax<ssescalarmodesuffix>\t{%3, <round_saeonly_scalar_mask_op4>%2, %1, %0<mask_scalar_operand4>|%0<mask_scalar_operand4>, %1, %2<round_saeonly_scalar_mask_op4>, %3}"
[(set_attr "prefix" "evex")
(set_attr "mode" "<ssescalarmode>")])
@@ -32672,7 +32649,7 @@
(unspec:VI1248_AVX10_2
[(match_operand:VI1248_AVX10_2 1 "memory_operand" "m")]
UNSPEC_VMOVRS))]
- "TARGET_AVX10_2_256 && TARGET_MOVRS"
+ "TARGET_AVX10_2 && TARGET_MOVRS"
"vmovrs<ssemodesuffix>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssemov")
(set_attr "prefix" "evex")
generated by cgit v1.1 at 2025-03-28 22:40:44 +0000