diff options
Diffstat (limited to 'gcc/config/i386/sse.md')
| -rw-r--r-- | gcc/config/i386/sse.md | 26 |
1 files changed, 21 insertions, 5 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index ed5ac1a..b280676 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1571,7 +1571,11 @@ "TARGET_AVX512VL || <MODE_SIZE> == 64" "vpternlogd\t{$0xFF, %0, %0, %0|%0, %0, %0, 0xFF}" [(set_attr "type" "sselog1") - (set_attr "prefix" "evex")]) + (set_attr "prefix" "evex") + (set (attr "mode") + (if_then_else (match_test "TARGET_AVX512VL") + (const_string "<sseinsnmode>") + (const_string "XI")))]) ;; If mem_addr points to a memory region with less than whole vector size bytes ;; of accessible memory and k is a mask that would prevent reading the inaccessible @@ -30845,7 +30849,10 @@ else return "vaesdec\t{%2, %1, %0|%0, %1, %2}"; } -[(set_attr "addr" "gpr16,*")]) +[(set_attr "isa" "avx,vaes_avx512vl") + (set_attr "type" "sselog1") + (set_attr "addr" "gpr16,*") + (set_attr "mode" "TI")]) (define_insn "vaesdeclast_<mode>" [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=x,v") @@ -30860,7 +30867,10 @@ else return "vaesdeclast\t{%2, %1, %0|%0, %1, %2}"; } -[(set_attr "addr" "gpr16,*")]) +[(set_attr "isa" "avx,vaes_avx512vl") + (set_attr "type" "sselog1") + (set_attr "addr" "gpr16,*") + (set_attr "mode" "TI")]) (define_insn "vaesenc_<mode>" [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=x,v") @@ -30875,7 +30885,10 @@ else return "vaesenc\t{%2, %1, %0|%0, %1, %2}"; } -[(set_attr "addr" "gpr16,*")]) +[(set_attr "isa" "avx,vaes_avx512vl") + (set_attr "type" "sselog1") + (set_attr "addr" "gpr16,*") + (set_attr "mode" "TI")]) (define_insn "vaesenclast_<mode>" [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=x,v") @@ -30890,7 +30903,10 @@ else return "vaesenclast\t{%2, %1, %0|%0, %1, %2}"; } -[(set_attr "addr" "gpr16,*")]) +[(set_attr "isa" "avx,vaes_avx512vl") + (set_attr "type" "sselog1") + (set_attr "addr" "gpr16,*") + (set_attr "mode" "TI")]) (define_insn "vpclmulqdq_<mode>" [(set (match_operand:VI8_FVL 0 "register_operand" "=v") |