diff options
Diffstat (limited to 'gcc/config/arm')
| -rw-r--r-- | gcc/config/arm/aarch-common.cc | 3 | ||||
| -rw-r--r-- | gcc/config/arm/aout.h | 5 | ||||
| -rw-r--r-- | gcc/config/arm/arm-builtins.cc | 1279 | ||||
| -rw-r--r-- | gcc/config/arm/arm-c.cc | 7 | ||||
| -rw-r--r-- | gcc/config/arm/arm-cpus.in | 28 | ||||
| -rw-r--r-- | gcc/config/arm/arm-generic.md | 4 | ||||
| -rw-r--r-- | gcc/config/arm/arm-opts.h | 1 | ||||
| -rw-r--r-- | gcc/config/arm/arm-protos.h | 8 | ||||
| -rw-r--r-- | gcc/config/arm/arm-tables.opt | 6 | ||||
| -rw-r--r-- | gcc/config/arm/arm-tune.md | 53 | ||||
| -rw-r--r-- | gcc/config/arm/arm.cc | 441 | ||||
| -rw-r--r-- | gcc/config/arm/arm.h | 175 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 43 | ||||
| -rw-r--r-- | gcc/config/arm/arm.opt | 3 | ||||
| -rw-r--r-- | gcc/config/arm/constraints.md | 18 | ||||
| -rw-r--r-- | gcc/config/arm/iterators.md | 20 | ||||
| -rw-r--r-- | gcc/config/arm/iwmmxt.md | 1766 | ||||
| -rw-r--r-- | gcc/config/arm/iwmmxt2.md | 903 | ||||
| -rw-r--r-- | gcc/config/arm/marvell-f-iwmmxt.md | 189 | ||||
| -rw-r--r-- | gcc/config/arm/predicates.md | 11 | ||||
| -rw-r--r-- | gcc/config/arm/t-arm | 3 | ||||
| -rw-r--r-- | gcc/config/arm/thumb2.md | 2 | ||||
| -rw-r--r-- | gcc/config/arm/types.md | 123 | ||||
| -rw-r--r-- | gcc/config/arm/unspecs.md | 29 | ||||
| -rw-r--r-- | gcc/config/arm/vec-common.md | 31 |
25 files changed, 159 insertions, 4992 deletions
diff --git a/gcc/config/arm/aarch-common.cc b/gcc/config/arm/aarch-common.cc index 3289853..9cd926e 100644 --- a/gcc/config/arm/aarch-common.cc +++ b/gcc/config/arm/aarch-common.cc @@ -655,8 +655,7 @@ arm_md_asm_adjust (vec<rtx> &outputs, vec<rtx> & /*inputs*/, emit_move_insn (dest, tmp); } } - rtx_insn *seq = get_insns (); - end_sequence (); + rtx_insn *seq = end_sequence (); return saw_asm_flag ? seq : NULL; } diff --git a/gcc/config/arm/aout.h b/gcc/config/arm/aout.h index cdce361..a9b0dfa 100644 --- a/gcc/config/arm/aout.h +++ b/gcc/config/arm/aout.h @@ -69,11 +69,6 @@ "d20", "?20", "d21", "?21", "d22", "?22", "d23", "?23", \ "d24", "?24", "d25", "?25", "d26", "?26", "d27", "?27", \ "d28", "?28", "d29", "?29", "d30", "?30", "d31", "?31", \ - "wr0", "wr1", "wr2", "wr3", \ - "wr4", "wr5", "wr6", "wr7", \ - "wr8", "wr9", "wr10", "wr11", \ - "wr12", "wr13", "wr14", "wr15", \ - "wcgr0", "wcgr1", "wcgr2", "wcgr3", \ "cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0", \ "ra_auth_code" \ } diff --git a/gcc/config/arm/arm-builtins.cc b/gcc/config/arm/arm-builtins.cc index c56ab5d..3bb2566 100644 --- a/gcc/config/arm/arm-builtins.cc +++ b/gcc/config/arm/arm-builtins.cc @@ -816,252 +816,6 @@ static arm_builtin_cde_datum cde_builtin_data[] = enum arm_builtins { - ARM_BUILTIN_GETWCGR0, - ARM_BUILTIN_GETWCGR1, - ARM_BUILTIN_GETWCGR2, - ARM_BUILTIN_GETWCGR3, - - ARM_BUILTIN_SETWCGR0, - ARM_BUILTIN_SETWCGR1, - ARM_BUILTIN_SETWCGR2, - ARM_BUILTIN_SETWCGR3, - - ARM_BUILTIN_WZERO, - - ARM_BUILTIN_WAVG2BR, - ARM_BUILTIN_WAVG2HR, - ARM_BUILTIN_WAVG2B, - ARM_BUILTIN_WAVG2H, - - ARM_BUILTIN_WACCB, - ARM_BUILTIN_WACCH, - ARM_BUILTIN_WACCW, - - ARM_BUILTIN_WMACS, - ARM_BUILTIN_WMACSZ, - ARM_BUILTIN_WMACU, - ARM_BUILTIN_WMACUZ, - - ARM_BUILTIN_WSADB, - ARM_BUILTIN_WSADBZ, - ARM_BUILTIN_WSADH, - ARM_BUILTIN_WSADHZ, - - ARM_BUILTIN_WALIGNI, - ARM_BUILTIN_WALIGNR0, - ARM_BUILTIN_WALIGNR1, - ARM_BUILTIN_WALIGNR2, - ARM_BUILTIN_WALIGNR3, - - ARM_BUILTIN_TMIA, - ARM_BUILTIN_TMIAPH, - ARM_BUILTIN_TMIABB, - ARM_BUILTIN_TMIABT, - ARM_BUILTIN_TMIATB, - ARM_BUILTIN_TMIATT, - - ARM_BUILTIN_TMOVMSKB, - ARM_BUILTIN_TMOVMSKH, - ARM_BUILTIN_TMOVMSKW, - - ARM_BUILTIN_TBCSTB, - ARM_BUILTIN_TBCSTH, - ARM_BUILTIN_TBCSTW, - - ARM_BUILTIN_WMADDS, - ARM_BUILTIN_WMADDU, - - ARM_BUILTIN_WPACKHSS, - ARM_BUILTIN_WPACKWSS, - ARM_BUILTIN_WPACKDSS, - ARM_BUILTIN_WPACKHUS, - ARM_BUILTIN_WPACKWUS, - ARM_BUILTIN_WPACKDUS, - - ARM_BUILTIN_WADDB, - ARM_BUILTIN_WADDH, - ARM_BUILTIN_WADDW, - ARM_BUILTIN_WADDSSB, - ARM_BUILTIN_WADDSSH, - ARM_BUILTIN_WADDSSW, - ARM_BUILTIN_WADDUSB, - ARM_BUILTIN_WADDUSH, - ARM_BUILTIN_WADDUSW, - ARM_BUILTIN_WSUBB, - ARM_BUILTIN_WSUBH, - ARM_BUILTIN_WSUBW, - ARM_BUILTIN_WSUBSSB, - ARM_BUILTIN_WSUBSSH, - ARM_BUILTIN_WSUBSSW, - ARM_BUILTIN_WSUBUSB, - ARM_BUILTIN_WSUBUSH, - ARM_BUILTIN_WSUBUSW, - - ARM_BUILTIN_WAND, - ARM_BUILTIN_WANDN, - ARM_BUILTIN_WOR, - ARM_BUILTIN_WXOR, - - ARM_BUILTIN_WCMPEQB, - ARM_BUILTIN_WCMPEQH, - ARM_BUILTIN_WCMPEQW, - ARM_BUILTIN_WCMPGTUB, - ARM_BUILTIN_WCMPGTUH, - ARM_BUILTIN_WCMPGTUW, - ARM_BUILTIN_WCMPGTSB, - ARM_BUILTIN_WCMPGTSH, - ARM_BUILTIN_WCMPGTSW, - - ARM_BUILTIN_TEXTRMSB, - ARM_BUILTIN_TEXTRMSH, - ARM_BUILTIN_TEXTRMSW, - ARM_BUILTIN_TEXTRMUB, - ARM_BUILTIN_TEXTRMUH, - ARM_BUILTIN_TEXTRMUW, - ARM_BUILTIN_TINSRB, - ARM_BUILTIN_TINSRH, - ARM_BUILTIN_TINSRW, - - ARM_BUILTIN_WMAXSW, - ARM_BUILTIN_WMAXSH, - ARM_BUILTIN_WMAXSB, - ARM_BUILTIN_WMAXUW, - ARM_BUILTIN_WMAXUH, - ARM_BUILTIN_WMAXUB, - ARM_BUILTIN_WMINSW, - ARM_BUILTIN_WMINSH, - ARM_BUILTIN_WMINSB, - ARM_BUILTIN_WMINUW, - ARM_BUILTIN_WMINUH, - ARM_BUILTIN_WMINUB, - - ARM_BUILTIN_WMULUM, - ARM_BUILTIN_WMULSM, - ARM_BUILTIN_WMULUL, - - ARM_BUILTIN_PSADBH, - ARM_BUILTIN_WSHUFH, - - ARM_BUILTIN_WSLLH, - ARM_BUILTIN_WSLLW, - ARM_BUILTIN_WSLLD, - ARM_BUILTIN_WSRAH, - ARM_BUILTIN_WSRAW, - ARM_BUILTIN_WSRAD, - ARM_BUILTIN_WSRLH, - ARM_BUILTIN_WSRLW, - ARM_BUILTIN_WSRLD, - ARM_BUILTIN_WRORH, - ARM_BUILTIN_WRORW, - ARM_BUILTIN_WRORD, - ARM_BUILTIN_WSLLHI, - ARM_BUILTIN_WSLLWI, - ARM_BUILTIN_WSLLDI, - ARM_BUILTIN_WSRAHI, - ARM_BUILTIN_WSRAWI, - ARM_BUILTIN_WSRADI, - ARM_BUILTIN_WSRLHI, - ARM_BUILTIN_WSRLWI, - ARM_BUILTIN_WSRLDI, - ARM_BUILTIN_WRORHI, - ARM_BUILTIN_WRORWI, - ARM_BUILTIN_WRORDI, - - ARM_BUILTIN_WUNPCKIHB, - ARM_BUILTIN_WUNPCKIHH, - ARM_BUILTIN_WUNPCKIHW, - ARM_BUILTIN_WUNPCKILB, - ARM_BUILTIN_WUNPCKILH, - ARM_BUILTIN_WUNPCKILW, - - ARM_BUILTIN_WUNPCKEHSB, - ARM_BUILTIN_WUNPCKEHSH, - ARM_BUILTIN_WUNPCKEHSW, - ARM_BUILTIN_WUNPCKEHUB, - ARM_BUILTIN_WUNPCKEHUH, - ARM_BUILTIN_WUNPCKEHUW, - ARM_BUILTIN_WUNPCKELSB, - ARM_BUILTIN_WUNPCKELSH, - ARM_BUILTIN_WUNPCKELSW, - ARM_BUILTIN_WUNPCKELUB, - ARM_BUILTIN_WUNPCKELUH, - ARM_BUILTIN_WUNPCKELUW, - - ARM_BUILTIN_WABSB, - ARM_BUILTIN_WABSH, - ARM_BUILTIN_WABSW, - - ARM_BUILTIN_WADDSUBHX, - ARM_BUILTIN_WSUBADDHX, - - ARM_BUILTIN_WABSDIFFB, - ARM_BUILTIN_WABSDIFFH, - ARM_BUILTIN_WABSDIFFW, - - ARM_BUILTIN_WADDCH, - ARM_BUILTIN_WADDCW, - - ARM_BUILTIN_WAVG4, - ARM_BUILTIN_WAVG4R, - - ARM_BUILTIN_WMADDSX, - ARM_BUILTIN_WMADDUX, - - ARM_BUILTIN_WMADDSN, - ARM_BUILTIN_WMADDUN, - - ARM_BUILTIN_WMULWSM, - ARM_BUILTIN_WMULWUM, - - ARM_BUILTIN_WMULWSMR, - ARM_BUILTIN_WMULWUMR, - - ARM_BUILTIN_WMULWL, - - ARM_BUILTIN_WMULSMR, - ARM_BUILTIN_WMULUMR, - - ARM_BUILTIN_WQMULM, - ARM_BUILTIN_WQMULMR, - - ARM_BUILTIN_WQMULWM, - ARM_BUILTIN_WQMULWMR, - - ARM_BUILTIN_WADDBHUSM, - ARM_BUILTIN_WADDBHUSL, - - ARM_BUILTIN_WQMIABB, - ARM_BUILTIN_WQMIABT, - ARM_BUILTIN_WQMIATB, - ARM_BUILTIN_WQMIATT, - - ARM_BUILTIN_WQMIABBN, - ARM_BUILTIN_WQMIABTN, - ARM_BUILTIN_WQMIATBN, - ARM_BUILTIN_WQMIATTN, - - ARM_BUILTIN_WMIABB, - ARM_BUILTIN_WMIABT, - ARM_BUILTIN_WMIATB, - ARM_BUILTIN_WMIATT, - - ARM_BUILTIN_WMIABBN, - ARM_BUILTIN_WMIABTN, - ARM_BUILTIN_WMIATBN, - ARM_BUILTIN_WMIATTN, - - ARM_BUILTIN_WMIAWBB, - ARM_BUILTIN_WMIAWBT, - ARM_BUILTIN_WMIAWTB, - ARM_BUILTIN_WMIAWTT, - - ARM_BUILTIN_WMIAWBBN, - ARM_BUILTIN_WMIAWBTN, - ARM_BUILTIN_WMIAWTBN, - ARM_BUILTIN_WMIAWTTN, - - ARM_BUILTIN_WMERGE, - ARM_BUILTIN_GET_FPSCR, ARM_BUILTIN_SET_FPSCR, ARM_BUILTIN_GET_FPSCR_NZCVQC, @@ -1878,115 +1632,6 @@ struct builtin_description static const struct builtin_description bdesc_2arg[] = { -#define IWMMXT_BUILTIN(code, string, builtin) \ - { isa_bit_iwmmxt, CODE_FOR_##code, \ - "__builtin_arm_" string, \ - ARM_BUILTIN_##builtin, UNKNOWN, 0 }, - -#define IWMMXT2_BUILTIN(code, string, builtin) \ - { isa_bit_iwmmxt2, CODE_FOR_##code, \ - "__builtin_arm_" string, \ - ARM_BUILTIN_##builtin, UNKNOWN, 0 }, - - IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB) - IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH) - IWMMXT_BUILTIN (addv2si3, "waddw", WADDW) - IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB) - IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH) - IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW) - IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB) - IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH) - IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW) - IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB) - IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH) - IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW) - IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB) - IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH) - IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW) - IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB) - IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH) - IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW) - IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL) - IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM) - IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM) - IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB) - IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH) - IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW) - IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB) - IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH) - IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW) - IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB) - IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH) - IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW) - IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB) - IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB) - IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH) - IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH) - IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW) - IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW) - IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB) - IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB) - IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH) - IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH) - IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW) - IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW) - IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND) - IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN) - IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR) - IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR) - IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B) - IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H) - IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR) - IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR) - IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB) - IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH) - IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW) - IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB) - IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH) - IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW) - IWMMXT2_BUILTIN (iwmmxt_waddsubhx, "waddsubhx", WADDSUBHX) - IWMMXT2_BUILTIN (iwmmxt_wsubaddhx, "wsubaddhx", WSUBADDHX) - IWMMXT2_BUILTIN (iwmmxt_wabsdiffb, "wabsdiffb", WABSDIFFB) - IWMMXT2_BUILTIN (iwmmxt_wabsdiffh, "wabsdiffh", WABSDIFFH) - IWMMXT2_BUILTIN (iwmmxt_wabsdiffw, "wabsdiffw", WABSDIFFW) - IWMMXT2_BUILTIN (iwmmxt_avg4, "wavg4", WAVG4) - IWMMXT2_BUILTIN (iwmmxt_avg4r, "wavg4r", WAVG4R) - IWMMXT2_BUILTIN (iwmmxt_wmulwsm, "wmulwsm", WMULWSM) - IWMMXT2_BUILTIN (iwmmxt_wmulwum, "wmulwum", WMULWUM) - IWMMXT2_BUILTIN (iwmmxt_wmulwsmr, "wmulwsmr", WMULWSMR) - IWMMXT2_BUILTIN (iwmmxt_wmulwumr, "wmulwumr", WMULWUMR) - IWMMXT2_BUILTIN (iwmmxt_wmulwl, "wmulwl", WMULWL) - IWMMXT2_BUILTIN (iwmmxt_wmulsmr, "wmulsmr", WMULSMR) - IWMMXT2_BUILTIN (iwmmxt_wmulumr, "wmulumr", WMULUMR) - IWMMXT2_BUILTIN (iwmmxt_wqmulm, "wqmulm", WQMULM) - IWMMXT2_BUILTIN (iwmmxt_wqmulmr, "wqmulmr", WQMULMR) - IWMMXT2_BUILTIN (iwmmxt_wqmulwm, "wqmulwm", WQMULWM) - IWMMXT2_BUILTIN (iwmmxt_wqmulwmr, "wqmulwmr", WQMULWMR) - IWMMXT_BUILTIN (iwmmxt_walignr0, "walignr0", WALIGNR0) - IWMMXT_BUILTIN (iwmmxt_walignr1, "walignr1", WALIGNR1) - IWMMXT_BUILTIN (iwmmxt_walignr2, "walignr2", WALIGNR2) - IWMMXT_BUILTIN (iwmmxt_walignr3, "walignr3", WALIGNR3) - -#define IWMMXT_BUILTIN2(code, builtin) \ - { isa_bit_iwmmxt, CODE_FOR_##code, NULL, \ - ARM_BUILTIN_##builtin, UNKNOWN, 0 }, - -#define IWMMXT2_BUILTIN2(code, builtin) \ - { isa_bit_iwmmxt2, CODE_FOR_##code, NULL, \ - ARM_BUILTIN_##builtin, UNKNOWN, 0 }, - - IWMMXT2_BUILTIN2 (iwmmxt_waddbhusm, WADDBHUSM) - IWMMXT2_BUILTIN2 (iwmmxt_waddbhusl, WADDBHUSL) - IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS) - IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS) - IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS) - IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS) - IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS) - IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS) - IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ) - IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ) - - #define FP_BUILTIN(L, U) \ {isa_nobit, CODE_FOR_##L, "__builtin_arm_"#L, ARM_BUILTIN_##U, \ UNKNOWN, 0}, @@ -2013,31 +1658,6 @@ static const struct builtin_description bdesc_2arg[] = static const struct builtin_description bdesc_1arg[] = { - IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB) - IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH) - IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW) - IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB) - IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH) - IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW) - IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB) - IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH) - IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW) - IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB) - IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH) - IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW) - IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB) - IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH) - IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW) - IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB) - IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH) - IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW) - IWMMXT2_BUILTIN (iwmmxt_wabsv8qi3, "wabsb", WABSB) - IWMMXT2_BUILTIN (iwmmxt_wabsv4hi3, "wabsh", WABSH) - IWMMXT2_BUILTIN (iwmmxt_wabsv2si3, "wabsw", WABSW) - IWMMXT_BUILTIN (tbcstv8qi, "tbcstb", TBCSTB) - IWMMXT_BUILTIN (tbcstv4hi, "tbcsth", TBCSTH) - IWMMXT_BUILTIN (tbcstv2si, "tbcstw", TBCSTW) - #define CRYPTO1(L, U, R, A) CRYPTO_BUILTIN (L, U) #define CRYPTO2(L, U, R, A1, A2) #define CRYPTO3(L, U, R, A1, A2, A3) @@ -2059,387 +1679,6 @@ static const struct builtin_description bdesc_3arg[] = }; #undef CRYPTO_BUILTIN -/* Set up all the iWMMXt builtins. This is not called if - TARGET_IWMMXT is zero. */ - -static void -arm_init_iwmmxt_builtins (void) -{ - const struct builtin_description * d; - size_t i; - - tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode); - tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode); - tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode); - - tree v8qi_ftype_v8qi_v8qi_int - = build_function_type_list (V8QI_type_node, - V8QI_type_node, V8QI_type_node, - integer_type_node, NULL_TREE); - tree v4hi_ftype_v4hi_int - = build_function_type_list (V4HI_type_node, - V4HI_type_node, integer_type_node, NULL_TREE); - tree v2si_ftype_v2si_int - = build_function_type_list (V2SI_type_node, - V2SI_type_node, integer_type_node, NULL_TREE); - tree v2si_ftype_di_di - = build_function_type_list (V2SI_type_node, - long_long_integer_type_node, - long_long_integer_type_node, - NULL_TREE); - tree di_ftype_di_int - = build_function_type_list (long_long_integer_type_node, - long_long_integer_type_node, - integer_type_node, NULL_TREE); - tree di_ftype_di_int_int - = build_function_type_list (long_long_integer_type_node, - long_long_integer_type_node, - integer_type_node, - integer_type_node, NULL_TREE); - tree int_ftype_v8qi - = build_function_type_list (integer_type_node, - V8QI_type_node, NULL_TREE); - tree int_ftype_v4hi - = build_function_type_list (integer_type_node, - V4HI_type_node, NULL_TREE); - tree int_ftype_v2si - = build_function_type_list (integer_type_node, - V2SI_type_node, NULL_TREE); - tree int_ftype_v8qi_int - = build_function_type_list (integer_type_node, - V8QI_type_node, integer_type_node, NULL_TREE); - tree int_ftype_v4hi_int - = build_function_type_list (integer_type_node, - V4HI_type_node, integer_type_node, NULL_TREE); - tree int_ftype_v2si_int - = build_function_type_list (integer_type_node, - V2SI_type_node, integer_type_node, NULL_TREE); - tree v8qi_ftype_v8qi_int_int - = build_function_type_list (V8QI_type_node, - V8QI_type_node, integer_type_node, - integer_type_node, NULL_TREE); - tree v4hi_ftype_v4hi_int_int - = build_function_type_list (V4HI_type_node, - V4HI_type_node, integer_type_node, - integer_type_node, NULL_TREE); - tree v2si_ftype_v2si_int_int - = build_function_type_list (V2SI_type_node, - V2SI_type_node, integer_type_node, - integer_type_node, NULL_TREE); - /* Miscellaneous. */ - tree v8qi_ftype_v4hi_v4hi - = build_function_type_list (V8QI_type_node, - V4HI_type_node, V4HI_type_node, NULL_TREE); - tree v4hi_ftype_v2si_v2si - = build_function_type_list (V4HI_type_node, - V2SI_type_node, V2SI_type_node, NULL_TREE); - tree v8qi_ftype_v4hi_v8qi - = build_function_type_list (V8QI_type_node, - V4HI_type_node, V8QI_type_node, NULL_TREE); - tree v2si_ftype_v4hi_v4hi - = build_function_type_list (V2SI_type_node, - V4HI_type_node, V4HI_type_node, NULL_TREE); - tree v2si_ftype_v8qi_v8qi - = build_function_type_list (V2SI_type_node, - V8QI_type_node, V8QI_type_node, NULL_TREE); - tree v4hi_ftype_v4hi_di - = build_function_type_list (V4HI_type_node, - V4HI_type_node, long_long_integer_type_node, - NULL_TREE); - tree v2si_ftype_v2si_di - = build_function_type_list (V2SI_type_node, - V2SI_type_node, long_long_integer_type_node, - NULL_TREE); - tree di_ftype_void - = build_function_type_list (long_long_unsigned_type_node, NULL_TREE); - tree int_ftype_void - = build_function_type_list (integer_type_node, NULL_TREE); - tree di_ftype_v8qi - = build_function_type_list (long_long_integer_type_node, - V8QI_type_node, NULL_TREE); - tree di_ftype_v4hi - = build_function_type_list (long_long_integer_type_node, - V4HI_type_node, NULL_TREE); - tree di_ftype_v2si - = build_function_type_list (long_long_integer_type_node, - V2SI_type_node, NULL_TREE); - tree v2si_ftype_v4hi - = build_function_type_list (V2SI_type_node, - V4HI_type_node, NULL_TREE); - tree v4hi_ftype_v8qi - = build_function_type_list (V4HI_type_node, - V8QI_type_node, NULL_TREE); - tree v8qi_ftype_v8qi - = build_function_type_list (V8QI_type_node, - V8QI_type_node, NULL_TREE); - tree v4hi_ftype_v4hi - = build_function_type_list (V4HI_type_node, - V4HI_type_node, NULL_TREE); - tree v2si_ftype_v2si - = build_function_type_list (V2SI_type_node, - V2SI_type_node, NULL_TREE); - - tree di_ftype_di_v4hi_v4hi - = build_function_type_list (long_long_unsigned_type_node, - long_long_unsigned_type_node, - V4HI_type_node, V4HI_type_node, - NULL_TREE); - - tree di_ftype_v4hi_v4hi - = build_function_type_list (long_long_unsigned_type_node, - V4HI_type_node,V4HI_type_node, - NULL_TREE); - - tree v2si_ftype_v2si_v4hi_v4hi - = build_function_type_list (V2SI_type_node, - V2SI_type_node, V4HI_type_node, - V4HI_type_node, NULL_TREE); - - tree v2si_ftype_v2si_v8qi_v8qi - = build_function_type_list (V2SI_type_node, - V2SI_type_node, V8QI_type_node, - V8QI_type_node, NULL_TREE); - - tree di_ftype_di_v2si_v2si - = build_function_type_list (long_long_unsigned_type_node, - long_long_unsigned_type_node, - V2SI_type_node, V2SI_type_node, - NULL_TREE); - - tree di_ftype_di_di_int - = build_function_type_list (long_long_unsigned_type_node, - long_long_unsigned_type_node, - long_long_unsigned_type_node, - integer_type_node, NULL_TREE); - - tree void_ftype_int - = build_function_type_list (void_type_node, - integer_type_node, NULL_TREE); - - tree v8qi_ftype_char - = build_function_type_list (V8QI_type_node, - signed_char_type_node, NULL_TREE); - - tree v4hi_ftype_short - = build_function_type_list (V4HI_type_node, - short_integer_type_node, NULL_TREE); - - tree v2si_ftype_int - = build_function_type_list (V2SI_type_node, - integer_type_node, NULL_TREE); - - /* Normal vector binops. */ - tree v8qi_ftype_v8qi_v8qi - = build_function_type_list (V8QI_type_node, - V8QI_type_node, V8QI_type_node, NULL_TREE); - tree v4hi_ftype_v4hi_v4hi - = build_function_type_list (V4HI_type_node, - V4HI_type_node,V4HI_type_node, NULL_TREE); - tree v2si_ftype_v2si_v2si - = build_function_type_list (V2SI_type_node, - V2SI_type_node, V2SI_type_node, NULL_TREE); - tree di_ftype_di_di - = build_function_type_list (long_long_unsigned_type_node, - long_long_unsigned_type_node, - long_long_unsigned_type_node, - NULL_TREE); - - /* Add all builtins that are more or less simple operations on two - operands. */ - for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) - { - /* Use one of the operands; the target can have a different mode for - mask-generating compares. */ - machine_mode mode; - tree type; - - if (d->name == 0 - || !(d->feature == isa_bit_iwmmxt - || d->feature == isa_bit_iwmmxt2)) - continue; - - mode = insn_data[d->icode].operand[1].mode; - - switch (mode) - { - case E_V8QImode: - type = v8qi_ftype_v8qi_v8qi; - break; - case E_V4HImode: - type = v4hi_ftype_v4hi_v4hi; - break; - case E_V2SImode: - type = v2si_ftype_v2si_v2si; - break; - case E_DImode: - type = di_ftype_di_di; - break; - - default: - gcc_unreachable (); - } - - def_mbuiltin (d->feature, d->name, type, d->code); - } - - /* Add the remaining MMX insns with somewhat more complicated types. */ -#define iwmmx_mbuiltin(NAME, TYPE, CODE) \ - def_mbuiltin (isa_bit_iwmmxt, "__builtin_arm_" NAME, \ - (TYPE), ARM_BUILTIN_ ## CODE) - -#define iwmmx2_mbuiltin(NAME, TYPE, CODE) \ - def_mbuiltin (isa_bit_iwmmxt2, "__builtin_arm_" NAME, \ - (TYPE), ARM_BUILTIN_ ## CODE) - - iwmmx_mbuiltin ("wzero", di_ftype_void, WZERO); - iwmmx_mbuiltin ("setwcgr0", void_ftype_int, SETWCGR0); - iwmmx_mbuiltin ("setwcgr1", void_ftype_int, SETWCGR1); - iwmmx_mbuiltin ("setwcgr2", void_ftype_int, SETWCGR2); - iwmmx_mbuiltin ("setwcgr3", void_ftype_int, SETWCGR3); - iwmmx_mbuiltin ("getwcgr0", int_ftype_void, GETWCGR0); - iwmmx_mbuiltin ("getwcgr1", int_ftype_void, GETWCGR1); - iwmmx_mbuiltin ("getwcgr2", int_ftype_void, GETWCGR2); - iwmmx_mbuiltin ("getwcgr3", int_ftype_void, GETWCGR3); - - iwmmx_mbuiltin ("wsllh", v4hi_ftype_v4hi_di, WSLLH); - iwmmx_mbuiltin ("wsllw", v2si_ftype_v2si_di, WSLLW); - iwmmx_mbuiltin ("wslld", di_ftype_di_di, WSLLD); - iwmmx_mbuiltin ("wsllhi", v4hi_ftype_v4hi_int, WSLLHI); - iwmmx_mbuiltin ("wsllwi", v2si_ftype_v2si_int, WSLLWI); - iwmmx_mbuiltin ("wslldi", di_ftype_di_int, WSLLDI); - - iwmmx_mbuiltin ("wsrlh", v4hi_ftype_v4hi_di, WSRLH); - iwmmx_mbuiltin ("wsrlw", v2si_ftype_v2si_di, WSRLW); - iwmmx_mbuiltin ("wsrld", di_ftype_di_di, WSRLD); - iwmmx_mbuiltin ("wsrlhi", v4hi_ftype_v4hi_int, WSRLHI); - iwmmx_mbuiltin ("wsrlwi", v2si_ftype_v2si_int, WSRLWI); - iwmmx_mbuiltin ("wsrldi", di_ftype_di_int, WSRLDI); - - iwmmx_mbuiltin ("wsrah", v4hi_ftype_v4hi_di, WSRAH); - iwmmx_mbuiltin ("wsraw", v2si_ftype_v2si_di, WSRAW); - iwmmx_mbuiltin ("wsrad", di_ftype_di_di, WSRAD); - iwmmx_mbuiltin ("wsrahi", v4hi_ftype_v4hi_int, WSRAHI); - iwmmx_mbuiltin ("wsrawi", v2si_ftype_v2si_int, WSRAWI); - iwmmx_mbuiltin ("wsradi", di_ftype_di_int, WSRADI); - - iwmmx_mbuiltin ("wrorh", v4hi_ftype_v4hi_di, WRORH); - iwmmx_mbuiltin ("wrorw", v2si_ftype_v2si_di, WRORW); - iwmmx_mbuiltin ("wrord", di_ftype_di_di, WRORD); - iwmmx_mbuiltin ("wrorhi", v4hi_ftype_v4hi_int, WRORHI); - iwmmx_mbuiltin ("wrorwi", v2si_ftype_v2si_int, WRORWI); - iwmmx_mbuiltin ("wrordi", di_ftype_di_int, WRORDI); - - iwmmx_mbuiltin ("wshufh", v4hi_ftype_v4hi_int, WSHUFH); - - iwmmx_mbuiltin ("wsadb", v2si_ftype_v2si_v8qi_v8qi, WSADB); - iwmmx_mbuiltin ("wsadh", v2si_ftype_v2si_v4hi_v4hi, WSADH); - iwmmx_mbuiltin ("wmadds", v2si_ftype_v4hi_v4hi, WMADDS); - iwmmx2_mbuiltin ("wmaddsx", v2si_ftype_v4hi_v4hi, WMADDSX); - iwmmx2_mbuiltin ("wmaddsn", v2si_ftype_v4hi_v4hi, WMADDSN); - iwmmx_mbuiltin ("wmaddu", v2si_ftype_v4hi_v4hi, WMADDU); - iwmmx2_mbuiltin ("wmaddux", v2si_ftype_v4hi_v4hi, WMADDUX); - iwmmx2_mbuiltin ("wmaddun", v2si_ftype_v4hi_v4hi, WMADDUN); - iwmmx_mbuiltin ("wsadbz", v2si_ftype_v8qi_v8qi, WSADBZ); - iwmmx_mbuiltin ("wsadhz", v2si_ftype_v4hi_v4hi, WSADHZ); - - iwmmx_mbuiltin ("textrmsb", int_ftype_v8qi_int, TEXTRMSB); - iwmmx_mbuiltin ("textrmsh", int_ftype_v4hi_int, TEXTRMSH); - iwmmx_mbuiltin ("textrmsw", int_ftype_v2si_int, TEXTRMSW); - iwmmx_mbuiltin ("textrmub", int_ftype_v8qi_int, TEXTRMUB); - iwmmx_mbuiltin ("textrmuh", int_ftype_v4hi_int, TEXTRMUH); - iwmmx_mbuiltin ("textrmuw", int_ftype_v2si_int, TEXTRMUW); - iwmmx_mbuiltin ("tinsrb", v8qi_ftype_v8qi_int_int, TINSRB); - iwmmx_mbuiltin ("tinsrh", v4hi_ftype_v4hi_int_int, TINSRH); - iwmmx_mbuiltin ("tinsrw", v2si_ftype_v2si_int_int, TINSRW); - - iwmmx_mbuiltin ("waccb", di_ftype_v8qi, WACCB); - iwmmx_mbuiltin ("wacch", di_ftype_v4hi, WACCH); - iwmmx_mbuiltin ("waccw", di_ftype_v2si, WACCW); - - iwmmx_mbuiltin ("tmovmskb", int_ftype_v8qi, TMOVMSKB); - iwmmx_mbuiltin ("tmovmskh", int_ftype_v4hi, TMOVMSKH); - iwmmx_mbuiltin ("tmovmskw", int_ftype_v2si, TMOVMSKW); - - iwmmx2_mbuiltin ("waddbhusm", v8qi_ftype_v4hi_v8qi, WADDBHUSM); - iwmmx2_mbuiltin ("waddbhusl", v8qi_ftype_v4hi_v8qi, WADDBHUSL); - - iwmmx_mbuiltin ("wpackhss", v8qi_ftype_v4hi_v4hi, WPACKHSS); - iwmmx_mbuiltin ("wpackhus", v8qi_ftype_v4hi_v4hi, WPACKHUS); - iwmmx_mbuiltin ("wpackwus", v4hi_ftype_v2si_v2si, WPACKWUS); - iwmmx_mbuiltin ("wpackwss", v4hi_ftype_v2si_v2si, WPACKWSS); - iwmmx_mbuiltin ("wpackdus", v2si_ftype_di_di, WPACKDUS); - iwmmx_mbuiltin ("wpackdss", v2si_ftype_di_di, WPACKDSS); - - iwmmx_mbuiltin ("wunpckehub", v4hi_ftype_v8qi, WUNPCKEHUB); - iwmmx_mbuiltin ("wunpckehuh", v2si_ftype_v4hi, WUNPCKEHUH); - iwmmx_mbuiltin ("wunpckehuw", di_ftype_v2si, WUNPCKEHUW); - iwmmx_mbuiltin ("wunpckehsb", v4hi_ftype_v8qi, WUNPCKEHSB); - iwmmx_mbuiltin ("wunpckehsh", v2si_ftype_v4hi, WUNPCKEHSH); - iwmmx_mbuiltin ("wunpckehsw", di_ftype_v2si, WUNPCKEHSW); - iwmmx_mbuiltin ("wunpckelub", v4hi_ftype_v8qi, WUNPCKELUB); - iwmmx_mbuiltin ("wunpckeluh", v2si_ftype_v4hi, WUNPCKELUH); - iwmmx_mbuiltin ("wunpckeluw", di_ftype_v2si, WUNPCKELUW); - iwmmx_mbuiltin ("wunpckelsb", v4hi_ftype_v8qi, WUNPCKELSB); - iwmmx_mbuiltin ("wunpckelsh", v2si_ftype_v4hi, WUNPCKELSH); - iwmmx_mbuiltin ("wunpckelsw", di_ftype_v2si, WUNPCKELSW); - - iwmmx_mbuiltin ("wmacs", di_ftype_di_v4hi_v4hi, WMACS); - iwmmx_mbuiltin ("wmacsz", di_ftype_v4hi_v4hi, WMACSZ); - iwmmx_mbuiltin ("wmacu", di_ftype_di_v4hi_v4hi, WMACU); - iwmmx_mbuiltin ("wmacuz", di_ftype_v4hi_v4hi, WMACUZ); - - iwmmx_mbuiltin ("walign", v8qi_ftype_v8qi_v8qi_int, WALIGNI); - iwmmx_mbuiltin ("tmia", di_ftype_di_int_int, TMIA); - iwmmx_mbuiltin ("tmiaph", di_ftype_di_int_int, TMIAPH); - iwmmx_mbuiltin ("tmiabb", di_ftype_di_int_int, TMIABB); - iwmmx_mbuiltin ("tmiabt", di_ftype_di_int_int, TMIABT); - iwmmx_mbuiltin ("tmiatb", di_ftype_di_int_int, TMIATB); - iwmmx_mbuiltin ("tmiatt", di_ftype_di_int_int, TMIATT); - - iwmmx2_mbuiltin ("wabsb", v8qi_ftype_v8qi, WABSB); - iwmmx2_mbuiltin ("wabsh", v4hi_ftype_v4hi, WABSH); - iwmmx2_mbuiltin ("wabsw", v2si_ftype_v2si, WABSW); - - iwmmx2_mbuiltin ("wqmiabb", v2si_ftype_v2si_v4hi_v4hi, WQMIABB); - iwmmx2_mbuiltin ("wqmiabt", v2si_ftype_v2si_v4hi_v4hi, WQMIABT); - iwmmx2_mbuiltin ("wqmiatb", v2si_ftype_v2si_v4hi_v4hi, WQMIATB); - iwmmx2_mbuiltin ("wqmiatt", v2si_ftype_v2si_v4hi_v4hi, WQMIATT); - - iwmmx2_mbuiltin ("wqmiabbn", v2si_ftype_v2si_v4hi_v4hi, WQMIABBN); - iwmmx2_mbuiltin ("wqmiabtn", v2si_ftype_v2si_v4hi_v4hi, WQMIABTN); - iwmmx2_mbuiltin ("wqmiatbn", v2si_ftype_v2si_v4hi_v4hi, WQMIATBN); - iwmmx2_mbuiltin ("wqmiattn", v2si_ftype_v2si_v4hi_v4hi, WQMIATTN); - - iwmmx2_mbuiltin ("wmiabb", di_ftype_di_v4hi_v4hi, WMIABB); - iwmmx2_mbuiltin ("wmiabt", di_ftype_di_v4hi_v4hi, WMIABT); - iwmmx2_mbuiltin ("wmiatb", di_ftype_di_v4hi_v4hi, WMIATB); - iwmmx2_mbuiltin ("wmiatt", di_ftype_di_v4hi_v4hi, WMIATT); - - iwmmx2_mbuiltin ("wmiabbn", di_ftype_di_v4hi_v4hi, WMIABBN); - iwmmx2_mbuiltin ("wmiabtn", di_ftype_di_v4hi_v4hi, WMIABTN); - iwmmx2_mbuiltin ("wmiatbn", di_ftype_di_v4hi_v4hi, WMIATBN); - iwmmx2_mbuiltin ("wmiattn", di_ftype_di_v4hi_v4hi, WMIATTN); - - iwmmx2_mbuiltin ("wmiawbb", di_ftype_di_v2si_v2si, WMIAWBB); - iwmmx2_mbuiltin ("wmiawbt", di_ftype_di_v2si_v2si, WMIAWBT); - iwmmx2_mbuiltin ("wmiawtb", di_ftype_di_v2si_v2si, WMIAWTB); - iwmmx2_mbuiltin ("wmiawtt", di_ftype_di_v2si_v2si, WMIAWTT); - - iwmmx2_mbuiltin ("wmiawbbn", di_ftype_di_v2si_v2si, WMIAWBBN); - iwmmx2_mbuiltin ("wmiawbtn", di_ftype_di_v2si_v2si, WMIAWBTN); - iwmmx2_mbuiltin ("wmiawtbn", di_ftype_di_v2si_v2si, WMIAWTBN); - iwmmx2_mbuiltin ("wmiawttn", di_ftype_di_v2si_v2si, WMIAWTTN); - - iwmmx2_mbuiltin ("wmerge", di_ftype_di_di_int, WMERGE); - - iwmmx_mbuiltin ("tbcstb", v8qi_ftype_char, TBCSTB); - iwmmx_mbuiltin ("tbcsth", v4hi_ftype_short, TBCSTH); - iwmmx_mbuiltin ("tbcstw", v2si_ftype_int, TBCSTW); - -#undef iwmmx_mbuiltin -#undef iwmmx2_mbuiltin -} - static void arm_init_fp16_builtins (void) { @@ -2454,9 +1693,6 @@ arm_init_fp16_builtins (void) void arm_init_builtins (void) { - if (TARGET_REALLY_IWMMXT) - arm_init_iwmmxt_builtins (); - /* This creates the arm_simd_floatHF_type_node so must come before arm_init_neon_builtins which uses it. */ arm_init_fp16_builtins (); @@ -2546,15 +1782,11 @@ arm_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED) clear instructions. */ static rtx -safe_vector_operand (rtx x, machine_mode mode) +safe_vector_operand (rtx x, machine_mode mode ATTRIBUTE_UNUSED) { if (x != const0_rtx) return x; - x = gen_reg_rtx (mode); - - emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x - : gen_rtx_SUBREG (DImode, x, 0))); - return x; + __builtin_unreachable (); } /* Function to expand ternary builtins. */ @@ -3053,8 +2285,7 @@ constant_arg: builtin and error out if not. */ start_sequence (); emit_insn (pat); - insn = get_insns (); - end_sequence (); + insn = end_sequence (); if (recog_memoized (insn) < 0) error ("this builtin is not supported for this target"); @@ -3266,21 +2497,10 @@ arm_general_expand_builtin (unsigned int fcode, const struct builtin_description * d; enum insn_code icode; tree arg0; - tree arg1; - tree arg2; rtx op0; rtx op1; - rtx op2; rtx pat; size_t i; - machine_mode tmode; - machine_mode mode0; - machine_mode mode1; - machine_mode mode2; - int opint; - int selector; - int mask; - int imm; if (fcode == ARM_BUILTIN_SIMD_LANE_CHECK) { @@ -3369,499 +2589,6 @@ arm_general_expand_builtin (unsigned int fcode, emit_insn (gen_cstoresi4 (target, op1, target, const0_rtx)); return target; - case ARM_BUILTIN_TEXTRMSB: - case ARM_BUILTIN_TEXTRMUB: - case ARM_BUILTIN_TEXTRMSH: - case ARM_BUILTIN_TEXTRMUH: - case ARM_BUILTIN_TEXTRMSW: - case ARM_BUILTIN_TEXTRMUW: - icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb - : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub - : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh - : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh - : CODE_FOR_iwmmxt_textrmw); - - arg0 = CALL_EXPR_ARG (exp, 0); - arg1 = CALL_EXPR_ARG (exp, 1); - op0 = expand_normal (arg0); - op1 = expand_normal (arg1); - tmode = insn_data[icode].operand[0].mode; - mode0 = insn_data[icode].operand[1].mode; - mode1 = insn_data[icode].operand[2].mode; - - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) - { - /* @@@ better error message */ - error ("selector must be an immediate"); - return gen_reg_rtx (tmode); - } - - opint = INTVAL (op1); - if (fcode == ARM_BUILTIN_TEXTRMSB || fcode == ARM_BUILTIN_TEXTRMUB) - { - if (opint > 7 || opint < 0) - error ("the range of selector should be in 0 to 7"); - } - else if (fcode == ARM_BUILTIN_TEXTRMSH || fcode == ARM_BUILTIN_TEXTRMUH) - { - if (opint > 3 || opint < 0) - error ("the range of selector should be in 0 to 3"); - } - else /* ARM_BUILTIN_TEXTRMSW || ARM_BUILTIN_TEXTRMUW. */ - { - if (opint > 1 || opint < 0) - error ("the range of selector should be in 0 to 1"); - } - - if (target == 0 - || GET_MODE (target) != tmode - || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); - pat = GEN_FCN (icode) (target, op0, op1); - if (! pat) - return 0; - emit_insn (pat); - return target; - - case ARM_BUILTIN_WALIGNI: - /* If op2 is immediate, call walighi, else call walighr. */ - arg0 = CALL_EXPR_ARG (exp, 0); - arg1 = CALL_EXPR_ARG (exp, 1); - arg2 = CALL_EXPR_ARG (exp, 2); - op0 = expand_normal (arg0); - op1 = expand_normal (arg1); - op2 = expand_normal (arg2); - if (CONST_INT_P (op2)) - { - icode = CODE_FOR_iwmmxt_waligni; - tmode = insn_data[icode].operand[0].mode; - mode0 = insn_data[icode].operand[1].mode; - mode1 = insn_data[icode].operand[2].mode; - mode2 = insn_data[icode].operand[3].mode; - if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - if (!(*insn_data[icode].operand[2].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); - gcc_assert ((*insn_data[icode].operand[3].predicate) (op2, mode2)); - selector = INTVAL (op2); - if (selector > 7 || selector < 0) - error ("the range of selector should be in 0 to 7"); - } - else - { - icode = CODE_FOR_iwmmxt_walignr; - tmode = insn_data[icode].operand[0].mode; - mode0 = insn_data[icode].operand[1].mode; - mode1 = insn_data[icode].operand[2].mode; - mode2 = insn_data[icode].operand[3].mode; - if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - if (!(*insn_data[icode].operand[2].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); - if (!(*insn_data[icode].operand[3].predicate) (op2, mode2)) - op2 = copy_to_mode_reg (mode2, op2); - } - if (target == 0 - || GET_MODE (target) != tmode - || !(*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); - pat = GEN_FCN (icode) (target, op0, op1, op2); - if (!pat) - return 0; - emit_insn (pat); - return target; - - case ARM_BUILTIN_TINSRB: - case ARM_BUILTIN_TINSRH: - case ARM_BUILTIN_TINSRW: - case ARM_BUILTIN_WMERGE: - icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb - : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh - : fcode == ARM_BUILTIN_WMERGE ? CODE_FOR_iwmmxt_wmerge - : CODE_FOR_iwmmxt_tinsrw); - arg0 = CALL_EXPR_ARG (exp, 0); - arg1 = CALL_EXPR_ARG (exp, 1); - arg2 = CALL_EXPR_ARG (exp, 2); - op0 = expand_normal (arg0); - op1 = expand_normal (arg1); - op2 = expand_normal (arg2); - tmode = insn_data[icode].operand[0].mode; - mode0 = insn_data[icode].operand[1].mode; - mode1 = insn_data[icode].operand[2].mode; - mode2 = insn_data[icode].operand[3].mode; - - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); - if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) - { - error ("selector must be an immediate"); - return const0_rtx; - } - if (icode == CODE_FOR_iwmmxt_wmerge) - { - selector = INTVAL (op2); - if (selector > 7 || selector < 0) - error ("the range of selector should be in 0 to 7"); - } - if ((icode == CODE_FOR_iwmmxt_tinsrb) - || (icode == CODE_FOR_iwmmxt_tinsrh) - || (icode == CODE_FOR_iwmmxt_tinsrw)) - { - mask = 0x01; - selector= INTVAL (op2); - if (icode == CODE_FOR_iwmmxt_tinsrb && (selector < 0 || selector > 7)) - error ("the range of selector should be in 0 to 7"); - else if (icode == CODE_FOR_iwmmxt_tinsrh && (selector < 0 ||selector > 3)) - error ("the range of selector should be in 0 to 3"); - else if (icode == CODE_FOR_iwmmxt_tinsrw && (selector < 0 ||selector > 1)) - error ("the range of selector should be in 0 to 1"); - mask <<= selector; - op2 = GEN_INT (mask); - } - if (target == 0 - || GET_MODE (target) != tmode - || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); - pat = GEN_FCN (icode) (target, op0, op1, op2); - if (! pat) - return 0; - emit_insn (pat); - return target; - - case ARM_BUILTIN_SETWCGR0: - case ARM_BUILTIN_SETWCGR1: - case ARM_BUILTIN_SETWCGR2: - case ARM_BUILTIN_SETWCGR3: - icode = (fcode == ARM_BUILTIN_SETWCGR0 ? CODE_FOR_iwmmxt_setwcgr0 - : fcode == ARM_BUILTIN_SETWCGR1 ? CODE_FOR_iwmmxt_setwcgr1 - : fcode == ARM_BUILTIN_SETWCGR2 ? CODE_FOR_iwmmxt_setwcgr2 - : CODE_FOR_iwmmxt_setwcgr3); - arg0 = CALL_EXPR_ARG (exp, 0); - op0 = expand_normal (arg0); - mode0 = insn_data[icode].operand[0].mode; - if (!(*insn_data[icode].operand[0].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - pat = GEN_FCN (icode) (op0); - if (!pat) - return 0; - emit_insn (pat); - return 0; - - case ARM_BUILTIN_GETWCGR0: - case ARM_BUILTIN_GETWCGR1: - case ARM_BUILTIN_GETWCGR2: - case ARM_BUILTIN_GETWCGR3: - icode = (fcode == ARM_BUILTIN_GETWCGR0 ? CODE_FOR_iwmmxt_getwcgr0 - : fcode == ARM_BUILTIN_GETWCGR1 ? CODE_FOR_iwmmxt_getwcgr1 - : fcode == ARM_BUILTIN_GETWCGR2 ? CODE_FOR_iwmmxt_getwcgr2 - : CODE_FOR_iwmmxt_getwcgr3); - tmode = insn_data[icode].operand[0].mode; - if (target == 0 - || GET_MODE (target) != tmode - || !(*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); - pat = GEN_FCN (icode) (target); - if (!pat) - return 0; - emit_insn (pat); - return target; - - case ARM_BUILTIN_WSHUFH: - icode = CODE_FOR_iwmmxt_wshufh; - arg0 = CALL_EXPR_ARG (exp, 0); - arg1 = CALL_EXPR_ARG (exp, 1); - op0 = expand_normal (arg0); - op1 = expand_normal (arg1); - tmode = insn_data[icode].operand[0].mode; - mode1 = insn_data[icode].operand[1].mode; - mode2 = insn_data[icode].operand[2].mode; - - if (! (*insn_data[icode].operand[1].predicate) (op0, mode1)) - op0 = copy_to_mode_reg (mode1, op0); - if (! (*insn_data[icode].operand[2].predicate) (op1, mode2)) - { - error ("mask must be an immediate"); - return const0_rtx; - } - selector = INTVAL (op1); - if (selector < 0 || selector > 255) - error ("the range of mask should be in 0 to 255"); - if (target == 0 - || GET_MODE (target) != tmode - || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); - pat = GEN_FCN (icode) (target, op0, op1); - if (! pat) - return 0; - emit_insn (pat); - return target; - - case ARM_BUILTIN_WMADDS: - return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmadds, exp, target); - case ARM_BUILTIN_WMADDSX: - return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmaddsx, exp, target); - case ARM_BUILTIN_WMADDSN: - return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmaddsn, exp, target); - case ARM_BUILTIN_WMADDU: - return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmaddu, exp, target); - case ARM_BUILTIN_WMADDUX: - return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmaddux, exp, target); - case ARM_BUILTIN_WMADDUN: - return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmaddun, exp, target); - case ARM_BUILTIN_WSADBZ: - return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, exp, target); - case ARM_BUILTIN_WSADHZ: - return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, exp, target); - - /* Several three-argument builtins. */ - case ARM_BUILTIN_WMACS: - case ARM_BUILTIN_WMACU: - case ARM_BUILTIN_TMIA: - case ARM_BUILTIN_TMIAPH: - case ARM_BUILTIN_TMIATT: - case ARM_BUILTIN_TMIATB: - case ARM_BUILTIN_TMIABT: - case ARM_BUILTIN_TMIABB: - case ARM_BUILTIN_WQMIABB: - case ARM_BUILTIN_WQMIABT: - case ARM_BUILTIN_WQMIATB: - case ARM_BUILTIN_WQMIATT: - case ARM_BUILTIN_WQMIABBN: - case ARM_BUILTIN_WQMIABTN: - case ARM_BUILTIN_WQMIATBN: - case ARM_BUILTIN_WQMIATTN: - case ARM_BUILTIN_WMIABB: - case ARM_BUILTIN_WMIABT: - case ARM_BUILTIN_WMIATB: - case ARM_BUILTIN_WMIATT: - case ARM_BUILTIN_WMIABBN: - case ARM_BUILTIN_WMIABTN: - case ARM_BUILTIN_WMIATBN: - case ARM_BUILTIN_WMIATTN: - case ARM_BUILTIN_WMIAWBB: - case ARM_BUILTIN_WMIAWBT: - case ARM_BUILTIN_WMIAWTB: - case ARM_BUILTIN_WMIAWTT: - case ARM_BUILTIN_WMIAWBBN: - case ARM_BUILTIN_WMIAWBTN: - case ARM_BUILTIN_WMIAWTBN: - case ARM_BUILTIN_WMIAWTTN: - case ARM_BUILTIN_WSADB: - case ARM_BUILTIN_WSADH: - icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs - : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu - : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia - : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph - : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb - : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt - : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb - : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt - : fcode == ARM_BUILTIN_WQMIABB ? CODE_FOR_iwmmxt_wqmiabb - : fcode == ARM_BUILTIN_WQMIABT ? CODE_FOR_iwmmxt_wqmiabt - : fcode == ARM_BUILTIN_WQMIATB ? CODE_FOR_iwmmxt_wqmiatb - : fcode == ARM_BUILTIN_WQMIATT ? CODE_FOR_iwmmxt_wqmiatt - : fcode == ARM_BUILTIN_WQMIABBN ? CODE_FOR_iwmmxt_wqmiabbn - : fcode == ARM_BUILTIN_WQMIABTN ? CODE_FOR_iwmmxt_wqmiabtn - : fcode == ARM_BUILTIN_WQMIATBN ? CODE_FOR_iwmmxt_wqmiatbn - : fcode == ARM_BUILTIN_WQMIATTN ? CODE_FOR_iwmmxt_wqmiattn - : fcode == ARM_BUILTIN_WMIABB ? CODE_FOR_iwmmxt_wmiabb - : fcode == ARM_BUILTIN_WMIABT ? CODE_FOR_iwmmxt_wmiabt - : fcode == ARM_BUILTIN_WMIATB ? CODE_FOR_iwmmxt_wmiatb - : fcode == ARM_BUILTIN_WMIATT ? CODE_FOR_iwmmxt_wmiatt - : fcode == ARM_BUILTIN_WMIABBN ? CODE_FOR_iwmmxt_wmiabbn - : fcode == ARM_BUILTIN_WMIABTN ? CODE_FOR_iwmmxt_wmiabtn - : fcode == ARM_BUILTIN_WMIATBN ? CODE_FOR_iwmmxt_wmiatbn - : fcode == ARM_BUILTIN_WMIATTN ? CODE_FOR_iwmmxt_wmiattn - : fcode == ARM_BUILTIN_WMIAWBB ? CODE_FOR_iwmmxt_wmiawbb - : fcode == ARM_BUILTIN_WMIAWBT ? CODE_FOR_iwmmxt_wmiawbt - : fcode == ARM_BUILTIN_WMIAWTB ? CODE_FOR_iwmmxt_wmiawtb - : fcode == ARM_BUILTIN_WMIAWTT ? CODE_FOR_iwmmxt_wmiawtt - : fcode == ARM_BUILTIN_WMIAWBBN ? CODE_FOR_iwmmxt_wmiawbbn - : fcode == ARM_BUILTIN_WMIAWBTN ? CODE_FOR_iwmmxt_wmiawbtn - : fcode == ARM_BUILTIN_WMIAWTBN ? CODE_FOR_iwmmxt_wmiawtbn - : fcode == ARM_BUILTIN_WMIAWTTN ? CODE_FOR_iwmmxt_wmiawttn - : fcode == ARM_BUILTIN_WSADB ? CODE_FOR_iwmmxt_wsadb - : CODE_FOR_iwmmxt_wsadh); - arg0 = CALL_EXPR_ARG (exp, 0); - arg1 = CALL_EXPR_ARG (exp, 1); - arg2 = CALL_EXPR_ARG (exp, 2); - op0 = expand_normal (arg0); - op1 = expand_normal (arg1); - op2 = expand_normal (arg2); - tmode = insn_data[icode].operand[0].mode; - mode0 = insn_data[icode].operand[1].mode; - mode1 = insn_data[icode].operand[2].mode; - mode2 = insn_data[icode].operand[3].mode; - - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); - if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) - op2 = copy_to_mode_reg (mode2, op2); - if (target == 0 - || GET_MODE (target) != tmode - || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); - pat = GEN_FCN (icode) (target, op0, op1, op2); - if (! pat) - return 0; - emit_insn (pat); - return target; - - case ARM_BUILTIN_WZERO: - target = gen_reg_rtx (DImode); - emit_insn (gen_iwmmxt_clrdi (target)); - return target; - - case ARM_BUILTIN_WSRLHI: - case ARM_BUILTIN_WSRLWI: - case ARM_BUILTIN_WSRLDI: - case ARM_BUILTIN_WSLLHI: - case ARM_BUILTIN_WSLLWI: - case ARM_BUILTIN_WSLLDI: - case ARM_BUILTIN_WSRAHI: - case ARM_BUILTIN_WSRAWI: - case ARM_BUILTIN_WSRADI: - case ARM_BUILTIN_WRORHI: - case ARM_BUILTIN_WRORWI: - case ARM_BUILTIN_WRORDI: - case ARM_BUILTIN_WSRLH: - case ARM_BUILTIN_WSRLW: - case ARM_BUILTIN_WSRLD: - case ARM_BUILTIN_WSLLH: - case ARM_BUILTIN_WSLLW: - case ARM_BUILTIN_WSLLD: - case ARM_BUILTIN_WSRAH: - case ARM_BUILTIN_WSRAW: - case ARM_BUILTIN_WSRAD: - case ARM_BUILTIN_WRORH: - case ARM_BUILTIN_WRORW: - case ARM_BUILTIN_WRORD: - icode = (fcode == ARM_BUILTIN_WSRLHI ? CODE_FOR_lshrv4hi3_iwmmxt - : fcode == ARM_BUILTIN_WSRLWI ? CODE_FOR_lshrv2si3_iwmmxt - : fcode == ARM_BUILTIN_WSRLDI ? CODE_FOR_lshrdi3_iwmmxt - : fcode == ARM_BUILTIN_WSLLHI ? CODE_FOR_ashlv4hi3_iwmmxt - : fcode == ARM_BUILTIN_WSLLWI ? CODE_FOR_ashlv2si3_iwmmxt - : fcode == ARM_BUILTIN_WSLLDI ? CODE_FOR_ashldi3_iwmmxt - : fcode == ARM_BUILTIN_WSRAHI ? CODE_FOR_ashrv4hi3_iwmmxt - : fcode == ARM_BUILTIN_WSRAWI ? CODE_FOR_ashrv2si3_iwmmxt - : fcode == ARM_BUILTIN_WSRADI ? CODE_FOR_ashrdi3_iwmmxt - : fcode == ARM_BUILTIN_WRORHI ? CODE_FOR_rorv4hi3 - : fcode == ARM_BUILTIN_WRORWI ? CODE_FOR_rorv2si3 - : fcode == ARM_BUILTIN_WRORDI ? CODE_FOR_rordi3 - : fcode == ARM_BUILTIN_WSRLH ? CODE_FOR_lshrv4hi3_di - : fcode == ARM_BUILTIN_WSRLW ? CODE_FOR_lshrv2si3_di - : fcode == ARM_BUILTIN_WSRLD ? CODE_FOR_lshrdi3_di - : fcode == ARM_BUILTIN_WSLLH ? CODE_FOR_ashlv4hi3_di - : fcode == ARM_BUILTIN_WSLLW ? CODE_FOR_ashlv2si3_di - : fcode == ARM_BUILTIN_WSLLD ? CODE_FOR_ashldi3_di - : fcode == ARM_BUILTIN_WSRAH ? CODE_FOR_ashrv4hi3_di - : fcode == ARM_BUILTIN_WSRAW ? CODE_FOR_ashrv2si3_di - : fcode == ARM_BUILTIN_WSRAD ? CODE_FOR_ashrdi3_di - : fcode == ARM_BUILTIN_WRORH ? CODE_FOR_rorv4hi3_di - : fcode == ARM_BUILTIN_WRORW ? CODE_FOR_rorv2si3_di - : fcode == ARM_BUILTIN_WRORD ? CODE_FOR_rordi3_di - : CODE_FOR_nothing); - arg1 = CALL_EXPR_ARG (exp, 1); - op1 = expand_normal (arg1); - if (GET_MODE (op1) == VOIDmode) - { - imm = INTVAL (op1); - if ((fcode == ARM_BUILTIN_WRORWI || fcode == ARM_BUILTIN_WRORW) - && (imm < 0 || imm > 32)) - { - const char *builtin = (fcode == ARM_BUILTIN_WRORWI - ? "_mm_rori_pi32" : "_mm_ror_pi32"); - error ("the range of count should be in 0 to 32; " - "please check the intrinsic %qs in code", builtin); - } - else if ((fcode == ARM_BUILTIN_WRORHI || fcode == ARM_BUILTIN_WRORH) - && (imm < 0 || imm > 16)) - { - const char *builtin = (fcode == ARM_BUILTIN_WRORHI - ? "_mm_rori_pi16" : "_mm_ror_pi16"); - error ("the range of count should be in 0 to 16; " - "please check the intrinsic %qs in code", builtin); - } - else if ((fcode == ARM_BUILTIN_WRORDI || fcode == ARM_BUILTIN_WRORD) - && (imm < 0 || imm > 64)) - { - const char *builtin = (fcode == ARM_BUILTIN_WRORDI - ? "_mm_rori_si64" : "_mm_ror_si64"); - error ("the range of count should be in 0 to 64; " - "please check the intrinsic %qs in code", builtin); - } - else if (imm < 0) - { - const char *builtin; - switch (fcode) - { - case ARM_BUILTIN_WSRLHI: - builtin = "_mm_srli_pi16"; - break; - case ARM_BUILTIN_WSRLWI: - builtin = "_mm_srli_pi32"; - break; - case ARM_BUILTIN_WSRLDI: - builtin = "_mm_srli_si64"; - break; - case ARM_BUILTIN_WSLLHI: - builtin = "_mm_slli_pi16"; - break; - case ARM_BUILTIN_WSLLWI: - builtin = "_mm_slli_pi32"; - break; - case ARM_BUILTIN_WSLLDI: - builtin = "_mm_slli_si64"; - break; - case ARM_BUILTIN_WSRAHI: - builtin = "_mm_srai_pi16"; - break; - case ARM_BUILTIN_WSRAWI: - builtin = "_mm_srai_pi32"; - break; - case ARM_BUILTIN_WSRADI: - builtin = "_mm_srai_si64"; - break; - case ARM_BUILTIN_WSRLH: - builtin = "_mm_srl_pi16"; - break; - case ARM_BUILTIN_WSRLW: - builtin = "_mm_srl_pi32"; - break; - case ARM_BUILTIN_WSRLD: - builtin = "_mm_srl_si64"; - break; - case ARM_BUILTIN_WSLLH: - builtin = "_mm_sll_pi16"; - break; - case ARM_BUILTIN_WSLLW: - builtin = "_mm_sll_pi32"; - break; - case ARM_BUILTIN_WSLLD: - builtin = "_mm_sll_si64"; - break; - case ARM_BUILTIN_WSRAH: - builtin = "_mm_sra_pi16"; - break; - case ARM_BUILTIN_WSRAW: - builtin = "_mm_sra_si64"; - break; - default: - builtin = "_mm_sra_si64"; - break; - } - error ("the count should be no less than 0; " - "please check the intrinsic %qs in code", builtin); - } - } - return arm_expand_binop_builtin (icode, exp, target); - default: break; } diff --git a/gcc/config/arm/arm-c.cc b/gcc/config/arm/arm-c.cc index 15e4080..d257e62 100644 --- a/gcc/config/arm/arm-c.cc +++ b/gcc/config/arm/arm-c.cc @@ -373,13 +373,6 @@ arm_cpu_builtins (struct cpp_reader* pfile) builtin_define (arm_arch_name); if (arm_arch_xscale) builtin_define ("__XSCALE__"); - if (arm_arch_iwmmxt) - { - builtin_define ("__IWMMXT__"); - builtin_define ("__ARM_WMMX"); - } - if (arm_arch_iwmmxt2) - builtin_define ("__IWMMXT2__"); /* ARMv6KZ was originally identified as the misspelled __ARM_ARCH_6ZK__. To preserve the existing behavior, the misspelled feature macro must still be defined. */ diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index 1939d55..7f5a8c6 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -102,12 +102,6 @@ define feature armv8 # ARMv8 CRC32 instructions. define feature crc32 -# XScale v2 (Wireless MMX). -define feature iwmmxt - -# XScale Wireless MMX2. -define feature iwmmxt2 - # Architecture rel 8.1. define feature armv8_1 @@ -778,18 +772,19 @@ begin arch armv9-a option bf16 add bf16 FP_ARMv8 DOTPROD end arch armv9-a +# We no-longer support the iwmmxt{,2} extensions, so treat these like xscale. begin arch iwmmxt - tune for iwmmxt + tune for xscale tune flags LDSCHED STRONG XSCALE base 5TE - isa ARMv5te xscale iwmmxt + isa ARMv5te xscale end arch iwmmxt begin arch iwmmxt2 - tune for iwmmxt2 + tune for xscale tune flags LDSCHED STRONG XSCALE base 5TE - isa ARMv5te xscale iwmmxt iwmmxt2 + isa ARMv5te xscale end arch iwmmxt2 # CPU entries @@ -924,23 +919,12 @@ end cpu arm10e begin cpu xscale tune flags LDSCHED XSCALE + alias iwmmxt iwmmxt2 architecture armv5te isa xscale costs xscale end cpu xscale -begin cpu iwmmxt - tune flags LDSCHED XSCALE - architecture iwmmxt - costs xscale -end cpu iwmmxt - -begin cpu iwmmxt2 - tune flags LDSCHED XSCALE - architecture iwmmxt2 - costs xscale -end cpu iwmmxt2 - begin cpu fa606te tune flags LDSCHED architecture armv5te diff --git a/gcc/config/arm/arm-generic.md b/gcc/config/arm/arm-generic.md index c270056..a8af0e6 100644 --- a/gcc/config/arm/arm-generic.md +++ b/gcc/config/arm/arm-generic.md @@ -96,14 +96,14 @@ (and (eq_attr "generic_sched" "yes") (and (eq_attr "ldsched" "yes") (and (eq_attr "type" "load_byte,load_4") - (eq_attr "tune" "xscale,iwmmxt,iwmmxt2")))) + (eq_attr "tune" "xscale")))) "core") (define_insn_reservation "load_ldsched" 2 (and (eq_attr "generic_sched" "yes") (and (eq_attr "ldsched" "yes") (and (eq_attr "type" "load_byte,load_4") - (eq_attr "tune" "!xscale,iwmmxt,iwmmxt2")))) + (eq_attr "tune" "!xscale")))) "core") (define_insn_reservation "load_or_store" 2 diff --git a/gcc/config/arm/arm-opts.h b/gcc/config/arm/arm-opts.h index 06a1939..5c543bf 100644 --- a/gcc/config/arm/arm-opts.h +++ b/gcc/config/arm/arm-opts.h @@ -46,7 +46,6 @@ enum arm_abi_type ARM_ABI_APCS, ARM_ABI_ATPCS, ARM_ABI_AAPCS, - ARM_ABI_IWMMXT, ARM_ABI_AAPCS_LINUX }; diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 254c731..ff7e765 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -190,8 +190,6 @@ extern void arm_output_multireg_pop (rtx *, bool, rtx, bool, bool); extern void arm_set_return_address (rtx, rtx); extern int arm_eliminable_register (rtx); extern const char *arm_output_shift(rtx *, int); -extern const char *arm_output_iwmmxt_shift_immediate (const char *, rtx *, bool); -extern const char *arm_output_iwmmxt_tinsr (rtx *); extern unsigned int arm_sync_loop_insns (rtx , rtx *); extern int arm_attr_length_push_multi(rtx, rtx); extern int arm_attr_length_pop_multi(rtx *, bool, bool); @@ -475,12 +473,6 @@ extern int arm_ld_sched; /* Nonzero if this chip is a StrongARM. */ extern int arm_tune_strongarm; -/* Nonzero if this chip supports Intel Wireless MMX technology. */ -extern int arm_arch_iwmmxt; - -/* Nonzero if this chip supports Intel Wireless MMX2 technology. */ -extern int arm_arch_iwmmxt2; - /* Nonzero if this chip is an XScale. */ extern int arm_arch_xscale; diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index db7767a..544de84 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -67,12 +67,6 @@ EnumValue Enum(processor_type) String(xscale) Value( TARGET_CPU_xscale) EnumValue -Enum(processor_type) String(iwmmxt) Value( TARGET_CPU_iwmmxt) - -EnumValue -Enum(processor_type) String(iwmmxt2) Value( TARGET_CPU_iwmmxt2) - -EnumValue Enum(processor_type) String(fa606te) Value( TARGET_CPU_fa606te) EnumValue diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index a04d1ee..20b5f93 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -25,31 +25,30 @@ fa526,fa626,arm7tdmi, arm710t,arm9,arm9tdmi, arm920t,arm10tdmi,arm9e, - arm10e,xscale,iwmmxt, - iwmmxt2,fa606te,fa626te, - fmp626,fa726te,arm926ejs, - arm1026ejs,arm1136js,arm1136jfs, - arm1176jzs,arm1176jzfs,mpcorenovfp, - mpcore,arm1156t2s,arm1156t2fs, - cortexm1,cortexm0,cortexm0plus, - cortexm1smallmultiply,cortexm0smallmultiply,cortexm0plussmallmultiply, - genericv7a,cortexa5,cortexa7, - cortexa8,cortexa9,cortexa12, - cortexa15,cortexa17,cortexr4, - cortexr4f,cortexr5,cortexr7, - cortexr8,cortexm7,cortexm4, - cortexm3,marvell_pj4,cortexa15cortexa7, - cortexa17cortexa7,cortexa32,cortexa35, - cortexa53,cortexa57,cortexa72, - cortexa73,exynosm1,xgene1, - cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35, - cortexa73cortexa53,cortexa55,cortexa75, - cortexa76,cortexa76ae,cortexa77, - cortexa78,cortexa78ae,cortexa78c, - cortexa710,cortexx1,cortexx1c, - neoversen1,cortexa75cortexa55,cortexa76cortexa55, - neoversev1,neoversen2,cortexm23, - cortexm33,cortexm35p,cortexm52, - cortexm55,starmc1,cortexm85, - cortexr52,cortexr52plus" + arm10e,xscale,fa606te, + fa626te,fmp626,fa726te, + arm926ejs,arm1026ejs,arm1136js, + arm1136jfs,arm1176jzs,arm1176jzfs, + mpcorenovfp,mpcore,arm1156t2s, + arm1156t2fs,cortexm1,cortexm0, + cortexm0plus,cortexm1smallmultiply,cortexm0smallmultiply, + cortexm0plussmallmultiply,genericv7a,cortexa5, + cortexa7,cortexa8,cortexa9, + cortexa12,cortexa15,cortexa17, + cortexr4,cortexr4f,cortexr5, + cortexr7,cortexr8,cortexm7, + cortexm4,cortexm3,marvell_pj4, + cortexa15cortexa7,cortexa17cortexa7,cortexa32, + cortexa35,cortexa53,cortexa57, + cortexa72,cortexa73,exynosm1, + xgene1,cortexa57cortexa53,cortexa72cortexa53, + cortexa73cortexa35,cortexa73cortexa53,cortexa55, + cortexa75,cortexa76,cortexa76ae, + cortexa77,cortexa78,cortexa78ae, + cortexa78c,cortexa710,cortexx1, + cortexx1c,neoversen1,cortexa75cortexa55, + cortexa76cortexa55,neoversev1,neoversen2, + cortexm23,cortexm33,cortexm35p, + cortexm52,cortexm55,starmc1, + cortexm85,cortexr52,cortexr52plus" (const (symbol_ref "((enum attr_tune) arm_tune)"))) diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index 670f487..bde06f3 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -948,12 +948,6 @@ int arm_ld_sched = 0; /* Nonzero if this chip is a StrongARM. */ int arm_tune_strongarm = 0; -/* Nonzero if this chip supports Intel Wireless MMX technology. */ -int arm_arch_iwmmxt = 0; - -/* Nonzero if this chip supports Intel Wireless MMX2 technology. */ -int arm_arch_iwmmxt2 = 0; - /* Nonzero if this chip is an XScale. */ int arm_arch_xscale = 0; @@ -2970,11 +2964,6 @@ arm_option_check_internal (struct gcc_options *opts) { int flags = opts->x_target_flags; - /* iWMMXt and NEON are incompatible. */ - if (TARGET_IWMMXT - && bitmap_bit_p (arm_active_target.isa, isa_bit_neon)) - error ("iWMMXt and NEON are incompatible"); - /* Make sure that the processor choice does not conflict with any of the other command line choices. */ if (TARGET_ARM_P (flags) @@ -2997,10 +2986,6 @@ arm_option_check_internal (struct gcc_options *opts) warning (0, "%<-g%> with %<-mno-apcs-frame%> may not give sensible " "debugging"); - /* iWMMXt unsupported under Thumb mode. */ - if (TARGET_THUMB_P (flags) && TARGET_IWMMXT) - error ("iWMMXt unsupported under Thumb mode"); - if (TARGET_HARD_TP && TARGET_THUMB1_P (flags)) error ("cannot use %<-mtp=cp15%> with 16-bit Thumb"); @@ -3928,8 +3913,6 @@ arm_option_reconfigure_globals (void) arm_arch_thumb1 = bitmap_bit_p (arm_active_target.isa, isa_bit_thumb); arm_arch_thumb2 = bitmap_bit_p (arm_active_target.isa, isa_bit_thumb2); arm_arch_xscale = bitmap_bit_p (arm_active_target.isa, isa_bit_xscale); - arm_arch_iwmmxt = bitmap_bit_p (arm_active_target.isa, isa_bit_iwmmxt); - arm_arch_iwmmxt2 = bitmap_bit_p (arm_active_target.isa, isa_bit_iwmmxt2); arm_arch_thumb_hwdiv = bitmap_bit_p (arm_active_target.isa, isa_bit_tdiv); arm_arch_arm_hwdiv = bitmap_bit_p (arm_active_target.isa, isa_bit_adiv); arm_arch_crc = bitmap_bit_p (arm_active_target.isa, isa_bit_crc32); @@ -3997,12 +3980,6 @@ arm_options_perform_arch_sanity_checks (void) if (arm_arch5t) target_flags &= ~MASK_INTERWORK; - if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN) - error ("iwmmxt requires an AAPCS compatible ABI for proper operation"); - - if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT) - error ("iwmmxt abi requires an iwmmxt capable cpu"); - /* BPABI targets use linker tricks to allow interworking on cores without thumb support. */ if (TARGET_INTERWORK @@ -4043,9 +4020,7 @@ arm_options_perform_arch_sanity_checks (void) if (TARGET_AAPCS_BASED) { - if (arm_abi == ARM_ABI_IWMMXT) - arm_pcs_default = ARM_PCS_AAPCS_IWMMXT; - else if (TARGET_HARD_FLOAT_ABI) + if (TARGET_HARD_FLOAT_ABI) { arm_pcs_default = ARM_PCS_AAPCS_VFP; if (!bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv2) @@ -4555,11 +4530,6 @@ use_return_insn (int iscond, rtx sibling) if (reg_needs_saving_p (regno)) return 0; - if (TARGET_REALLY_IWMMXT) - for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++) - if (reg_needs_saving_p (regno)) - return 0; - return 1; } @@ -6048,9 +6018,6 @@ arm_libcall_value_1 (machine_mode mode) { if (TARGET_AAPCS_BASED) return aapcs_libcall_value (mode); - else if (TARGET_IWMMXT_ABI - && arm_vector_mode_supported_p (mode)) - return gen_rtx_REG (mode, FIRST_IWMMXT_REGNUM); else return gen_rtx_REG (mode, ARG_REGISTER (1)); } @@ -6083,9 +6050,7 @@ arm_function_value_regno_p (const unsigned int regno) || (TARGET_32BIT && TARGET_AAPCS_BASED && TARGET_HARD_FLOAT - && regno == FIRST_VFP_REGNUM) - || (TARGET_IWMMXT_ABI - && regno == FIRST_IWMMXT_REGNUM)) + && regno == FIRST_VFP_REGNUM)) return true; return false; @@ -6102,8 +6067,6 @@ arm_apply_result_size (void) { if (TARGET_HARD_FLOAT_ABI) size += 32; - if (TARGET_IWMMXT_ABI) - size += 8; } return size; @@ -6265,7 +6228,6 @@ const struct pcs_attribute_arg #if 0 /* We could recognize these, but changes would be needed elsewhere * to implement them. */ - {"aapcs-iwmmxt", ARM_PCS_AAPCS_IWMMXT}, {"atpcs", ARM_PCS_ATPCS}, {"apcs", ARM_PCS_APCS}, #endif @@ -7195,26 +7157,12 @@ arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype, /* On the ARM, the offset starts at 0. */ pcum->nregs = 0; - pcum->iwmmxt_nregs = 0; pcum->can_split = true; /* Varargs vectors are treated the same as long long. named_count avoids having to change the way arm handles 'named' */ pcum->named_count = 0; pcum->nargs = 0; - - if (TARGET_REALLY_IWMMXT && fntype) - { - tree fn_arg; - - for (fn_arg = TYPE_ARG_TYPES (fntype); - fn_arg; - fn_arg = TREE_CHAIN (fn_arg)) - pcum->named_count += 1; - - if (! pcum->named_count) - pcum->named_count = INT_MAX; - } } /* Return 2 if double word alignment is required for argument passing, @@ -7308,22 +7256,6 @@ arm_function_arg (cumulative_args_t pcum_v, const function_arg_info &arg) return pcum->aapcs_reg; } - /* Varargs vectors are treated the same as long long. - named_count avoids having to change the way arm handles 'named' */ - if (TARGET_IWMMXT_ABI - && arm_vector_mode_supported_p (arg.mode) - && pcum->named_count > pcum->nargs + 1) - { - if (pcum->iwmmxt_nregs <= 9) - return gen_rtx_REG (arg.mode, - pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM); - else - { - pcum->can_split = false; - return NULL_RTX; - } - } - /* Put doubleword aligned quantities in even register pairs. */ if ((pcum->nregs & 1) && ARM_DOUBLEWORD_ALIGN) { @@ -7383,9 +7315,6 @@ arm_arg_partial_bytes (cumulative_args_t pcum_v, const function_arg_info &arg) return pcum->aapcs_partial; } - if (TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (arg.mode)) - return 0; - if (NUM_ARG_REGS > nregs && (NUM_ARG_REGS < nregs + ARM_NUM_REGS2 (arg.mode, arg.type)) && pcum->can_split) @@ -7422,12 +7351,7 @@ arm_function_arg_advance (cumulative_args_t pcum_v, else { pcum->nargs += 1; - if (arm_vector_mode_supported_p (arg.mode) - && pcum->named_count > pcum->nargs - && TARGET_IWMMXT_ABI) - pcum->iwmmxt_nregs += 1; - else - pcum->nregs += ARM_NUM_REGS2 (arg.mode, arg.type); + pcum->nregs += ARM_NUM_REGS2 (arg.mode, arg.type); } } @@ -8149,8 +8073,7 @@ require_pic_register (rtx pic_reg, bool compute_now) else arm_load_pic_register (0UL, pic_reg); - seq = get_insns (); - end_sequence (); + seq = end_sequence (); for (insn = seq; insn; insn = NEXT_INSN (insn)) if (INSN_P (insn)) @@ -8906,12 +8829,6 @@ arm_legitimate_index_p (machine_mode mode, rtx index, RTX_CODE outer, && INTVAL (index) > -1024 && (INTVAL (index) & 3) == 0); - if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode)) - return (code == CONST_INT - && INTVAL (index) < 1024 - && INTVAL (index) > -1024 - && (INTVAL (index) & 3) == 0); - if (GET_MODE_SIZE (mode) <= 4 && ! (arm_arch4 && (mode == HImode @@ -8991,17 +8908,6 @@ thumb2_legitimate_index_p (machine_mode mode, rtx index, int strict_p) && INTVAL (index) > -256 && (INTVAL (index) & 3) == 0); - if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode)) - { - /* For DImode assume values will usually live in core regs - and only allow LDRD addressing modes. */ - if (!TARGET_LDRD || mode != DImode) - return (code == CONST_INT - && INTVAL (index) < 1024 - && INTVAL (index) > -1024 - && (INTVAL (index) & 3) == 0); - } - /* For quad modes, we restrict the constant offset to be slightly less than what the instruction format permits. We do this because for quad mode moves, we will actually decompose them into two separate @@ -9372,10 +9278,7 @@ arm_call_tls_get_addr (rtx x, rtx reg, rtx *valuep, int reloc) LCT_PURE, /* LCT_CONST? */ Pmode, reg, Pmode); - rtx_insn *insns = get_insns (); - end_sequence (); - - return insns; + return end_sequence (); } static rtx @@ -12463,11 +12366,6 @@ arm_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, if ((IS_VFP_CLASS (from) && !IS_VFP_CLASS (to)) || (!IS_VFP_CLASS (from) && IS_VFP_CLASS (to))) return 15; - else if ((from == IWMMXT_REGS && to != IWMMXT_REGS) - || (from != IWMMXT_REGS && to == IWMMXT_REGS)) - return 4; - else if (from == IWMMXT_GR_REGS || to == IWMMXT_GR_REGS) - return 20; else return 2; } @@ -14993,8 +14891,6 @@ arm_gen_load_multiple_1 (int count, int *regs, rtx *mems, rtx basereg, if (!multiple_operation_profitable_p (false, count, 0)) { - rtx seq; - start_sequence (); for (i = 0; i < count; i++) @@ -15003,10 +14899,7 @@ arm_gen_load_multiple_1 (int count, int *regs, rtx *mems, rtx basereg, if (wback_offset != 0) emit_move_insn (basereg, plus_constant (Pmode, basereg, wback_offset)); - seq = get_insns (); - end_sequence (); - - return seq; + return end_sequence (); } result = gen_rtx_PARALLEL (VOIDmode, @@ -15044,8 +14937,6 @@ arm_gen_store_multiple_1 (int count, int *regs, rtx *mems, rtx basereg, if (!multiple_operation_profitable_p (false, count, 0)) { - rtx seq; - start_sequence (); for (i = 0; i < count; i++) @@ -15054,10 +14945,7 @@ arm_gen_store_multiple_1 (int count, int *regs, rtx *mems, rtx basereg, if (wback_offset != 0) emit_move_insn (basereg, plus_constant (Pmode, basereg, wback_offset)); - seq = get_insns (); - end_sequence (); - - return seq; + return end_sequence (); } result = gen_rtx_PARALLEL (VOIDmode, @@ -16211,14 +16099,16 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y) case UNGT: case UNGE: case UNEQ: - case LTGT: return CCFPmode; case LT: case LE: case GT: case GE: - return CCFPEmode; + case LTGT: + return (flag_finite_math_only + ? CCFPmode + : CCFPEmode); default: gcc_unreachable (); @@ -17581,8 +17471,7 @@ struct minipool_node rtx value; /* The mode of value. */ machine_mode mode; - /* The size of the value. With iWMMXt enabled - sizes > 4 also imply an alignment of 8-bytes. */ + /* The size of the value. */ int fix_size; }; @@ -18942,8 +18831,7 @@ cmse_clear_registers (sbitmap to_clear_bitmap, uint32_t *padding_bits_to_clear, XVECEXP (par, 0, k++) = set; emit_use (reg); } - use_seq = get_insns (); - end_sequence (); + use_seq = end_sequence (); emit_insn_after (use_seq, emit_insn (par)); } @@ -18988,8 +18876,7 @@ cmse_clear_registers (sbitmap to_clear_bitmap, uint32_t *padding_bits_to_clear, rtx clobber = gen_rtx_CLOBBER (VOIDmode, ccreg); XVECEXP (par, 0, j) = clobber; - use_seq = get_insns (); - end_sequence (); + use_seq = end_sequence (); emit_insn_after (use_seq, emit_insn (par)); } @@ -19230,8 +19117,7 @@ cmse_nonsecure_call_inline_register_clear (void) cmse_clear_registers (to_clear_bitmap, padding_bits_to_clear, NUM_ARG_REGS, ip_reg, clearing_reg); - seq = get_insns (); - end_sequence (); + seq = end_sequence (); emit_insn_before (seq, insn); /* The AAPCS requires the callee to widen integral types narrower @@ -20245,9 +20131,7 @@ output_move_double (rtx *operands, bool emit, int *count) } else { - /* Use a single insn if we can. - FIXME: IWMMXT allows offsets larger than ldrd can - handle, fix these up with a pair of ldr. */ + /* Use a single insn if we can. */ if (can_ldrd && (TARGET_THUMB2 || !CONST_INT_P (otherops[2]) @@ -20272,9 +20156,7 @@ output_move_double (rtx *operands, bool emit, int *count) } else { - /* Use a single insn if we can. - FIXME: IWMMXT allows offsets larger than ldrd can handle, - fix these up with a pair of ldr. */ + /* Use a single insn if we can. */ if (can_ldrd && (TARGET_THUMB2 || !CONST_INT_P (otherops[2]) @@ -20512,8 +20394,6 @@ output_move_double (rtx *operands, bool emit, int *count) otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0); otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1); - /* IWMMXT allows offsets larger than strd can handle, - fix these up with a pair of str. */ if (!TARGET_THUMB2 && CONST_INT_P (otherops[2]) && (INTVAL(otherops[2]) <= -256 @@ -21450,34 +21330,6 @@ arm_compute_save_core_reg_mask (void) if (cfun->machine->lr_save_eliminated) save_reg_mask &= ~ (1 << LR_REGNUM); - if (TARGET_REALLY_IWMMXT - && ((bit_count (save_reg_mask) - + ARM_NUM_INTS (crtl->args.pretend_args_size + - arm_compute_static_chain_stack_bytes()) - ) % 2) != 0) - { - /* The total number of registers that are going to be pushed - onto the stack is odd. We need to ensure that the stack - is 64-bit aligned before we start to save iWMMXt registers, - and also before we start to create locals. (A local variable - might be a double or long long which we will load/store using - an iWMMXt instruction). Therefore we need to push another - ARM register, so that the stack will be 64-bit aligned. We - try to avoid using the arg registers (r0 -r3) as they might be - used to pass values in a tail call. */ - for (reg = 4; reg <= 12; reg++) - if ((save_reg_mask & (1 << reg)) == 0) - break; - - if (reg <= 12) - save_reg_mask |= (1 << reg); - else - { - cfun->machine->sibcall_blocked = 1; - save_reg_mask |= (1 << 3); - } - } - /* We may need to push an additional register for use initializing the PIC base register. */ if (TARGET_THUMB2 && IS_NESTED (func_type) && flag_pic @@ -21685,19 +21537,17 @@ output_return_instruction (rtx operand, bool really_return, bool reverse, if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM)) { - /* There are three possible reasons for the IP register - being saved. 1) a stack frame was created, in which case - IP contains the old stack pointer, or 2) an ISR routine - corrupted it, or 3) it was saved to align the stack on - iWMMXt. In case 1, restore IP into SP, otherwise just - restore IP. */ + /* There are two possible reasons for the IP register being saved. + 1) a stack frame was created, in which case IP contains the old + stack pointer, or 2) an ISR routine corrupted it. In case 1, + restore IP into SP, otherwise just restore IP. */ if (frame_pointer_needed) { live_regs_mask &= ~ (1 << IP_REGNUM); live_regs_mask |= (1 << SP_REGNUM); } else - gcc_assert (IS_INTERRUPT (func_type) || TARGET_REALLY_IWMMXT); + gcc_assert (IS_INTERRUPT (func_type)); } /* On some ARM architectures it is faster to use LDR rather than @@ -23149,8 +22999,6 @@ arm_compute_frame_layout (void) if (TARGET_32BIT) { - unsigned int regno; - offsets->saved_regs_mask = arm_compute_save_core_reg_mask (); core_saved = bit_count (offsets->saved_regs_mask) * 4; saved = core_saved; @@ -23159,16 +23007,6 @@ arm_compute_frame_layout (void) preserve that condition at any subroutine call. We also require the soft frame pointer to be doubleword aligned. */ - if (TARGET_REALLY_IWMMXT) - { - /* Check for the call-saved iWMMXt registers. */ - for (regno = FIRST_IWMMXT_REGNUM; - regno <= LAST_IWMMXT_REGNUM; - regno++) - if (reg_needs_saving_p (regno)) - saved += 8; - } - func_type = arm_current_func_type (); /* Space for saved VFP registers. */ if (! IS_VOLATILE (func_type) @@ -23384,18 +23222,6 @@ arm_save_coproc_regs(void) int saved_size = 0; unsigned reg; unsigned start_reg; - rtx insn; - - if (TARGET_REALLY_IWMMXT) - for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--) - if (reg_needs_saving_p (reg)) - { - insn = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx); - insn = gen_rtx_MEM (V2SImode, insn); - insn = emit_set_insn (insn, gen_rtx_REG (V2SImode, reg)); - RTX_FRAME_RELATED_P (insn) = 1; - saved_size += 8; - } if (TARGET_VFP_BASE) { @@ -24554,42 +24380,9 @@ arm_print_operand (FILE *stream, rtx x, int code) return; case 'U': - if (!REG_P (x) - || REGNO (x) < FIRST_IWMMXT_GR_REGNUM - || REGNO (x) > LAST_IWMMXT_GR_REGNUM) - /* Bad value for wCG register number. */ - { - output_operand_lossage ("invalid operand for code '%c'", code); - return; - } - - else - fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM); - return; - - /* Print an iWMMXt control register name. */ case 'w': - if (!CONST_INT_P (x) - || INTVAL (x) < 0 - || INTVAL (x) >= 16) - /* Bad value for wC register number. */ - { - output_operand_lossage ("invalid operand for code '%c'", code); - return; - } - - else - { - static const char * wc_reg_names [16] = - { - "wCID", "wCon", "wCSSF", "wCASF", - "wC4", "wC5", "wC6", "wC7", - "wCGR0", "wCGR1", "wCGR2", "wCGR3", - "wC12", "wC13", "wC14", "wC15" - }; - - fputs (wc_reg_names [INTVAL (x)], stream); - } + /* Former iWMMXT support, removed after GCC-15. */ + output_operand_lossage ("obsolete iWMMXT format code '%c'", code); return; /* Print the high single-precision register of a VFP double-precision @@ -25924,15 +25717,6 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode) return false; } - if (TARGET_REALLY_IWMMXT) - { - if (IS_IWMMXT_GR_REGNUM (regno)) - return mode == SImode; - - if (IS_IWMMXT_REGNUM (regno)) - return VALID_IWMMXT_REG_MODE (mode); - } - /* We allow almost any value to be stored in the general registers. Restrict doubleword quantities to even register pairs in ARM state so that we can use ldrd. The same restriction applies for MVE @@ -26038,12 +25822,6 @@ arm_regno_class (int regno) return VFP_HI_REGS; } - if (IS_IWMMXT_REGNUM (regno)) - return IWMMXT_REGS; - - if (IS_IWMMXT_GR_REGNUM (regno)) - return IWMMXT_GR_REGS; - return NO_REGS; } @@ -27961,27 +27739,6 @@ arm_expand_epilogue_apcs_frame (bool really_return) gen_rtx_REG (SImode, IP_REGNUM)); } - if (TARGET_IWMMXT) - { - /* The frame pointer is guaranteed to be non-double-word aligned, as - it is set to double-word-aligned old_stack_pointer - 4. */ - rtx_insn *insn; - int lrm_count = (num_regs % 2) ? (num_regs + 2) : (num_regs + 1); - - for (i = LAST_IWMMXT_REGNUM; i >= FIRST_IWMMXT_REGNUM; i--) - if (reg_needs_saving_p (i)) - { - rtx addr = gen_frame_mem (V2SImode, - plus_constant (Pmode, hard_frame_pointer_rtx, - - lrm_count * 4)); - insn = emit_insn (gen_movsi (gen_rtx_REG (V2SImode, i), addr)); - REG_NOTES (insn) = alloc_reg_note (REG_CFA_RESTORE, - gen_rtx_REG (V2SImode, i), - NULL_RTX); - lrm_count += 2; - } - } - /* saved_regs_mask should contain IP which contains old stack pointer at the time of activation creation. Since SP and IP are adjacent registers, we can restore the value directly into SP. */ @@ -28194,23 +27951,6 @@ arm_expand_epilogue (bool really_return) stack_pointer_rtx); } - if (TARGET_IWMMXT) - for (i = FIRST_IWMMXT_REGNUM; i <= LAST_IWMMXT_REGNUM; i++) - if (reg_needs_saving_p (i)) - { - rtx_insn *insn; - rtx addr = gen_rtx_MEM (V2SImode, - gen_rtx_POST_INC (SImode, - stack_pointer_rtx)); - set_mem_alias_set (addr, get_frame_alias_set ()); - insn = emit_insn (gen_movsi (gen_rtx_REG (V2SImode, i), addr)); - REG_NOTES (insn) = alloc_reg_note (REG_CFA_RESTORE, - gen_rtx_REG (V2SImode, i), - NULL_RTX); - arm_add_cfa_adjust_cfa_note (insn, UNITS_PER_WORD, - stack_pointer_rtx, stack_pointer_rtx); - } - if (saved_regs_mask) { rtx insn; @@ -29851,7 +29591,7 @@ arm_vector_mode_supported_p (machine_mode mode) || mode == V8BFmode)) return true; - if ((TARGET_NEON || TARGET_IWMMXT) + if (TARGET_NEON && ((mode == V2SImode) || (mode == V4HImode) || (mode == V8QImode))) @@ -29943,19 +29683,6 @@ arm_preferred_simd_mode (scalar_mode mode) default:; } - if (TARGET_REALLY_IWMMXT) - switch (mode) - { - case E_SImode: - return V2SImode; - case E_HImode: - return V4HImode; - case E_QImode: - return V8QImode; - - default:; - } - if (TARGET_HAVE_MVE) switch (mode) { @@ -30037,12 +29764,6 @@ arm_debugger_regno (unsigned int regno) return 256 + (regno - FIRST_VFP_REGNUM) / 2; } - if (IS_IWMMXT_GR_REGNUM (regno)) - return 104 + regno - FIRST_IWMMXT_GR_REGNUM; - - if (IS_IWMMXT_REGNUM (regno)) - return 112 + regno - FIRST_IWMMXT_REGNUM; - if (IS_PAC_REGNUM (regno)) return DWARF_PAC_REGNUM; @@ -30629,95 +30350,6 @@ arm_output_shift(rtx * operands, int set_flags) return ""; } -/* Output assembly for a WMMX immediate shift instruction. */ -const char * -arm_output_iwmmxt_shift_immediate (const char *insn_name, rtx *operands, bool wror_or_wsra) -{ - int shift = INTVAL (operands[2]); - char templ[50]; - machine_mode opmode = GET_MODE (operands[0]); - - gcc_assert (shift >= 0); - - /* If the shift value in the register versions is > 63 (for D qualifier), - 31 (for W qualifier) or 15 (for H qualifier). */ - if (((opmode == V4HImode) && (shift > 15)) - || ((opmode == V2SImode) && (shift > 31)) - || ((opmode == DImode) && (shift > 63))) - { - if (wror_or_wsra) - { - sprintf (templ, "%s\t%%0, %%1, #%d", insn_name, 32); - output_asm_insn (templ, operands); - if (opmode == DImode) - { - sprintf (templ, "%s\t%%0, %%0, #%d", insn_name, 32); - output_asm_insn (templ, operands); - } - } - else - { - /* The destination register will contain all zeros. */ - sprintf (templ, "wzero\t%%0"); - output_asm_insn (templ, operands); - } - return ""; - } - - if ((opmode == DImode) && (shift > 32)) - { - sprintf (templ, "%s\t%%0, %%1, #%d", insn_name, 32); - output_asm_insn (templ, operands); - sprintf (templ, "%s\t%%0, %%0, #%d", insn_name, shift - 32); - output_asm_insn (templ, operands); - } - else - { - sprintf (templ, "%s\t%%0, %%1, #%d", insn_name, shift); - output_asm_insn (templ, operands); - } - return ""; -} - -/* Output assembly for a WMMX tinsr instruction. */ -const char * -arm_output_iwmmxt_tinsr (rtx *operands) -{ - int mask = INTVAL (operands[3]); - int i; - char templ[50]; - int units = mode_nunits[GET_MODE (operands[0])]; - gcc_assert ((mask & (mask - 1)) == 0); - for (i = 0; i < units; ++i) - { - if ((mask & 0x01) == 1) - { - break; - } - mask >>= 1; - } - gcc_assert (i < units); - { - switch (GET_MODE (operands[0])) - { - case E_V8QImode: - sprintf (templ, "tinsrb%%?\t%%0, %%2, #%d", i); - break; - case E_V4HImode: - sprintf (templ, "tinsrh%%?\t%%0, %%2, #%d", i); - break; - case E_V2SImode: - sprintf (templ, "tinsrw%%?\t%%0, %%2, #%d", i); - break; - default: - gcc_unreachable (); - break; - } - output_asm_insn (templ, operands); - } - return ""; -} - /* Output an arm casesi dispatch sequence. Used by arm_casesi_internal insn. Responsible for the handling of switch statements in arm. */ const char * @@ -31090,26 +30722,6 @@ arm_conditional_register_usage (void) fixed_regs[VPR_REGNUM] = 0; } - if (TARGET_REALLY_IWMMXT && !TARGET_GENERAL_REGS_ONLY) - { - regno = FIRST_IWMMXT_GR_REGNUM; - /* The 2002/10/09 revision of the XScale ABI has wCG0 - and wCG1 as call-preserved registers. The 2002/11/21 - revision changed this so that all wCG registers are - scratch registers. */ - for (regno = FIRST_IWMMXT_GR_REGNUM; - regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) - fixed_regs[regno] = 0; - /* The XScale ABI has wR0 - wR9 as scratch registers, - the rest as call-preserved registers. */ - for (regno = FIRST_IWMMXT_REGNUM; - regno <= LAST_IWMMXT_REGNUM; ++ regno) - { - fixed_regs[regno] = 0; - call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; - } - } - if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) { fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; @@ -35959,8 +35571,7 @@ arm_attempt_dlstp_transform (rtx label) emit_insn (PATTERN (insn)); } } - seq = get_insns (); - end_sequence (); + seq = end_sequence (); /* Re-write the entire BB contents with the transformed sequence. */ diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 8472b75..2e9d678 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -137,13 +137,6 @@ emission of floating point pcs attributes. */ #define TARGET_MAYBE_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) /* Use hardware floating point calling convention. */ #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) -#define TARGET_IWMMXT (arm_arch_iwmmxt) -#define TARGET_IWMMXT2 (arm_arch_iwmmxt2) -#define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT \ - && !TARGET_GENERAL_REGS_ONLY) -#define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT \ - && !TARGET_GENERAL_REGS_ONLY) -#define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) #define TARGET_ARM (! TARGET_THUMB) #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ #define TARGET_BACKTRACE (crtl->is_leaf \ @@ -526,12 +519,6 @@ extern int arm_ld_sched; /* Nonzero if this chip is a StrongARM. */ extern int arm_tune_strongarm; -/* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ -extern int arm_arch_iwmmxt; - -/* Nonzero if this chip supports Intel Wireless MMX2 technology. */ -extern int arm_arch_iwmmxt2; - /* Nonzero if this chip is an XScale. */ extern int arm_arch_xscale; @@ -855,10 +842,6 @@ extern const int arm_arch_cde_coproc_bits[]; 1,1,1,1,1,1,1,1, \ 1,1,1,1,1,1,1,1, \ 1,1,1,1,1,1,1,1, \ - /* IWMMXT regs. */ \ - 1,1,1,1,1,1,1,1, \ - 1,1,1,1,1,1,1,1, \ - 1,1,1,1, \ /* Specials. */ \ 1,1,1,1,1,1,1,1 \ } @@ -885,10 +868,6 @@ extern const int arm_arch_cde_coproc_bits[]; 1,1,1,1,1,1,1,1, \ 1,1,1,1,1,1,1,1, \ 1,1,1,1,1,1,1,1, \ - /* IWMMXT regs. */ \ - 1,1,1,1,1,1,1,1, \ - 1,1,1,1,1,1,1,1, \ - 1,1,1,1, \ /* Specials. */ \ 1,1,1,1,1,1,1,1 \ } @@ -1010,23 +989,11 @@ extern const int arm_arch_cde_coproc_bits[]; /* Register to use for pushing function arguments. */ #define STACK_POINTER_REGNUM SP_REGNUM -#define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1) -#define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15) - -/* Need to sync with WCGR in iwmmxt.md. */ -#define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1) -#define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3) - -#define IS_IWMMXT_REGNUM(REGNUM) \ - (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) -#define IS_IWMMXT_GR_REGNUM(REGNUM) \ - (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) - /* Base register for access to local variables of the function. */ -#define FRAME_POINTER_REGNUM 102 +#define FRAME_POINTER_REGNUM (CC_REGNUM + 2) /* Base register for access to arguments of the function. */ -#define ARG_POINTER_REGNUM 103 +#define ARG_POINTER_REGNUM (FRAME_POINTER_REGNUM + 1) #define FIRST_VFP_REGNUM 16 #define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15) @@ -1067,9 +1034,8 @@ extern const int arm_arch_cde_coproc_bits[]; /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP + 1 APSRQ + 1 APSRGE + 1 VPR + 1 Pseudo register to save PAC. */ -/* Intel Wireless MMX Technology registers add 16 + 4 more. */ /* VFP (VFP3) adds 32 (64) + 1 VFPCC. */ -#define FIRST_PSEUDO_REGISTER 108 +#define FIRST_PSEUDO_REGISTER 88 #define DWARF_PAC_REGNUM 143 @@ -1086,9 +1052,6 @@ extern const int arm_arch_cde_coproc_bits[]; #define SUBTARGET_FRAME_POINTER_REQUIRED 0 #endif -#define VALID_IWMMXT_REG_MODE(MODE) \ - (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) - /* Modes valid for Neon D registers. */ #define VALID_NEON_DREG_MODE(MODE) \ ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ @@ -1168,9 +1131,9 @@ extern const int arm_arch_cde_coproc_bits[]; /* The conditions under which vector modes are supported for general arithmetic by any vector extension. */ -#define ARM_HAVE_V8QI_ARITH (ARM_HAVE_NEON_V8QI_ARITH || TARGET_REALLY_IWMMXT) -#define ARM_HAVE_V4HI_ARITH (ARM_HAVE_NEON_V4HI_ARITH || TARGET_REALLY_IWMMXT) -#define ARM_HAVE_V2SI_ARITH (ARM_HAVE_NEON_V2SI_ARITH || TARGET_REALLY_IWMMXT) +#define ARM_HAVE_V8QI_ARITH (ARM_HAVE_NEON_V8QI_ARITH) +#define ARM_HAVE_V4HI_ARITH (ARM_HAVE_NEON_V4HI_ARITH) +#define ARM_HAVE_V2SI_ARITH (ARM_HAVE_NEON_V2SI_ARITH) #define ARM_HAVE_V16QI_ARITH (ARM_HAVE_NEON_V16QI_ARITH || TARGET_HAVE_MVE) #define ARM_HAVE_V8HI_ARITH (ARM_HAVE_NEON_V8HI_ARITH || TARGET_HAVE_MVE) @@ -1204,9 +1167,9 @@ extern const int arm_arch_cde_coproc_bits[]; /* The conditions under which vector modes are supported by load/store instructions by any vector extension. */ -#define ARM_HAVE_V8QI_LDST (ARM_HAVE_NEON_V8QI_LDST || TARGET_REALLY_IWMMXT) -#define ARM_HAVE_V4HI_LDST (ARM_HAVE_NEON_V4HI_LDST || TARGET_REALLY_IWMMXT) -#define ARM_HAVE_V2SI_LDST (ARM_HAVE_NEON_V2SI_LDST || TARGET_REALLY_IWMMXT) +#define ARM_HAVE_V8QI_LDST (ARM_HAVE_NEON_V8QI_LDST) +#define ARM_HAVE_V4HI_LDST (ARM_HAVE_NEON_V4HI_LDST) +#define ARM_HAVE_V2SI_LDST (ARM_HAVE_NEON_V2SI_LDST) #define ARM_HAVE_V16QI_LDST (ARM_HAVE_NEON_V16QI_LDST || TARGET_HAVE_MVE) #define ARM_HAVE_V8HI_LDST (ARM_HAVE_NEON_V8HI_LDST || TARGET_HAVE_MVE) @@ -1238,8 +1201,6 @@ extern int arm_regs_in_sequence[]; function. */ #define VREG(X) (FIRST_VFP_REGNUM + (X)) -#define WREG(X) (FIRST_IWMMXT_REGNUM + (X)) -#define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X)) #define REG_ALLOC_ORDER \ { \ @@ -1265,12 +1226,6 @@ extern int arm_regs_in_sequence[]; VREG(20), VREG(21), VREG(22), VREG(23), \ VREG(24), VREG(25), VREG(26), VREG(27), \ VREG(28), VREG(29), VREG(30), VREG(31), \ - /* IWMMX registers. */ \ - WREG(0), WREG(1), WREG(2), WREG(3), \ - WREG(4), WREG(5), WREG(6), WREG(7), \ - WREG(8), WREG(9), WREG(10), WREG(11), \ - WREG(12), WREG(13), WREG(14), WREG(15), \ - WGREG(0), WGREG(1), WGREG(2), WGREG(3), \ /* Registers not for general use. */ \ CC_REGNUM, VFPCC_REGNUM, \ FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \ @@ -1315,8 +1270,6 @@ enum reg_class VFP_LO_REGS, VFP_HI_REGS, VFP_REGS, - IWMMXT_REGS, - IWMMXT_GR_REGS, CC_REG, VFPCC_REG, SFP_REG, @@ -1346,8 +1299,6 @@ enum reg_class "VFP_LO_REGS", \ "VFP_HI_REGS", \ "VFP_REGS", \ - "IWMMXT_REGS", \ - "IWMMXT_GR_REGS", \ "CC_REG", \ "VFPCC_REG", \ "SFP_REG", \ @@ -1363,29 +1314,27 @@ enum reg_class of length N_REG_CLASSES. */ #define REG_CLASS_CONTENTS \ { \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ - { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ - { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ - { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ - { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ - { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ - { 0x00005555, 0x00000000, 0x00000000, 0x00000000 }, /* EVEN_REGS. */ \ - { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ - { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ - { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \ - { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \ - { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \ - { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \ - { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000400 }, /* VPR_REG. */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000800 }, /* PAC_REG. */ \ - { 0x00005FFF, 0x00000000, 0x00000000, 0x00000400 }, /* GENERAL_AND_VPR_REGS. */ \ - { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000040F } /* ALL_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ + { 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */ \ + { 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ + { 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ + { 0x00005F00, 0x00000000, 0x00000000 }, /* HI_REGS */ \ + { 0x0000100F, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ + { 0x00005555, 0x00000000, 0x00000000 }, /* EVEN_REGS. */ \ + { 0x00005FFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ + { 0x00007FFF, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ + { 0xFFFF0000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \ + { 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_LO_REGS */ \ + { 0x00000000, 0xFFFF0000, 0x0000FFFF }, /* VFP_HI_REGS */ \ + { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF }, /* VFP_REGS */ \ + { 0x00000000, 0x00000000, 0x00010000 }, /* CC_REG */ \ + { 0x00000000, 0x00000000, 0x00020000 }, /* VFPCC_REG */ \ + { 0x00000000, 0x00000000, 0x00040000 }, /* SFP_REG */ \ + { 0x00000000, 0x00000000, 0x00080000 }, /* AFP_REG */ \ + { 0x00000000, 0x00000000, 0x00400000 }, /* VPR_REG. */ \ + { 0x00000000, 0x00000000, 0x00800000 }, /* PAC_REG. */ \ + { 0x00005FFF, 0x00000000, 0x00400000 }, /* GENERAL_AND_VPR_REGS. */ \ + { 0xFFFF7FFF, 0xFFFFFFFF, 0x0040FFFF } /* ALL_REGS. */ \ } #define FP_SYSREGS \ @@ -1460,39 +1409,34 @@ extern const char *fp_sysreg_names[NB_FP_SYSREGS]; /* Return the register class of a scratch register needed to copy IN into or out of a register in CLASS in MODE. If it can be done directly, NO_REGS is returned. */ -#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ - /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ - ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ - ? coproc_secondary_reload_class (MODE, X, FALSE) \ - : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ - ? coproc_secondary_reload_class (MODE, X, TRUE) \ - : TARGET_32BIT \ - ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ - ? GENERAL_REGS : NO_REGS) \ - : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) +#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ + /* Restrict which direct reloads are allowed for VFP regs. */ \ + ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ + ? coproc_secondary_reload_class (MODE, X, FALSE) \ + : (TARGET_32BIT \ + ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ + ? GENERAL_REGS \ + : NO_REGS) \ + : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))) /* If we need to load shorts byte-at-a-time, then we need a scratch. */ -#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ - /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ - ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ - ? coproc_secondary_reload_class (MODE, X, FALSE) : \ - (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \ - coproc_secondary_reload_class (MODE, X, TRUE) : \ - (TARGET_32BIT ? \ - (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ - && CONSTANT_P (X)) \ - ? GENERAL_REGS : \ - (((MODE) == HImode && ! arm_arch4 \ - && (MEM_P (X) \ - || ((REG_P (X) || GET_CODE (X) == SUBREG) \ - && true_regnum (X) == -1))) \ - ? GENERAL_REGS : NO_REGS) \ - : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) +#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ + /* Restrict which direct reloads are allowed for VFP regs. */ \ + ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ + ? coproc_secondary_reload_class (MODE, X, FALSE) \ + : (TARGET_32BIT \ + ? (((MODE) == HImode \ + && ! arm_arch4 \ + && (MEM_P (X) \ + || ((REG_P (X) || GET_CODE (X) == SUBREG) \ + && true_regnum (X) == -1))) \ + ? GENERAL_REGS \ + : NO_REGS) \ + : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) /* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS. - ARM regs are UNITS_PER_WORD bits. - FIXME: Is this true for iWMMX? */ + ARM regs are UNITS_PER_WORD bits. */ #define CLASS_MAX_NREGS(CLASS, MODE) \ (CLASS == VPR_REG) \ ? CEIL (GET_MODE_SIZE (MODE), 2) \ @@ -1672,7 +1616,6 @@ enum arm_pcs { ARM_PCS_AAPCS, /* Base standard AAPCS. */ ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */ - ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */ /* This must be the last AAPCS variant. */ ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */ ARM_PCS_ATPCS, /* ATPCS. */ @@ -1690,8 +1633,6 @@ typedef struct { /* This is the number of registers of arguments scanned so far. */ int nregs; - /* This is the number of iWMMXt register arguments scanned so far. */ - int iwmmxt_nregs; int named_count; int nargs; /* Which procedure call variant to use for this call. */ @@ -1739,9 +1680,7 @@ typedef struct #define FUNCTION_ARG_REGNO_P(REGNO) \ (IN_RANGE ((REGNO), 0, 3) \ || (TARGET_AAPCS_BASED && TARGET_HARD_FLOAT \ - && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \ - || (TARGET_IWMMXT_ABI \ - && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) + && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15))) /* If your target environment doesn't prefix user functions with an @@ -2257,7 +2196,11 @@ extern int making_const_table; #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) -#define REVERSIBLE_CC_MODE(MODE) 1 +/* Floating-point modes cannot be reversed unless we don't care about + NaNs. */ +#define REVERSIBLE_CC_MODE(MODE) \ + (flag_finite_math_only \ + || !((MODE) == CCFPmode || (MODE) == CCFPEmode)) #define REVERSE_CONDITION(CODE,MODE) \ (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 597ef67..5e5e112 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -37,12 +37,12 @@ (LR_REGNUM 14) ; Return address register (PC_REGNUM 15) ; Program counter (LAST_ARM_REGNUM 15) ; - (CC_REGNUM 100) ; Condition code pseudo register - (VFPCC_REGNUM 101) ; VFP Condition code pseudo register - (APSRQ_REGNUM 104) ; Q bit pseudo register - (APSRGE_REGNUM 105) ; GE bits pseudo register - (VPR_REGNUM 106) ; Vector Predication Register - MVE register. - (RA_AUTH_CODE 107) ; Pseudo register to save PAC. + (CC_REGNUM 80) ; Condition code pseudo register + (VFPCC_REGNUM 81) ; VFP Condition code pseudo register + (APSRQ_REGNUM 84) ; Q bit pseudo register + (APSRGE_REGNUM 85) ; GE bits pseudo register + (VPR_REGNUM 86) ; Vector Predication Register - MVE register. + (RA_AUTH_CODE 87) ; Pseudo register to save PAC. ] ) ;; 3rd operand to select_dominance_cc_mode @@ -149,7 +149,7 @@ ; This attribute is used to compute attribute "enabled", ; use type "any" to enable an alternative in all cases. (define_attr "arch" "any, a, t, 32, t1, t2, v6,nov6, v6t2, \ - v8mb, fix_vlldm, iwmmxt, iwmmxt2, armv6_or_vfpv3, \ + v8mb, fix_vlldm, armv6_or_vfpv3, \ neon, mve" (const_string "any")) @@ -197,10 +197,6 @@ (match_test "fix_vlldm")) (const_string "yes") - (and (eq_attr "arch" "iwmmxt2") - (match_test "TARGET_REALLY_IWMMXT2")) - (const_string "yes") - (and (eq_attr "arch" "armv6_or_vfpv3") (match_test "arm_arch6 || TARGET_VFP3")) (const_string "yes") @@ -362,18 +358,7 @@ alus_ext, alus_imm, alus_sreg,\ alus_shift_imm, alus_shift_reg, bfm, csel, rev, logic_imm, logic_reg,\ logic_shift_imm, logic_shift_reg, logics_imm, logics_reg,\ - logics_shift_imm, logics_shift_reg, extend, shift_imm, float, fcsel,\ - wmmx_wor, wmmx_wxor, wmmx_wand, wmmx_wandn, wmmx_wmov, wmmx_tmcrr,\ - wmmx_tmrrc, wmmx_wldr, wmmx_wstr, wmmx_tmcr, wmmx_tmrc, wmmx_wadd,\ - wmmx_wsub, wmmx_wmul, wmmx_wmac, wmmx_wavg2, wmmx_tinsr, wmmx_textrm,\ - wmmx_wshufh, wmmx_wcmpeq, wmmx_wcmpgt, wmmx_wmax, wmmx_wmin, wmmx_wpack,\ - wmmx_wunpckih, wmmx_wunpckil, wmmx_wunpckeh, wmmx_wunpckel, wmmx_wror,\ - wmmx_wsra, wmmx_wsrl, wmmx_wsll, wmmx_wmadd, wmmx_tmia, wmmx_tmiaph,\ - wmmx_tmiaxy, wmmx_tbcst, wmmx_tmovmsk, wmmx_wacc, wmmx_waligni,\ - wmmx_walignr, wmmx_tandc, wmmx_textrc, wmmx_torc, wmmx_torvsc, wmmx_wsad,\ - wmmx_wabs, wmmx_wabsdiff, wmmx_waddsubhx, wmmx_wsubaddhx, wmmx_wavg4,\ - wmmx_wmulw, wmmx_wqmulm, wmmx_wqmulwm, wmmx_waddbhus, wmmx_wqmiaxy,\ - wmmx_wmiaxy, wmmx_wmiawxy, wmmx_wmerge") + logics_shift_imm, logics_shift_reg, extend, shift_imm, float, fcsel") (const_string "single") (const_string "multi"))) @@ -435,7 +420,6 @@ (const_string "yes") (const_string "no")))) -(include "marvell-f-iwmmxt.md") (include "arm-generic.md") (include "arm926ejs.md") (include "arm1020e.md") @@ -2893,14 +2877,12 @@ ;; Split DImode and, ior, xor operations. Simply perform the logical ;; operation on the upper and lower halves of the registers. ;; This is needed for atomic operations in arm_split_atomic_op. -;; Avoid splitting IWMMXT instructions. (define_split [(set (match_operand:DI 0 "s_register_operand" "") (match_operator:DI 6 "logical_binary_operator" [(match_operand:DI 1 "s_register_operand" "") (match_operand:DI 2 "s_register_operand" "")]))] - "TARGET_32BIT && reload_completed - && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))" + "TARGET_32BIT && reload_completed" [(set (match_dup 0) (match_op_dup:SI 6 [(match_dup 1) (match_dup 2)])) (set (match_dup 3) (match_op_dup:SI 6 [(match_dup 4) (match_dup 5)]))] " @@ -6345,7 +6327,6 @@ "TARGET_32BIT && !(TARGET_HARD_FLOAT) && !(TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT) - && !TARGET_IWMMXT && ( register_operand (operands[0], DImode) || register_operand (operands[1], DImode))" "* @@ -6554,7 +6535,7 @@ (define_insn "*arm_movsi_insn" [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m") (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,rk"))] - "TARGET_ARM && !TARGET_IWMMXT && !TARGET_HARD_FLOAT + "TARGET_ARM && !TARGET_HARD_FLOAT && ( register_operand (operands[0], SImode) || register_operand (operands[1], SImode))" "@ @@ -13123,10 +13104,8 @@ [(set_attr "conds" "unconditional") (set_attr "type" "nop")]) -;; Vector bits common to IWMMXT, Neon and MVE +;; Vector bits common to Neon and MVE (include "vec-common.md") -;; Load the Intel Wireless Multimedia Extension patterns -(include "iwmmxt.md") ;; Load the VFP co-processor patterns (include "vfp.md") ;; Thumb-1 patterns diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt index 042cb54..d5eeeae 100644 --- a/gcc/config/arm/arm.opt +++ b/gcc/config/arm/arm.opt @@ -58,9 +58,6 @@ EnumValue Enum(arm_abi_type) String(aapcs) Value(ARM_ABI_AAPCS) EnumValue -Enum(arm_abi_type) String(iwmmxt) Value(ARM_ABI_IWMMXT) - -EnumValue Enum(arm_abi_type) String(aapcs-linux) Value(ARM_ABI_AAPCS_LINUX) mabort-on-noreturn diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index 9f1a37a..24743a8 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -19,11 +19,12 @@ ;; <http://www.gnu.org/licenses/>. ;; The following register constraints have been used: -;; - in ARM/Thumb-2 state: t, w, x, y, z +;; - in ARM/Thumb-2 state: t, w, x ;; - in Thumb state: h, b ;; - in both states: l, c, k, q, Cs, Ts, US ;; In ARM state, 'l' is an alias for 'r' ;; 'f' and 'v' were previously used for FPA and MAVERICK registers. +;; 'y' and 'z' were previously used for iWMMX registers (removed after gcc-15) ;; The following normal constraints have been used: ;; in ARM/Thumb-2 state: G, I, j, J, K, L, M @@ -39,7 +40,7 @@ ;; in all states: Pg ;; The following memory constraints have been used: -;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us, Uo, Up, Uf, Ux, Ul, Uz +;; in ARM/Thumb-2 state: Uh, Ut, Uv, Un, Um, Us, Uo, Up, Uf, Ux, Ul, Uz ;; in ARM state: Uq ;; in Thumb state: Uu, Uw ;; in all states: Q @@ -112,13 +113,6 @@ (define_register_constraint "x" "TARGET_32BIT ? VFP_D0_D7_REGS : NO_REGS" "The VFP registers @code{d0}-@code{d7}.") -(define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS" - "The Intel iWMMX co-processor registers.") - -(define_register_constraint "z" - "TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS" - "The Intel iWMMX GR registers.") - (define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS" "In Thumb state the core registers @code{r0}-@code{r7}.") @@ -478,12 +472,6 @@ ? arm_coproc_mem_operand_no_writeback (op) : neon_vector_mem_operand (op, 2, true)"))) -(define_memory_constraint "Uy" - "@internal - In ARM/Thumb-2 state a valid iWMMX load/store address." - (and (match_code "mem") - (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)"))) - (define_memory_constraint "Un" "@internal In ARM/Thumb-2 state a valid address for Neon doubleword vector diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 743fe48..0c163ed 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -59,30 +59,25 @@ ;; A list of modes which the VFP unit can handle (define_mode_iterator SDF [(SF "") (DF "TARGET_VFP_DOUBLE")]) -;; Integer element sizes implemented by IWMMXT. -(define_mode_iterator VMMX [V2SI V4HI V8QI]) - -(define_mode_iterator VMMX2 [V4HI V2SI]) - ;; Integer element sizes for shifts. (define_mode_iterator VSHFT [V4HI V2SI DI]) -;; Integer and float modes supported by Neon and IWMMXT. +;; Integer and float modes supported by Neon. (define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) -;; Integer and float modes supported by Neon, IWMMXT and MVE. +;; Integer and float modes supported by Neon and MVE. (define_mode_iterator VNIM1 [V16QI V8HI V4SI V4SF V2DI]) -;; Integer and float modes supported by Neon and IWMMXT but not MVE. +;; Integer and float modes supported by Neon but not MVE. (define_mode_iterator VNINOTM1 [V2SI V4HI V8QI V2SF]) -;; Integer and float modes supported by Neon and IWMMXT, except V2DI. +;; Integer and float modes supported by Neon, except V2DI. (define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) -;; Integer modes supported by Neon and IWMMXT +;; Integer modes supported by Neon (define_mode_iterator VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI]) -;; Integer modes supported by Neon and IWMMXT, except V2DI +;; Integer modes supported by Neon, except V2DI (define_mode_iterator VINTW [V2SI V4HI V8QI V4SI V8HI V16QI]) ;; Double-width vector modes, on which we support arithmetic (no HF!) @@ -1644,9 +1639,6 @@ ;; distinguishes between 16-bit Thumb and 32-bit Thumb/ARM. (define_mode_attr arch [(CC_Z "32") (SI "t1")]) -;; Determine element size suffix from vector mode. -(define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")]) - ;; vtbl<n> suffix for NEON vector modes. (define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")]) diff --git a/gcc/config/arm/iwmmxt.md b/gcc/config/arm/iwmmxt.md deleted file mode 100644 index 0aa5dcd..0000000 --- a/gcc/config/arm/iwmmxt.md +++ /dev/null @@ -1,1766 +0,0 @@ -;; Patterns for the Intel Wireless MMX technology architecture. -;; Copyright (C) 2003-2025 Free Software Foundation, Inc. -;; Contributed by Red Hat. - -;; This file is part of GCC. - -;; GCC is free software; you can redistribute it and/or modify it under -;; the terms of the GNU General Public License as published by the Free -;; Software Foundation; either version 3, or (at your option) any later -;; version. - -;; GCC is distributed in the hope that it will be useful, but WITHOUT -;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -;; License for more details. - -;; You should have received a copy of the GNU General Public License -;; along with GCC; see the file COPYING3. If not see -;; <http://www.gnu.org/licenses/>. - -;; Register numbers. Need to sync with FIRST_IWMMXT_GR_REGNUM in arm.h -(define_constants - [(WCGR0 96) - (WCGR1 97) - (WCGR2 98) - (WCGR3 99) - ] -) - -(define_insn "tbcstv8qi" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (vec_duplicate:V8QI (match_operand:QI 1 "s_register_operand" "r")))] - "TARGET_REALLY_IWMMXT" - "tbcstb%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tbcst")] -) - -(define_insn "tbcstv4hi" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (vec_duplicate:V4HI (match_operand:HI 1 "s_register_operand" "r")))] - "TARGET_REALLY_IWMMXT" - "tbcsth%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tbcst")] -) - -(define_insn "tbcstv2si" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (vec_duplicate:V2SI (match_operand:SI 1 "s_register_operand" "r")))] - "TARGET_REALLY_IWMMXT" - "tbcstw%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tbcst")] -) - -(define_insn "iwmmxt_iordi3" - [(set (match_operand:DI 0 "register_operand" "=y") - (ior:DI (match_operand:DI 1 "register_operand" "%y") - (match_operand:DI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wor%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "length" "4") - (set_attr "type" "wmmx_wor")] -) - -(define_insn "iwmmxt_xordi3" - [(set (match_operand:DI 0 "register_operand" "=y") - (xor:DI (match_operand:DI 1 "register_operand" "%y") - (match_operand:DI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wxor%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "length" "4") - (set_attr "type" "wmmx_wxor")] -) - -(define_insn "iwmmxt_anddi3" - [(set (match_operand:DI 0 "register_operand" "=y") - (and:DI (match_operand:DI 1 "register_operand" "%y") - (match_operand:DI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wand%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "length" "4") - (set_attr "type" "wmmx_wand")] -) - -(define_insn "iwmmxt_nanddi3" - [(set (match_operand:DI 0 "register_operand" "=y") - (and:DI (match_operand:DI 1 "register_operand" "y") - (not:DI (match_operand:DI 2 "register_operand" "y"))))] - "TARGET_REALLY_IWMMXT" - "wandn%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wandn")] -) - -(define_insn "*iwmmxt_arm_movdi" - [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m,y,y,r, y,Uy,*w, r,*w,*w, *Uv") - (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r,y,r,y,Uy,y, r,*w,*w,*Uvi,*w"))] - "TARGET_REALLY_IWMMXT - && ( register_operand (operands[0], DImode) - || register_operand (operands[1], DImode))" - "* - switch (which_alternative) - { - case 0: - case 1: - case 2: - return \"#\"; - case 3: case 4: - return output_move_double (operands, true, NULL); - case 5: - return \"wmov%?\\t%0,%1\"; - case 6: - return \"tmcrr%?\\t%0,%Q1,%R1\"; - case 7: - return \"tmrrc%?\\t%Q0,%R0,%1\"; - case 8: - return \"wldrd%?\\t%0,%1\"; - case 9: - return \"wstrd%?\\t%1,%0\"; - case 10: - return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\"; - case 11: - return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\"; - case 12: - if (TARGET_VFP_SINGLE) - return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\"; - else - return \"fcpyd%?\\t%P0, %P1\\t%@ int\"; - case 13: case 14: - return output_move_vfp (operands); - default: - gcc_unreachable (); - } - " - [(set (attr "length") (cond [(eq_attr "alternative" "0,3,4") (const_int 8) - (eq_attr "alternative" "1") (const_int 12) - (eq_attr "alternative" "2") (const_int 16) - (eq_attr "alternative" "12") - (if_then_else - (eq (symbol_ref "TARGET_VFP_SINGLE") (const_int 1)) - (const_int 8) - (const_int 4))] - (const_int 4))) - (set_attr "type" "*,*,*,load_8,store_8,*,*,*,*,*,f_mcrr,f_mrrc,\ - ffarithd,f_loadd,f_stored") - (set_attr "arm_pool_range" "*,*,*,1020,*,*,*,*,*,*,*,*,*,1020,*") - (set_attr "arm_neg_pool_range" "*,*,*,1008,*,*,*,*,*,*,*,*,*,1008,*")] -) - -(define_insn "*iwmmxt_movsi_insn" - [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk, m,z,r,?z,?Uy,*t, r,*t,*t ,*Uv") - (match_operand:SI 1 "general_operand" " rk,I,K,j,mi,rk,r,z,Uy, z, r,*t,*t,*Uvi, *t"))] - "TARGET_REALLY_IWMMXT - && ( register_operand (operands[0], SImode) - || register_operand (operands[1], SImode))" - "* - switch (which_alternative) - { - case 0: return \"mov\\t%0, %1\"; - case 1: return \"mov\\t%0, %1\"; - case 2: return \"mvn\\t%0, #%B1\"; - case 3: return \"movw\\t%0, %1\"; - case 4: return \"ldr\\t%0, %1\"; - case 5: return \"str\\t%1, %0\"; - case 6: return \"tmcr\\t%0, %1\"; - case 7: return \"tmrc\\t%0, %1\"; - case 8: return arm_output_load_gr (operands); - case 9: return \"wstrw\\t%1, %0\"; - case 10:return \"fmsr\\t%0, %1\"; - case 11:return \"fmrs\\t%0, %1\"; - case 12:return \"fcpys\\t%0, %1\\t%@ int\"; - case 13: case 14: - return output_move_vfp (operands); - default: - gcc_unreachable (); - }" - [(set_attr "type" "*,*,*,*,load_4,store_4,*,*,*,*,f_mcr,f_mrc,\ - fmov,f_loads,f_stores") - (set_attr "length" "*,*,*,*,*, *,*,*, 16, *,*,*,*,*,*") - (set_attr "pool_range" "*,*,*,*,4096, *,*,*,1024, *,*,*,*,1020,*") - (set_attr "neg_pool_range" "*,*,*,*,4084, *,*,*, *, 1012,*,*,*,1008,*") - ;; Note - the "predicable" attribute is not allowed to have alternatives. - ;; Since the wSTRw wCx instruction is not predicable, we cannot support - ;; predicating any of the alternatives in this template. Instead, - ;; we do the predication ourselves, in cond_iwmmxt_movsi_insn. - (set_attr "predicable" "no") - ;; Also - we have to pretend that these insns clobber the condition code - ;; bits as otherwise arm_final_prescan_insn() will try to conditionalize - ;; them. - (set_attr "conds" "clob")] -) - -;; Because iwmmxt_movsi_insn is not predicable, we provide the -;; cond_exec version explicitly, with appropriate constraints. - -(define_insn "*cond_iwmmxt_movsi_insn" - [(cond_exec - (match_operator 2 "arm_comparison_operator" - [(match_operand 3 "cc_register" "") - (const_int 0)]) - (set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r") - (match_operand:SI 1 "general_operand" "rI,K,mi,r,r,z")))] - "TARGET_REALLY_IWMMXT - && ( register_operand (operands[0], SImode) - || register_operand (operands[1], SImode))" - "* - switch (which_alternative) - { - case 0: return \"mov%?\\t%0, %1\"; - case 1: return \"mvn%?\\t%0, #%B1\"; - case 2: return \"ldr%?\\t%0, %1\"; - case 3: return \"str%?\\t%1, %0\"; - case 4: return \"tmcr%?\\t%0, %1\"; - default: return \"tmrc%?\\t%0, %1\"; - }" - [(set_attr "type" "*,*,load_4,store_4,*,*") - (set_attr "pool_range" "*,*,4096, *,*,*") - (set_attr "neg_pool_range" "*,*,4084, *,*,*")] -) - -(define_insn "mov<mode>_internal" - [(set (match_operand:VMMX 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r,?r,?m") - (match_operand:VMMX 1 "general_operand" "y,y,mi,y,r,r,mi,r"))] - "TARGET_REALLY_IWMMXT" - "* - switch (which_alternative) - { - case 0: return \"wmov%?\\t%0, %1\"; - case 1: return \"wstrd%?\\t%1, %0\"; - case 2: return \"wldrd%?\\t%0, %1\"; - case 3: return \"tmrrc%?\\t%Q0, %R0, %1\"; - case 4: return \"tmcrr%?\\t%0, %Q1, %R1\"; - case 5: return \"#\"; - default: return output_move_double (operands, true, NULL); - }" - [(set_attr "predicable" "yes") - (set_attr "length" "4, 4, 4,4,4,8, 8,8") - (set_attr "type" "wmmx_wmov,wmmx_wstr,wmmx_wldr,wmmx_tmrrc,wmmx_tmcrr,*,load_4,store_4") - (set_attr "pool_range" "*, *, 256,*,*,*, 256,*") - (set_attr "neg_pool_range" "*, *, 244,*,*,*, 244,*")] -) - -(define_expand "iwmmxt_setwcgr0" - [(set (reg:SI WCGR0) - (match_operand:SI 0 "register_operand"))] - "TARGET_REALLY_IWMMXT" - {} -) - -(define_expand "iwmmxt_setwcgr1" - [(set (reg:SI WCGR1) - (match_operand:SI 0 "register_operand"))] - "TARGET_REALLY_IWMMXT" - {} -) - -(define_expand "iwmmxt_setwcgr2" - [(set (reg:SI WCGR2) - (match_operand:SI 0 "register_operand"))] - "TARGET_REALLY_IWMMXT" - {} -) - -(define_expand "iwmmxt_setwcgr3" - [(set (reg:SI WCGR3) - (match_operand:SI 0 "register_operand"))] - "TARGET_REALLY_IWMMXT" - {} -) - -(define_expand "iwmmxt_getwcgr0" - [(set (match_operand:SI 0 "register_operand") - (reg:SI WCGR0))] - "TARGET_REALLY_IWMMXT" - {} -) - -(define_expand "iwmmxt_getwcgr1" - [(set (match_operand:SI 0 "register_operand") - (reg:SI WCGR1))] - "TARGET_REALLY_IWMMXT" - {} -) - -(define_expand "iwmmxt_getwcgr2" - [(set (match_operand:SI 0 "register_operand") - (reg:SI WCGR2))] - "TARGET_REALLY_IWMMXT" - {} -) - -(define_expand "iwmmxt_getwcgr3" - [(set (match_operand:SI 0 "register_operand") - (reg:SI WCGR3))] - "TARGET_REALLY_IWMMXT" - {} -) - -(define_insn "*and<mode>3_iwmmxt" - [(set (match_operand:VMMX 0 "register_operand" "=y") - (and:VMMX (match_operand:VMMX 1 "register_operand" "y") - (match_operand:VMMX 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wand\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wand")] -) - -(define_insn "*ior<mode>3_iwmmxt" - [(set (match_operand:VMMX 0 "register_operand" "=y") - (ior:VMMX (match_operand:VMMX 1 "register_operand" "y") - (match_operand:VMMX 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wor\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wor")] -) - -(define_insn "*xor<mode>3_iwmmxt" - [(set (match_operand:VMMX 0 "register_operand" "=y") - (xor:VMMX (match_operand:VMMX 1 "register_operand" "y") - (match_operand:VMMX 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wxor\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wxor")] -) - - -;; Vector add/subtract - -(define_insn "*add<mode>3_iwmmxt" - [(set (match_operand:VMMX 0 "register_operand" "=y") - (plus:VMMX (match_operand:VMMX 1 "register_operand" "y") - (match_operand:VMMX 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wadd<MMX_char>%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wadd")] -) - -(define_insn "ssaddv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "waddbss%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wadd")] -) - -(define_insn "ssaddv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "waddhss%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wadd")] -) - -(define_insn "ssaddv2si3" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (ss_plus:V2SI (match_operand:V2SI 1 "register_operand" "y") - (match_operand:V2SI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "waddwss%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wadd")] -) - -(define_insn "usaddv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "waddbus%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wadd")] -) - -(define_insn "usaddv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "waddhus%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wadd")] -) - -(define_insn "usaddv2si3" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (us_plus:V2SI (match_operand:V2SI 1 "register_operand" "y") - (match_operand:V2SI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "waddwus%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wadd")] -) - -(define_insn "*sub<mode>3_iwmmxt" - [(set (match_operand:VMMX 0 "register_operand" "=y") - (minus:VMMX (match_operand:VMMX 1 "register_operand" "y") - (match_operand:VMMX 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wsub<MMX_char>%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wsub")] -) - -(define_insn "sssubv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wsubbss%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wsub")] -) - -(define_insn "sssubv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wsubhss%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wsub")] -) - -(define_insn "sssubv2si3" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (ss_minus:V2SI (match_operand:V2SI 1 "register_operand" "y") - (match_operand:V2SI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wsubwss%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wsub")] -) - -(define_insn "ussubv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wsubbus%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wsub")] -) - -(define_insn "ussubv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wsubhus%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wsub")] -) - -(define_insn "ussubv2si3" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (us_minus:V2SI (match_operand:V2SI 1 "register_operand" "y") - (match_operand:V2SI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wsubwus%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wsub")] -) - -(define_insn "*mulv4hi3_iwmmxt" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (mult:V4HI (match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wmulul%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmul")] -) - -(define_insn "smulv4hi3_highpart" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (truncate:V4HI - (lshiftrt:V4SI - (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))) - (const_int 16))))] - "TARGET_REALLY_IWMMXT" - "wmulsm%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmul")] -) - -(define_insn "umulv4hi3_highpart" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (truncate:V4HI - (lshiftrt:V4SI - (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))) - (const_int 16))))] - "TARGET_REALLY_IWMMXT" - "wmulum%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmul")] -) - -(define_insn "iwmmxt_wmacs" - [(set (match_operand:DI 0 "register_operand" "=y") - (unspec:DI [(match_operand:DI 1 "register_operand" "0") - (match_operand:V4HI 2 "register_operand" "y") - (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACS))] - "TARGET_REALLY_IWMMXT" - "wmacs%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmac")] -) - -(define_insn "iwmmxt_wmacsz" - [(set (match_operand:DI 0 "register_operand" "=y") - (unspec:DI [(match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACSZ))] - "TARGET_REALLY_IWMMXT" - "wmacsz%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmac")] -) - -(define_insn "iwmmxt_wmacu" - [(set (match_operand:DI 0 "register_operand" "=y") - (unspec:DI [(match_operand:DI 1 "register_operand" "0") - (match_operand:V4HI 2 "register_operand" "y") - (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACU))] - "TARGET_REALLY_IWMMXT" - "wmacu%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmac")] -) - -(define_insn "iwmmxt_wmacuz" - [(set (match_operand:DI 0 "register_operand" "=y") - (unspec:DI [(match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACUZ))] - "TARGET_REALLY_IWMMXT" - "wmacuz%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmac")] -) - -;; Same as xordi3, but don't show input operands so that we don't think -;; they are live. -(define_insn "iwmmxt_clrdi" - [(set (match_operand:DI 0 "register_operand" "=y") - (unspec:DI [(const_int 0)] UNSPEC_CLRDI))] - "TARGET_REALLY_IWMMXT" - "wxor%?\\t%0, %0, %0" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wxor")] -) - -;; Seems like cse likes to generate these, so we have to support them. - -(define_insn "iwmmxt_clrv8qi" - [(set (match_operand:V8QI 0 "s_register_operand" "=y") - (const_vector:V8QI [(const_int 0) (const_int 0) - (const_int 0) (const_int 0) - (const_int 0) (const_int 0) - (const_int 0) (const_int 0)]))] - "TARGET_REALLY_IWMMXT" - "wxor%?\\t%0, %0, %0" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wxor")] -) - -(define_insn "iwmmxt_clrv4hi" - [(set (match_operand:V4HI 0 "s_register_operand" "=y") - (const_vector:V4HI [(const_int 0) (const_int 0) - (const_int 0) (const_int 0)]))] - "TARGET_REALLY_IWMMXT" - "wxor%?\\t%0, %0, %0" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wxor")] -) - -(define_insn "iwmmxt_clrv2si" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (const_vector:V2SI [(const_int 0) (const_int 0)]))] - "TARGET_REALLY_IWMMXT" - "wxor%?\\t%0, %0, %0" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wxor")] -) - -;; Unsigned averages/sum of absolute differences - -(define_insn "iwmmxt_uavgrndv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (truncate:V8QI - (lshiftrt:V8HI - (plus:V8HI - (plus:V8HI (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y")) - (zero_extend:V8HI (match_operand:V8QI 2 "register_operand" "y"))) - (const_vector:V8HI [(const_int 1) - (const_int 1) - (const_int 1) - (const_int 1) - (const_int 1) - (const_int 1) - (const_int 1) - (const_int 1)])) - (const_int 1))))] - "TARGET_REALLY_IWMMXT" - "wavg2br%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wavg2")] -) - -(define_insn "iwmmxt_uavgrndv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (truncate:V4HI - (lshiftrt:V4SI - (plus:V4SI - (plus:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))) - (const_vector:V4SI [(const_int 1) - (const_int 1) - (const_int 1) - (const_int 1)])) - (const_int 1))))] - "TARGET_REALLY_IWMMXT" - "wavg2hr%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wavg2")] -) - -(define_insn "iwmmxt_uavgv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (truncate:V8QI - (lshiftrt:V8HI - (plus:V8HI (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y")) - (zero_extend:V8HI (match_operand:V8QI 2 "register_operand" "y"))) - (const_int 1))))] - "TARGET_REALLY_IWMMXT" - "wavg2b%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wavg2")] -) - -(define_insn "iwmmxt_uavgv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (truncate:V4HI - (lshiftrt:V4SI - (plus:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))) - (const_int 1))))] - "TARGET_REALLY_IWMMXT" - "wavg2h%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wavg2")] -) - -;; Insert/extract/shuffle - -(define_insn "iwmmxt_tinsrb" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (vec_merge:V8QI - (vec_duplicate:V8QI - (truncate:QI (match_operand:SI 2 "nonimmediate_operand" "r"))) - (match_operand:V8QI 1 "register_operand" "0") - (match_operand:SI 3 "immediate_operand" "i")))] - "TARGET_REALLY_IWMMXT" - "* - { - return arm_output_iwmmxt_tinsr (operands); - } - " - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tinsr")] -) - -(define_insn "iwmmxt_tinsrh" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (vec_merge:V4HI - (vec_duplicate:V4HI - (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "r"))) - (match_operand:V4HI 1 "register_operand" "0") - (match_operand:SI 3 "immediate_operand" "i")))] - "TARGET_REALLY_IWMMXT" - "* - { - return arm_output_iwmmxt_tinsr (operands); - } - " - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tinsr")] -) - -(define_insn "iwmmxt_tinsrw" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (vec_merge:V2SI - (vec_duplicate:V2SI - (match_operand:SI 2 "nonimmediate_operand" "r")) - (match_operand:V2SI 1 "register_operand" "0") - (match_operand:SI 3 "immediate_operand" "i")))] - "TARGET_REALLY_IWMMXT" - "* - { - return arm_output_iwmmxt_tinsr (operands); - } - " - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tinsr")] -) - -(define_insn "iwmmxt_textrmub" - [(set (match_operand:SI 0 "register_operand" "=r") - (zero_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y") - (parallel - [(match_operand:SI 2 "immediate_operand" "i")]))))] - "TARGET_REALLY_IWMMXT" - "textrmub%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_textrm")] -) - -(define_insn "iwmmxt_textrmsb" - [(set (match_operand:SI 0 "register_operand" "=r") - (sign_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y") - (parallel - [(match_operand:SI 2 "immediate_operand" "i")]))))] - "TARGET_REALLY_IWMMXT" - "textrmsb%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_textrm")] -) - -(define_insn "iwmmxt_textrmuh" - [(set (match_operand:SI 0 "register_operand" "=r") - (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y") - (parallel - [(match_operand:SI 2 "immediate_operand" "i")]))))] - "TARGET_REALLY_IWMMXT" - "textrmuh%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_textrm")] -) - -(define_insn "iwmmxt_textrmsh" - [(set (match_operand:SI 0 "register_operand" "=r") - (sign_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y") - (parallel - [(match_operand:SI 2 "immediate_operand" "i")]))))] - "TARGET_REALLY_IWMMXT" - "textrmsh%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_textrm")] -) - -;; There are signed/unsigned variants of this instruction, but they are -;; pointless. -(define_insn "iwmmxt_textrmw" - [(set (match_operand:SI 0 "register_operand" "=r") - (vec_select:SI (match_operand:V2SI 1 "register_operand" "y") - (parallel [(match_operand:SI 2 "immediate_operand" "i")])))] - "TARGET_REALLY_IWMMXT" - "textrmsw%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_textrm")] -) - -(define_insn "iwmmxt_wshufh" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y") - (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_WSHUFH))] - "TARGET_REALLY_IWMMXT" - "wshufh%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wshufh")] -) - -;; Mask-generating comparisons -;; -;; Note - you cannot use patterns like these here: -;; -;; (set (match:<vector>) (<comparator>:<vector> (match:<vector>) (match:<vector>))) -;; -;; Because GCC will assume that the truth value (1 or 0) is installed -;; into the entire destination vector, (with the '1' going into the least -;; significant element of the vector). This is not how these instructions -;; behave. - -(define_insn "eqv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (unspec_volatile:V8QI [(match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")] - VUNSPEC_WCMP_EQ))] - "TARGET_REALLY_IWMMXT" - "wcmpeqb%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wcmpeq")] -) - -(define_insn "eqv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (unspec_volatile:V4HI [(match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")] - VUNSPEC_WCMP_EQ))] - "TARGET_REALLY_IWMMXT" - "wcmpeqh%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wcmpeq")] -) - -(define_insn "eqv2si3" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec_volatile:V2SI - [(match_operand:V2SI 1 "register_operand" "y") - (match_operand:V2SI 2 "register_operand" "y")] - VUNSPEC_WCMP_EQ))] - "TARGET_REALLY_IWMMXT" - "wcmpeqw%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wcmpeq")] -) - -(define_insn "gtuv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (unspec_volatile:V8QI [(match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")] - VUNSPEC_WCMP_GTU))] - "TARGET_REALLY_IWMMXT" - "wcmpgtub%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wcmpgt")] -) - -(define_insn "gtuv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (unspec_volatile:V4HI [(match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")] - VUNSPEC_WCMP_GTU))] - "TARGET_REALLY_IWMMXT" - "wcmpgtuh%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wcmpgt")] -) - -(define_insn "gtuv2si3" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec_volatile:V2SI [(match_operand:V2SI 1 "register_operand" "y") - (match_operand:V2SI 2 "register_operand" "y")] - VUNSPEC_WCMP_GTU))] - "TARGET_REALLY_IWMMXT" - "wcmpgtuw%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wcmpgt")] -) - -(define_insn "gtv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (unspec_volatile:V8QI [(match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")] - VUNSPEC_WCMP_GT))] - "TARGET_REALLY_IWMMXT" - "wcmpgtsb%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wcmpgt")] -) - -(define_insn "gtv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (unspec_volatile:V4HI [(match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")] - VUNSPEC_WCMP_GT))] - "TARGET_REALLY_IWMMXT" - "wcmpgtsh%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wcmpgt")] -) - -(define_insn "gtv2si3" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec_volatile:V2SI [(match_operand:V2SI 1 "register_operand" "y") - (match_operand:V2SI 2 "register_operand" "y")] - VUNSPEC_WCMP_GT))] - "TARGET_REALLY_IWMMXT" - "wcmpgtsw%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wcmpgt")] -) - -;; Max/min insns - -(define_insn "*smax<mode>3_iwmmxt" - [(set (match_operand:VMMX 0 "register_operand" "=y") - (smax:VMMX (match_operand:VMMX 1 "register_operand" "y") - (match_operand:VMMX 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wmaxs<MMX_char>%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmax")] -) - -(define_insn "*umax<mode>3_iwmmxt" - [(set (match_operand:VMMX 0 "register_operand" "=y") - (umax:VMMX (match_operand:VMMX 1 "register_operand" "y") - (match_operand:VMMX 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wmaxu<MMX_char>%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmax")] -) - -(define_insn "*smin<mode>3_iwmmxt" - [(set (match_operand:VMMX 0 "register_operand" "=y") - (smin:VMMX (match_operand:VMMX 1 "register_operand" "y") - (match_operand:VMMX 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wmins<MMX_char>%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmin")] -) - -(define_insn "*umin<mode>3_iwmmxt" - [(set (match_operand:VMMX 0 "register_operand" "=y") - (umin:VMMX (match_operand:VMMX 1 "register_operand" "y") - (match_operand:VMMX 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wminu<MMX_char>%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmin")] -) - -;; Pack/unpack insns. - -(define_insn "iwmmxt_wpackhss" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (vec_concat:V8QI - (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y")) - (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))] - "TARGET_REALLY_IWMMXT" - "wpackhss%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wpack")] -) - -(define_insn "iwmmxt_wpackwss" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (vec_concat:V4HI - (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y")) - (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))] - "TARGET_REALLY_IWMMXT" - "wpackwss%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wpack")] -) - -(define_insn "iwmmxt_wpackdss" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (vec_concat:V2SI - (ss_truncate:SI (match_operand:DI 1 "register_operand" "y")) - (ss_truncate:SI (match_operand:DI 2 "register_operand" "y"))))] - "TARGET_REALLY_IWMMXT" - "wpackdss%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wpack")] -) - -(define_insn "iwmmxt_wpackhus" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (vec_concat:V8QI - (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y")) - (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))] - "TARGET_REALLY_IWMMXT" - "wpackhus%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wpack")] -) - -(define_insn "iwmmxt_wpackwus" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (vec_concat:V4HI - (us_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y")) - (us_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))] - "TARGET_REALLY_IWMMXT" - "wpackwus%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wpack")] -) - -(define_insn "iwmmxt_wpackdus" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (vec_concat:V2SI - (us_truncate:SI (match_operand:DI 1 "register_operand" "y")) - (us_truncate:SI (match_operand:DI 2 "register_operand" "y"))))] - "TARGET_REALLY_IWMMXT" - "wpackdus%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wpack")] -) - -(define_insn "iwmmxt_wunpckihb" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (vec_merge:V8QI - (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y") - (parallel [(const_int 4) - (const_int 0) - (const_int 5) - (const_int 1) - (const_int 6) - (const_int 2) - (const_int 7) - (const_int 3)])) - (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y") - (parallel [(const_int 0) - (const_int 4) - (const_int 1) - (const_int 5) - (const_int 2) - (const_int 6) - (const_int 3) - (const_int 7)])) - (const_int 85)))] - "TARGET_REALLY_IWMMXT" - "wunpckihb%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckih")] -) - -(define_insn "iwmmxt_wunpckihh" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (vec_merge:V4HI - (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y") - (parallel [(const_int 2) - (const_int 0) - (const_int 3) - (const_int 1)])) - (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y") - (parallel [(const_int 0) - (const_int 2) - (const_int 1) - (const_int 3)])) - (const_int 5)))] - "TARGET_REALLY_IWMMXT" - "wunpckihh%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckih")] -) - -(define_insn "iwmmxt_wunpckihw" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (vec_merge:V2SI - (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y") - (parallel [(const_int 1) - (const_int 0)])) - (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y") - (parallel [(const_int 0) - (const_int 1)])) - (const_int 1)))] - "TARGET_REALLY_IWMMXT" - "wunpckihw%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckih")] -) - -(define_insn "iwmmxt_wunpckilb" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (vec_merge:V8QI - (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y") - (parallel [(const_int 0) - (const_int 4) - (const_int 1) - (const_int 5) - (const_int 2) - (const_int 6) - (const_int 3) - (const_int 7)])) - (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y") - (parallel [(const_int 4) - (const_int 0) - (const_int 5) - (const_int 1) - (const_int 6) - (const_int 2) - (const_int 7) - (const_int 3)])) - (const_int 85)))] - "TARGET_REALLY_IWMMXT" - "wunpckilb%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckil")] -) - -(define_insn "iwmmxt_wunpckilh" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (vec_merge:V4HI - (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y") - (parallel [(const_int 0) - (const_int 2) - (const_int 1) - (const_int 3)])) - (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y") - (parallel [(const_int 2) - (const_int 0) - (const_int 3) - (const_int 1)])) - (const_int 5)))] - "TARGET_REALLY_IWMMXT" - "wunpckilh%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckil")] -) - -(define_insn "iwmmxt_wunpckilw" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (vec_merge:V2SI - (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y") - (parallel [(const_int 0) - (const_int 1)])) - (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y") - (parallel [(const_int 1) - (const_int 0)])) - (const_int 1)))] - "TARGET_REALLY_IWMMXT" - "wunpckilw%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckil")] -) - -(define_insn "iwmmxt_wunpckehub" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (vec_select:V4HI - (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y")) - (parallel [(const_int 4) (const_int 5) - (const_int 6) (const_int 7)])))] - "TARGET_REALLY_IWMMXT" - "wunpckehub%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckeh")] -) - -(define_insn "iwmmxt_wunpckehuh" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (vec_select:V2SI - (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (parallel [(const_int 2) (const_int 3)])))] - "TARGET_REALLY_IWMMXT" - "wunpckehuh%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckeh")] -) - -(define_insn "iwmmxt_wunpckehuw" - [(set (match_operand:DI 0 "register_operand" "=y") - (vec_select:DI - (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y")) - (parallel [(const_int 1)])))] - "TARGET_REALLY_IWMMXT" - "wunpckehuw%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckeh")] -) - -(define_insn "iwmmxt_wunpckehsb" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (vec_select:V4HI - (sign_extend:V8HI (match_operand:V8QI 1 "register_operand" "y")) - (parallel [(const_int 4) (const_int 5) - (const_int 6) (const_int 7)])))] - "TARGET_REALLY_IWMMXT" - "wunpckehsb%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckeh")] -) - -(define_insn "iwmmxt_wunpckehsh" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (vec_select:V2SI - (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (parallel [(const_int 2) (const_int 3)])))] - "TARGET_REALLY_IWMMXT" - "wunpckehsh%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckeh")] -) - -(define_insn "iwmmxt_wunpckehsw" - [(set (match_operand:DI 0 "register_operand" "=y") - (vec_select:DI - (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y")) - (parallel [(const_int 1)])))] - "TARGET_REALLY_IWMMXT" - "wunpckehsw%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckeh")] -) - -(define_insn "iwmmxt_wunpckelub" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (vec_select:V4HI - (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y")) - (parallel [(const_int 0) (const_int 1) - (const_int 2) (const_int 3)])))] - "TARGET_REALLY_IWMMXT" - "wunpckelub%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckel")] -) - -(define_insn "iwmmxt_wunpckeluh" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (vec_select:V2SI - (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (parallel [(const_int 0) (const_int 1)])))] - "TARGET_REALLY_IWMMXT" - "wunpckeluh%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckel")] -) - -(define_insn "iwmmxt_wunpckeluw" - [(set (match_operand:DI 0 "register_operand" "=y") - (vec_select:DI - (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y")) - (parallel [(const_int 0)])))] - "TARGET_REALLY_IWMMXT" - "wunpckeluw%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckel")] -) - -(define_insn "iwmmxt_wunpckelsb" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (vec_select:V4HI - (sign_extend:V8HI (match_operand:V8QI 1 "register_operand" "y")) - (parallel [(const_int 0) (const_int 1) - (const_int 2) (const_int 3)])))] - "TARGET_REALLY_IWMMXT" - "wunpckelsb%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckel")] -) - -(define_insn "iwmmxt_wunpckelsh" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (vec_select:V2SI - (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (parallel [(const_int 0) (const_int 1)])))] - "TARGET_REALLY_IWMMXT" - "wunpckelsh%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckel")] -) - -(define_insn "iwmmxt_wunpckelsw" - [(set (match_operand:DI 0 "register_operand" "=y") - (vec_select:DI - (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y")) - (parallel [(const_int 0)])))] - "TARGET_REALLY_IWMMXT" - "wunpckelsw%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckel")] -) - -;; Shifts - -(define_insn "ror<mode>3" - [(set (match_operand:VSHFT 0 "register_operand" "=y,y") - (rotatert:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y") - (match_operand:SI 2 "imm_or_reg_operand" "z,i")))] - "TARGET_REALLY_IWMMXT" - "* - switch (which_alternative) - { - case 0: - return \"wror<MMX_char>g%?\\t%0, %1, %2\"; - case 1: - return arm_output_iwmmxt_shift_immediate (\"wror<MMX_char>\", operands, true); - default: - gcc_unreachable (); - } - " - [(set_attr "predicable" "yes") - (set_attr "arch" "*, iwmmxt2") - (set_attr "type" "wmmx_wror, wmmx_wror")] -) - -(define_insn "ashr<mode>3_iwmmxt" - [(set (match_operand:VSHFT 0 "register_operand" "=y,y") - (ashiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y") - (match_operand:SI 2 "imm_or_reg_operand" "z,i")))] - "TARGET_REALLY_IWMMXT" - "* - switch (which_alternative) - { - case 0: - return \"wsra<MMX_char>g%?\\t%0, %1, %2\"; - case 1: - return arm_output_iwmmxt_shift_immediate (\"wsra<MMX_char>\", operands, true); - default: - gcc_unreachable (); - } - " - [(set_attr "predicable" "yes") - (set_attr "arch" "*, iwmmxt2") - (set_attr "type" "wmmx_wsra, wmmx_wsra")] -) - -(define_insn "lshr<mode>3_iwmmxt" - [(set (match_operand:VSHFT 0 "register_operand" "=y,y") - (lshiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y") - (match_operand:SI 2 "imm_or_reg_operand" "z,i")))] - "TARGET_REALLY_IWMMXT" - "* - switch (which_alternative) - { - case 0: - return \"wsrl<MMX_char>g%?\\t%0, %1, %2\"; - case 1: - return arm_output_iwmmxt_shift_immediate (\"wsrl<MMX_char>\", operands, false); - default: - gcc_unreachable (); - } - " - [(set_attr "predicable" "yes") - (set_attr "arch" "*, iwmmxt2") - (set_attr "type" "wmmx_wsrl, wmmx_wsrl")] -) - -(define_insn "ashl<mode>3_iwmmxt" - [(set (match_operand:VSHFT 0 "register_operand" "=y,y") - (ashift:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y") - (match_operand:SI 2 "imm_or_reg_operand" "z,i")))] - "TARGET_REALLY_IWMMXT" - "* - switch (which_alternative) - { - case 0: - return \"wsll<MMX_char>g%?\\t%0, %1, %2\"; - case 1: - return arm_output_iwmmxt_shift_immediate (\"wsll<MMX_char>\", operands, false); - default: - gcc_unreachable (); - } - " - [(set_attr "predicable" "yes") - (set_attr "arch" "*, iwmmxt2") - (set_attr "type" "wmmx_wsll, wmmx_wsll")] -) - -(define_insn "ror<mode>3_di" - [(set (match_operand:VSHFT 0 "register_operand" "=y,y") - (rotatert:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y") - (match_operand:DI 2 "imm_or_reg_operand" "y,i")))] - "TARGET_REALLY_IWMMXT" - "* - switch (which_alternative) - { - case 0: - return \"wror<MMX_char>%?\\t%0, %1, %2\"; - case 1: - return arm_output_iwmmxt_shift_immediate (\"wror<MMX_char>\", operands, true); - default: - gcc_unreachable (); - } - " - [(set_attr "predicable" "yes") - (set_attr "arch" "*, iwmmxt2") - (set_attr "type" "wmmx_wror, wmmx_wror")] -) - -(define_insn "ashr<mode>3_di" - [(set (match_operand:VSHFT 0 "register_operand" "=y,y") - (ashiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y") - (match_operand:DI 2 "imm_or_reg_operand" "y,i")))] - "TARGET_REALLY_IWMMXT" - "* - switch (which_alternative) - { - case 0: - return \"wsra<MMX_char>%?\\t%0, %1, %2\"; - case 1: - return arm_output_iwmmxt_shift_immediate (\"wsra<MMX_char>\", operands, true); - default: - gcc_unreachable (); - } - " - [(set_attr "predicable" "yes") - (set_attr "arch" "*, iwmmxt2") - (set_attr "type" "wmmx_wsra, wmmx_wsra")] -) - -(define_insn "lshr<mode>3_di" - [(set (match_operand:VSHFT 0 "register_operand" "=y,y") - (lshiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y") - (match_operand:DI 2 "register_operand" "y,i")))] - "TARGET_REALLY_IWMMXT" - "* - switch (which_alternative) - { - case 0: - return \"wsrl<MMX_char>%?\\t%0, %1, %2\"; - case 1: - return arm_output_iwmmxt_shift_immediate (\"wsrl<MMX_char>\", operands, false); - default: - gcc_unreachable (); - } - " - [(set_attr "predicable" "yes") - (set_attr "arch" "*, iwmmxt2") - (set_attr "type" "wmmx_wsrl, wmmx_wsrl")] -) - -(define_insn "ashl<mode>3_di" - [(set (match_operand:VSHFT 0 "register_operand" "=y,y") - (ashift:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y") - (match_operand:DI 2 "imm_or_reg_operand" "y,i")))] - "TARGET_REALLY_IWMMXT" - "* - switch (which_alternative) - { - case 0: - return \"wsll<MMX_char>%?\\t%0, %1, %2\"; - case 1: - return arm_output_iwmmxt_shift_immediate (\"wsll<MMX_char>\", operands, false); - default: - gcc_unreachable (); - } - " - [(set_attr "predicable" "yes") - (set_attr "arch" "*, iwmmxt2") - (set_attr "type" "wmmx_wsll, wmmx_wsll")] -) - -(define_insn "iwmmxt_wmadds" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (plus:V2SI - (mult:V2SI - (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (parallel [(const_int 1) (const_int 3)])) - (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")) - (parallel [(const_int 1) (const_int 3)]))) - (mult:V2SI - (vec_select:V2SI (sign_extend:V4SI (match_dup 1)) - (parallel [(const_int 0) (const_int 2)])) - (vec_select:V2SI (sign_extend:V4SI (match_dup 2)) - (parallel [(const_int 0) (const_int 2)])))))] - "TARGET_REALLY_IWMMXT" - "wmadds%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmadd")] -) - -(define_insn "iwmmxt_wmaddu" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (plus:V2SI - (mult:V2SI - (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (parallel [(const_int 1) (const_int 3)])) - (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")) - (parallel [(const_int 1) (const_int 3)]))) - (mult:V2SI - (vec_select:V2SI (zero_extend:V4SI (match_dup 1)) - (parallel [(const_int 0) (const_int 2)])) - (vec_select:V2SI (zero_extend:V4SI (match_dup 2)) - (parallel [(const_int 0) (const_int 2)])))))] - "TARGET_REALLY_IWMMXT" - "wmaddu%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmadd")] -) - -(define_insn "iwmmxt_tmia" - [(set (match_operand:DI 0 "register_operand" "=y") - (plus:DI (match_operand:DI 1 "register_operand" "0") - (mult:DI (sign_extend:DI - (match_operand:SI 2 "register_operand" "r")) - (sign_extend:DI - (match_operand:SI 3 "register_operand" "r")))))] - "TARGET_REALLY_IWMMXT" - "tmia%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tmia")] -) - -(define_insn "iwmmxt_tmiaph" - [(set (match_operand:DI 0 "register_operand" "=y") - (plus:DI (match_operand:DI 1 "register_operand" "0") - (plus:DI - (mult:DI (sign_extend:DI - (truncate:HI (match_operand:SI 2 "register_operand" "r"))) - (sign_extend:DI - (truncate:HI (match_operand:SI 3 "register_operand" "r")))) - (mult:DI (sign_extend:DI - (truncate:HI (ashiftrt:SI (match_dup 2) (const_int 16)))) - (sign_extend:DI - (truncate:HI (ashiftrt:SI (match_dup 3) (const_int 16))))))))] - "TARGET_REALLY_IWMMXT" - "tmiaph%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tmiaph")] -) - -(define_insn "iwmmxt_tmiabb" - [(set (match_operand:DI 0 "register_operand" "=y") - (plus:DI (match_operand:DI 1 "register_operand" "0") - (mult:DI (sign_extend:DI - (truncate:HI (match_operand:SI 2 "register_operand" "r"))) - (sign_extend:DI - (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))] - "TARGET_REALLY_IWMMXT" - "tmiabb%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tmiaxy")] -) - -(define_insn "iwmmxt_tmiatb" - [(set (match_operand:DI 0 "register_operand" "=y") - (plus:DI (match_operand:DI 1 "register_operand" "0") - (mult:DI (sign_extend:DI - (truncate:HI - (ashiftrt:SI - (match_operand:SI 2 "register_operand" "r") - (const_int 16)))) - (sign_extend:DI - (truncate:HI - (match_operand:SI 3 "register_operand" "r"))))))] - "TARGET_REALLY_IWMMXT" - "tmiatb%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tmiaxy")] -) - -(define_insn "iwmmxt_tmiabt" - [(set (match_operand:DI 0 "register_operand" "=y") - (plus:DI (match_operand:DI 1 "register_operand" "0") - (mult:DI (sign_extend:DI - (truncate:HI - (match_operand:SI 2 "register_operand" "r"))) - (sign_extend:DI - (truncate:HI - (ashiftrt:SI - (match_operand:SI 3 "register_operand" "r") - (const_int 16)))))))] - "TARGET_REALLY_IWMMXT" - "tmiabt%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tmiaxy")] -) - -(define_insn "iwmmxt_tmiatt" - [(set (match_operand:DI 0 "register_operand" "=y") - (plus:DI (match_operand:DI 1 "register_operand" "0") - (mult:DI (sign_extend:DI - (truncate:HI - (ashiftrt:SI - (match_operand:SI 2 "register_operand" "r") - (const_int 16)))) - (sign_extend:DI - (truncate:HI - (ashiftrt:SI - (match_operand:SI 3 "register_operand" "r") - (const_int 16)))))))] - "TARGET_REALLY_IWMMXT" - "tmiatt%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tmiaxy")] -) - -(define_insn "iwmmxt_tmovmskb" - [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_TMOVMSK))] - "TARGET_REALLY_IWMMXT" - "tmovmskb%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tmovmsk")] -) - -(define_insn "iwmmxt_tmovmskh" - [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_TMOVMSK))] - "TARGET_REALLY_IWMMXT" - "tmovmskh%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tmovmsk")] -) - -(define_insn "iwmmxt_tmovmskw" - [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_TMOVMSK))] - "TARGET_REALLY_IWMMXT" - "tmovmskw%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tmovmsk")] -) - -(define_insn "iwmmxt_waccb" - [(set (match_operand:DI 0 "register_operand" "=y") - (unspec:DI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_WACC))] - "TARGET_REALLY_IWMMXT" - "waccb%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wacc")] -) - -(define_insn "iwmmxt_wacch" - [(set (match_operand:DI 0 "register_operand" "=y") - (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_WACC))] - "TARGET_REALLY_IWMMXT" - "wacch%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wacc")] -) - -(define_insn "iwmmxt_waccw" - [(set (match_operand:DI 0 "register_operand" "=y") - (unspec:DI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_WACC))] - "TARGET_REALLY_IWMMXT" - "waccw%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wacc")] -) - -;; use unspec here to prevent 8 * imm to be optimized by cse -(define_insn "iwmmxt_waligni" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (unspec:V8QI [(subreg:V8QI - (ashiftrt:TI - (subreg:TI (vec_concat:V16QI - (match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")) 0) - (mult:SI - (match_operand:SI 3 "immediate_operand" "i") - (const_int 8))) 0)] UNSPEC_WALIGNI))] - "TARGET_REALLY_IWMMXT" - "waligni%?\\t%0, %1, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_waligni")] -) - -(define_insn "iwmmxt_walignr" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (subreg:V8QI (ashiftrt:TI - (subreg:TI (vec_concat:V16QI - (match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")) 0) - (mult:SI - (zero_extract:SI (match_operand:SI 3 "register_operand" "z") (const_int 3) (const_int 0)) - (const_int 8))) 0))] - "TARGET_REALLY_IWMMXT" - "walignr%U3%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_walignr")] -) - -(define_insn "iwmmxt_walignr0" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (subreg:V8QI (ashiftrt:TI - (subreg:TI (vec_concat:V16QI - (match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")) 0) - (mult:SI - (zero_extract:SI (reg:SI WCGR0) (const_int 3) (const_int 0)) - (const_int 8))) 0))] - "TARGET_REALLY_IWMMXT" - "walignr0%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_walignr")] -) - -(define_insn "iwmmxt_walignr1" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (subreg:V8QI (ashiftrt:TI - (subreg:TI (vec_concat:V16QI - (match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")) 0) - (mult:SI - (zero_extract:SI (reg:SI WCGR1) (const_int 3) (const_int 0)) - (const_int 8))) 0))] - "TARGET_REALLY_IWMMXT" - "walignr1%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_walignr")] -) - -(define_insn "iwmmxt_walignr2" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (subreg:V8QI (ashiftrt:TI - (subreg:TI (vec_concat:V16QI - (match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")) 0) - (mult:SI - (zero_extract:SI (reg:SI WCGR2) (const_int 3) (const_int 0)) - (const_int 8))) 0))] - "TARGET_REALLY_IWMMXT" - "walignr2%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_walignr")] -) - -(define_insn "iwmmxt_walignr3" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (subreg:V8QI (ashiftrt:TI - (subreg:TI (vec_concat:V16QI - (match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")) 0) - (mult:SI - (zero_extract:SI (reg:SI WCGR3) (const_int 3) (const_int 0)) - (const_int 8))) 0))] - "TARGET_REALLY_IWMMXT" - "walignr3%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_walignr")] -) - -(define_insn "iwmmxt_wsadb" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec:V2SI [ - (match_operand:V2SI 1 "register_operand" "0") - (match_operand:V8QI 2 "register_operand" "y") - (match_operand:V8QI 3 "register_operand" "y")] UNSPEC_WSAD))] - "TARGET_REALLY_IWMMXT" - "wsadb%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wsad")] -) - -(define_insn "iwmmxt_wsadh" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec:V2SI [ - (match_operand:V2SI 1 "register_operand" "0") - (match_operand:V4HI 2 "register_operand" "y") - (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WSAD))] - "TARGET_REALLY_IWMMXT" - "wsadh%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wsad")] -) - -(define_insn "iwmmxt_wsadbz" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec:V2SI [(match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSADZ))] - "TARGET_REALLY_IWMMXT" - "wsadbz%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wsad")] -) - -(define_insn "iwmmxt_wsadhz" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec:V2SI [(match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSADZ))] - "TARGET_REALLY_IWMMXT" - "wsadhz%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wsad")] -) - -(include "iwmmxt2.md") diff --git a/gcc/config/arm/iwmmxt2.md b/gcc/config/arm/iwmmxt2.md deleted file mode 100644 index 74cd148..0000000 --- a/gcc/config/arm/iwmmxt2.md +++ /dev/null @@ -1,903 +0,0 @@ -;; Patterns for the Intel Wireless MMX technology architecture. -;; Copyright (C) 2011-2025 Free Software Foundation, Inc. -;; Written by Marvell, Inc. -;; -;; This file is part of GCC. -;; -;; GCC is free software; you can redistribute it and/or modify it -;; under the terms of the GNU General Public License as published -;; by the Free Software Foundation; either version 3, or (at your -;; option) any later version. - -;; GCC is distributed in the hope that it will be useful, but WITHOUT -;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -;; License for more details. - -;; You should have received a copy of the GNU General Public License -;; along with GCC; see the file COPYING3. If not see -;; <http://www.gnu.org/licenses/>. - -(define_insn "iwmmxt_wabs<mode>3" - [(set (match_operand:VMMX 0 "register_operand" "=y") - (unspec:VMMX [(match_operand:VMMX 1 "register_operand" "y")] UNSPEC_WABS))] - "TARGET_REALLY_IWMMXT" - "wabs<MMX_char>%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wabs")] -) - -(define_insn "iwmmxt_wabsdiffb" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (truncate:V8QI - (abs:V8HI - (minus:V8HI - (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y")) - (zero_extend:V8HI (match_operand:V8QI 2 "register_operand" "y"))))))] - "TARGET_REALLY_IWMMXT" - "wabsdiffb%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wabsdiff")] -) - -(define_insn "iwmmxt_wabsdiffh" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (truncate: V4HI - (abs:V4SI - (minus:V4SI - (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))))))] - "TARGET_REALLY_IWMMXT" - "wabsdiffh%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wabsdiff")] -) - -(define_insn "iwmmxt_wabsdiffw" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (truncate: V2SI - (abs:V2DI - (minus:V2DI - (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y")) - (zero_extend:V2DI (match_operand:V2SI 2 "register_operand" "y"))))))] - "TARGET_REALLY_IWMMXT" - "wabsdiffw%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wabsdiff")] -) - -(define_insn "iwmmxt_waddsubhx" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (vec_merge:V4HI - (ss_minus:V4HI - (match_operand:V4HI 1 "register_operand" "y") - (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y") - (parallel [(const_int 1) (const_int 0) (const_int 3) (const_int 2)]))) - (ss_plus:V4HI - (match_dup 1) - (vec_select:V4HI (match_dup 2) - (parallel [(const_int 1) (const_int 0) (const_int 3) (const_int 2)]))) - (const_int 10)))] - "TARGET_REALLY_IWMMXT" - "waddsubhx%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_waddsubhx")] -) - -(define_insn "iwmmxt_wsubaddhx" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (vec_merge:V4HI - (ss_plus:V4HI - (match_operand:V4HI 1 "register_operand" "y") - (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y") - (parallel [(const_int 1) (const_int 0) (const_int 3) (const_int 2)]))) - (ss_minus:V4HI - (match_dup 1) - (vec_select:V4HI (match_dup 2) - (parallel [(const_int 1) (const_int 0) (const_int 3) (const_int 2)]))) - (const_int 10)))] - "TARGET_REALLY_IWMMXT" - "wsubaddhx%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wsubaddhx")] -) - -(define_insn "addc<mode>3" - [(set (match_operand:VMMX2 0 "register_operand" "=y") - (unspec:VMMX2 - [(plus:VMMX2 - (match_operand:VMMX2 1 "register_operand" "y") - (match_operand:VMMX2 2 "register_operand" "y"))] UNSPEC_WADDC))] - "TARGET_REALLY_IWMMXT" - "wadd<MMX_char>c%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wadd")] -) - -(define_insn "iwmmxt_avg4" -[(set (match_operand:V8QI 0 "register_operand" "=y") - (truncate:V8QI - (vec_select:V8HI - (vec_merge:V8HI - (lshiftrt:V8HI - (plus:V8HI - (plus:V8HI - (plus:V8HI - (plus:V8HI - (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y")) - (zero_extend:V8HI (match_operand:V8QI 2 "register_operand" "y"))) - (vec_select:V8HI (zero_extend:V8HI (match_dup 1)) - (parallel [(const_int 7) (const_int 0) (const_int 1) (const_int 2) - (const_int 3) (const_int 4) (const_int 5) (const_int 6)]))) - (vec_select:V8HI (zero_extend:V8HI (match_dup 2)) - (parallel [(const_int 7) (const_int 0) (const_int 1) (const_int 2) - (const_int 3) (const_int 4) (const_int 5) (const_int 6)]))) - (const_vector:V8HI [(const_int 1) (const_int 1) (const_int 1) (const_int 1) - (const_int 1) (const_int 1) (const_int 1) (const_int 1)])) - (const_int 2)) - (const_vector:V8HI [(const_int 0) (const_int 0) (const_int 0) (const_int 0) - (const_int 0) (const_int 0) (const_int 0) (const_int 0)]) - (const_int 254)) - (parallel [(const_int 1) (const_int 2) (const_int 3) (const_int 4) - (const_int 5) (const_int 6) (const_int 7) (const_int 0)]))))] - "TARGET_REALLY_IWMMXT" - "wavg4%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wavg4")] -) - -(define_insn "iwmmxt_avg4r" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (truncate:V8QI - (vec_select:V8HI - (vec_merge:V8HI - (lshiftrt:V8HI - (plus:V8HI - (plus:V8HI - (plus:V8HI - (plus:V8HI - (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y")) - (zero_extend:V8HI (match_operand:V8QI 2 "register_operand" "y"))) - (vec_select:V8HI (zero_extend:V8HI (match_dup 1)) - (parallel [(const_int 7) (const_int 0) (const_int 1) (const_int 2) - (const_int 3) (const_int 4) (const_int 5) (const_int 6)]))) - (vec_select:V8HI (zero_extend:V8HI (match_dup 2)) - (parallel [(const_int 7) (const_int 0) (const_int 1) (const_int 2) - (const_int 3) (const_int 4) (const_int 5) (const_int 6)]))) - (const_vector:V8HI [(const_int 2) (const_int 2) (const_int 2) (const_int 2) - (const_int 2) (const_int 2) (const_int 2) (const_int 2)])) - (const_int 2)) - (const_vector:V8HI [(const_int 0) (const_int 0) (const_int 0) (const_int 0) - (const_int 0) (const_int 0) (const_int 0) (const_int 0)]) - (const_int 254)) - (parallel [(const_int 1) (const_int 2) (const_int 3) (const_int 4) - (const_int 5) (const_int 6) (const_int 7) (const_int 0)]))))] - "TARGET_REALLY_IWMMXT" - "wavg4r%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wavg4")] -) - -(define_insn "iwmmxt_wmaddsx" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (plus:V2SI - (mult:V2SI - (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (parallel [(const_int 1) (const_int 3)])) - (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")) - (parallel [(const_int 0) (const_int 2)]))) - (mult:V2SI - (vec_select:V2SI (sign_extend:V4SI (match_dup 1)) - (parallel [(const_int 0) (const_int 2)])) - (vec_select:V2SI (sign_extend:V4SI (match_dup 2)) - (parallel [(const_int 1) (const_int 3)])))))] - "TARGET_REALLY_IWMMXT" - "wmaddsx%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmadd")] -) - -(define_insn "iwmmxt_wmaddux" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (plus:V2SI - (mult:V2SI - (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (parallel [(const_int 1) (const_int 3)])) - (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")) - (parallel [(const_int 0) (const_int 2)]))) - (mult:V2SI - (vec_select:V2SI (zero_extend:V4SI (match_dup 1)) - (parallel [(const_int 0) (const_int 2)])) - (vec_select:V2SI (zero_extend:V4SI (match_dup 2)) - (parallel [(const_int 1) (const_int 3)])))))] - "TARGET_REALLY_IWMMXT" - "wmaddux%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmadd")] -) - -(define_insn "iwmmxt_wmaddsn" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (minus:V2SI - (mult:V2SI - (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (parallel [(const_int 0) (const_int 2)])) - (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")) - (parallel [(const_int 0) (const_int 2)]))) - (mult:V2SI - (vec_select:V2SI (sign_extend:V4SI (match_dup 1)) - (parallel [(const_int 1) (const_int 3)])) - (vec_select:V2SI (sign_extend:V4SI (match_dup 2)) - (parallel [(const_int 1) (const_int 3)])))))] - "TARGET_REALLY_IWMMXT" - "wmaddsn%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmadd")] -) - -(define_insn "iwmmxt_wmaddun" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (minus:V2SI - (mult:V2SI - (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (parallel [(const_int 0) (const_int 2)])) - (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")) - (parallel [(const_int 0) (const_int 2)]))) - (mult:V2SI - (vec_select:V2SI (zero_extend:V4SI (match_dup 1)) - (parallel [(const_int 1) (const_int 3)])) - (vec_select:V2SI (zero_extend:V4SI (match_dup 2)) - (parallel [(const_int 1) (const_int 3)])))))] - "TARGET_REALLY_IWMMXT" - "wmaddun%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmadd")] -) - -(define_insn "iwmmxt_wmulwsm" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (truncate:V2SI - (ashiftrt:V2DI - (mult:V2DI - (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y")) - (sign_extend:V2DI (match_operand:V2SI 2 "register_operand" "y"))) - (const_int 32))))] - "TARGET_REALLY_IWMMXT" - "wmulwsm%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmulw")] -) - -(define_insn "iwmmxt_wmulwum" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (truncate:V2SI - (lshiftrt:V2DI - (mult:V2DI - (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y")) - (zero_extend:V2DI (match_operand:V2SI 2 "register_operand" "y"))) - (const_int 32))))] - "TARGET_REALLY_IWMMXT" - "wmulwum%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmulw")] -) - -(define_insn "iwmmxt_wmulsmr" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (truncate:V4HI - (ashiftrt:V4SI - (plus:V4SI - (mult:V4SI - (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))) - (const_vector:V4SI [(const_int 32768) - (const_int 32768) - (const_int 32768)])) - (const_int 16))))] - "TARGET_REALLY_IWMMXT" - "wmulsmr%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmul")] -) - -(define_insn "iwmmxt_wmulumr" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (truncate:V4HI - (lshiftrt:V4SI - (plus:V4SI - (mult:V4SI - (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))) - (const_vector:V4SI [(const_int 32768) - (const_int 32768) - (const_int 32768) - (const_int 32768)])) - (const_int 16))))] - "TARGET_REALLY_IWMMXT" - "wmulumr%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmul")] -) - -(define_insn "iwmmxt_wmulwsmr" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (truncate:V2SI - (ashiftrt:V2DI - (plus:V2DI - (mult:V2DI - (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y")) - (sign_extend:V2DI (match_operand:V2SI 2 "register_operand" "y"))) - (const_vector:V2DI [(const_int 2147483648) - (const_int 2147483648)])) - (const_int 32))))] - "TARGET_REALLY_IWMMXT" - "wmulwsmr%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmul")] -) - -(define_insn "iwmmxt_wmulwumr" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (truncate:V2SI - (lshiftrt:V2DI - (plus:V2DI - (mult:V2DI - (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y")) - (zero_extend:V2DI (match_operand:V2SI 2 "register_operand" "y"))) - (const_vector:V2DI [(const_int 2147483648) - (const_int 2147483648)])) - (const_int 32))))] - "TARGET_REALLY_IWMMXT" - "wmulwumr%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmulw")] -) - -(define_insn "iwmmxt_wmulwl" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (mult:V2SI - (match_operand:V2SI 1 "register_operand" "y") - (match_operand:V2SI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wmulwl%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmulw")] -) - -(define_insn "iwmmxt_wqmulm" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WQMULM))] - "TARGET_REALLY_IWMMXT" - "wqmulm%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wqmulm")] -) - -(define_insn "iwmmxt_wqmulwm" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "y") - (match_operand:V2SI 2 "register_operand" "y")] UNSPEC_WQMULWM))] - "TARGET_REALLY_IWMMXT" - "wqmulwm%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wqmulwm")] -) - -(define_insn "iwmmxt_wqmulmr" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WQMULMR))] - "TARGET_REALLY_IWMMXT" - "wqmulmr%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wqmulm")] -) - -(define_insn "iwmmxt_wqmulwmr" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "y") - (match_operand:V2SI 2 "register_operand" "y")] UNSPEC_WQMULWMR))] - "TARGET_REALLY_IWMMXT" - "wqmulwmr%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wqmulwm")] -) - -(define_insn "iwmmxt_waddbhusm" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (vec_concat:V8QI - (const_vector:V4QI [(const_int 0) (const_int 0) (const_int 0) (const_int 0)]) - (us_truncate:V4QI - (ss_plus:V4HI - (match_operand:V4HI 1 "register_operand" "y") - (zero_extend:V4HI - (vec_select:V4QI (match_operand:V8QI 2 "register_operand" "y") - (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7)])))))))] - "TARGET_REALLY_IWMMXT" - "waddbhusm%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_waddbhus")] -) - -(define_insn "iwmmxt_waddbhusl" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (vec_concat:V8QI - (us_truncate:V4QI - (ss_plus:V4HI - (match_operand:V4HI 1 "register_operand" "y") - (zero_extend:V4HI - (vec_select:V4QI (match_operand:V8QI 2 "register_operand" "y") - (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)]))))) - (const_vector:V4QI [(const_int 0) (const_int 0) (const_int 0) (const_int 0)])))] - "TARGET_REALLY_IWMMXT" - "waddbhusl%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_waddbhus")] -) - -(define_insn "iwmmxt_wqmiabb" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "0") - (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 0)) - (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 32)) - (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 0)) - (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 32))] UNSPEC_WQMIAxy))] - "TARGET_REALLY_IWMMXT" - "wqmiabb%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wqmiaxy")] -) - -(define_insn "iwmmxt_wqmiabt" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "0") - (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 0)) - (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 32)) - (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 16)) - (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 48))] UNSPEC_WQMIAxy))] - "TARGET_REALLY_IWMMXT" - "wqmiabt%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wqmiaxy")] -) - -(define_insn "iwmmxt_wqmiatb" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "0") - (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 16)) - (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 48)) - (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 0)) - (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 32))] UNSPEC_WQMIAxy))] - "TARGET_REALLY_IWMMXT" - "wqmiatb%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wqmiaxy")] -) - -(define_insn "iwmmxt_wqmiatt" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "0") - (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 16)) - (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 48)) - (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 16)) - (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 48))] UNSPEC_WQMIAxy))] - "TARGET_REALLY_IWMMXT" - "wqmiatt%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wqmiaxy")] -) - -(define_insn "iwmmxt_wqmiabbn" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "0") - (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 0)) - (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 32)) - (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 0)) - (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 32))] UNSPEC_WQMIAxyn))] - "TARGET_REALLY_IWMMXT" - "wqmiabbn%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wqmiaxy")] -) - -(define_insn "iwmmxt_wqmiabtn" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "0") - (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 0)) - (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 32)) - (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 16)) - (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 48))] UNSPEC_WQMIAxyn))] - "TARGET_REALLY_IWMMXT" - "wqmiabtn%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wqmiaxy")] -) - -(define_insn "iwmmxt_wqmiatbn" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "0") - (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 16)) - (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 48)) - (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 0)) - (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 32))] UNSPEC_WQMIAxyn))] - "TARGET_REALLY_IWMMXT" - "wqmiatbn%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wqmiaxy")] -) - -(define_insn "iwmmxt_wqmiattn" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "0") - (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 16)) - (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 48)) - (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 16)) - (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 48))] UNSPEC_WQMIAxyn))] - "TARGET_REALLY_IWMMXT" - "wqmiattn%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wqmiaxy")] -) - -(define_insn "iwmmxt_wmiabb" - [(set (match_operand:DI 0 "register_operand" "=y") - (plus:DI (match_operand:DI 1 "register_operand" "0") - (plus:DI - (mult:DI - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 2 "register_operand" "y") - (parallel [(const_int 0)]))) - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 3 "register_operand" "y") - (parallel [(const_int 0)])))) - (mult:DI - (sign_extend:DI - (vec_select:HI (match_dup 2) - (parallel [(const_int 2)]))) - (sign_extend:DI - (vec_select:HI (match_dup 3) - (parallel [(const_int 2)])))))))] - "TARGET_REALLY_IWMMXT" - "wmiabb%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiaxy")] -) - -(define_insn "iwmmxt_wmiabt" - [(set (match_operand:DI 0 "register_operand" "=y") - (plus:DI (match_operand:DI 1 "register_operand" "0") - (plus:DI - (mult:DI - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 2 "register_operand" "y") - (parallel [(const_int 0)]))) - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 3 "register_operand" "y") - (parallel [(const_int 1)])))) - (mult:DI - (sign_extend:DI - (vec_select:HI (match_dup 2) - (parallel [(const_int 2)]))) - (sign_extend:DI - (vec_select:HI (match_dup 3) - (parallel [(const_int 3)])))))))] - "TARGET_REALLY_IWMMXT" - "wmiabt%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiaxy")] -) - -(define_insn "iwmmxt_wmiatb" - [(set (match_operand:DI 0 "register_operand" "=y") - (plus:DI (match_operand:DI 1 "register_operand" "0") - (plus:DI - (mult:DI - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 2 "register_operand" "y") - (parallel [(const_int 1)]))) - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 3 "register_operand" "y") - (parallel [(const_int 0)])))) - (mult:DI - (sign_extend:DI - (vec_select:HI (match_dup 2) - (parallel [(const_int 3)]))) - (sign_extend:DI - (vec_select:HI (match_dup 3) - (parallel [(const_int 2)])))))))] - "TARGET_REALLY_IWMMXT" - "wmiatb%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiaxy")] -) - -(define_insn "iwmmxt_wmiatt" - [(set (match_operand:DI 0 "register_operand" "=y") - (plus:DI (match_operand:DI 1 "register_operand" "0") - (plus:DI - (mult:DI - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 2 "register_operand" "y") - (parallel [(const_int 1)]))) - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 3 "register_operand" "y") - (parallel [(const_int 1)])))) - (mult:DI - (sign_extend:DI - (vec_select:HI (match_dup 2) - (parallel [(const_int 3)]))) - (sign_extend:DI - (vec_select:HI (match_dup 3) - (parallel [(const_int 3)])))))))] - "TARGET_REALLY_IWMMXT" - "wmiatt%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiaxy")] -) - -(define_insn "iwmmxt_wmiabbn" - [(set (match_operand:DI 0 "register_operand" "=y") - (minus:DI (match_operand:DI 1 "register_operand" "0") - (plus:DI - (mult:DI - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 2 "register_operand" "y") - (parallel [(const_int 0)]))) - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 3 "register_operand" "y") - (parallel [(const_int 0)])))) - (mult:DI - (sign_extend:DI - (vec_select:HI (match_dup 2) - (parallel [(const_int 2)]))) - (sign_extend:DI - (vec_select:HI (match_dup 3) - (parallel [(const_int 2)])))))))] - "TARGET_REALLY_IWMMXT" - "wmiabbn%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiaxy")] -) - -(define_insn "iwmmxt_wmiabtn" - [(set (match_operand:DI 0 "register_operand" "=y") - (minus:DI (match_operand:DI 1 "register_operand" "0") - (plus:DI - (mult:DI - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 2 "register_operand" "y") - (parallel [(const_int 0)]))) - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 3 "register_operand" "y") - (parallel [(const_int 1)])))) - (mult:DI - (sign_extend:DI - (vec_select:HI (match_dup 2) - (parallel [(const_int 2)]))) - (sign_extend:DI - (vec_select:HI (match_dup 3) - (parallel [(const_int 3)])))))))] - "TARGET_REALLY_IWMMXT" - "wmiabtn%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiaxy")] -) - -(define_insn "iwmmxt_wmiatbn" - [(set (match_operand:DI 0 "register_operand" "=y") - (minus:DI (match_operand:DI 1 "register_operand" "0") - (plus:DI - (mult:DI - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 2 "register_operand" "y") - (parallel [(const_int 1)]))) - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 3 "register_operand" "y") - (parallel [(const_int 0)])))) - (mult:DI - (sign_extend:DI - (vec_select:HI (match_dup 2) - (parallel [(const_int 3)]))) - (sign_extend:DI - (vec_select:HI (match_dup 3) - (parallel [(const_int 2)])))))))] - "TARGET_REALLY_IWMMXT" - "wmiatbn%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiaxy")] -) - -(define_insn "iwmmxt_wmiattn" - [(set (match_operand:DI 0 "register_operand" "=y") - (minus:DI (match_operand:DI 1 "register_operand" "0") - (plus:DI - (mult:DI - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 2 "register_operand" "y") - (parallel [(const_int 1)]))) - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 3 "register_operand" "y") - (parallel [(const_int 1)])))) - (mult:DI - (sign_extend:DI - (vec_select:HI (match_dup 2) - (parallel [(const_int 3)]))) - (sign_extend:DI - (vec_select:HI (match_dup 3) - (parallel [(const_int 3)])))))))] - "TARGET_REALLY_IWMMXT" - "wmiattn%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiaxy")] -) - -(define_insn "iwmmxt_wmiawbb" - [(set (match_operand:DI 0 "register_operand" "=y") - (plus:DI - (match_operand:DI 1 "register_operand" "0") - (mult:DI - (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 0)]))) - (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 0)]))))))] - "TARGET_REALLY_IWMMXT" - "wmiawbb%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiawxy")] -) - -(define_insn "iwmmxt_wmiawbt" - [(set (match_operand:DI 0 "register_operand" "=y") - (plus:DI - (match_operand:DI 1 "register_operand" "0") - (mult:DI - (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 0)]))) - (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 1)]))))))] - "TARGET_REALLY_IWMMXT" - "wmiawbt%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiawxy")] -) - -(define_insn "iwmmxt_wmiawtb" - [(set (match_operand:DI 0 "register_operand" "=y") - (plus:DI - (match_operand:DI 1 "register_operand" "0") - (mult:DI - (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 1)]))) - (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 0)]))))))] - "TARGET_REALLY_IWMMXT" - "wmiawtb%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiawxy")] -) - -(define_insn "iwmmxt_wmiawtt" -[(set (match_operand:DI 0 "register_operand" "=y") - (plus:DI - (match_operand:DI 1 "register_operand" "0") - (mult:DI - (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 1)]))) - (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 1)]))))))] - "TARGET_REALLY_IWMMXT" - "wmiawtt%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiawxy")] -) - -(define_insn "iwmmxt_wmiawbbn" - [(set (match_operand:DI 0 "register_operand" "=y") - (minus:DI - (match_operand:DI 1 "register_operand" "0") - (mult:DI - (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 0)]))) - (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 0)]))))))] - "TARGET_REALLY_IWMMXT" - "wmiawbbn%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiawxy")] -) - -(define_insn "iwmmxt_wmiawbtn" - [(set (match_operand:DI 0 "register_operand" "=y") - (minus:DI - (match_operand:DI 1 "register_operand" "0") - (mult:DI - (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 0)]))) - (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 1)]))))))] - "TARGET_REALLY_IWMMXT" - "wmiawbtn%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiawxy")] -) - -(define_insn "iwmmxt_wmiawtbn" - [(set (match_operand:DI 0 "register_operand" "=y") - (minus:DI - (match_operand:DI 1 "register_operand" "0") - (mult:DI - (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 1)]))) - (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 0)]))))))] - "TARGET_REALLY_IWMMXT" - "wmiawtbn%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiawxy")] -) - -(define_insn "iwmmxt_wmiawttn" - [(set (match_operand:DI 0 "register_operand" "=y") - (minus:DI - (match_operand:DI 1 "register_operand" "0") - (mult:DI - (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 1)]))) - (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 1)]))))))] - "TARGET_REALLY_IWMMXT" - "wmiawttn%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiawxy")] -) - -(define_insn "iwmmxt_wmerge" - [(set (match_operand:DI 0 "register_operand" "=y") - (ior:DI - (ashift:DI - (match_operand:DI 2 "register_operand" "y") - (minus:SI - (const_int 64) - (mult:SI - (match_operand:SI 3 "immediate_operand" "i") - (const_int 8)))) - (lshiftrt:DI - (ashift:DI - (match_operand:DI 1 "register_operand" "y") - (mult:SI - (match_dup 3) - (const_int 8))) - (mult:SI - (match_dup 3) - (const_int 8)))))] - "TARGET_REALLY_IWMMXT" - "wmerge%?\\t%0, %1, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmerge")] -) - -(define_insn "iwmmxt_tandc<mode>3" - [(set (reg:CC CC_REGNUM) - (subreg:CC (unspec:VMMX [(const_int 0)] UNSPEC_TANDC) 0)) - (unspec:CC [(reg:SI 15)] UNSPEC_TANDC)] - "TARGET_REALLY_IWMMXT" - "tandc<MMX_char>%?\\t r15" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tandc")] -) - -(define_insn "iwmmxt_torc<mode>3" - [(set (reg:CC CC_REGNUM) - (subreg:CC (unspec:VMMX [(const_int 0)] UNSPEC_TORC) 0)) - (unspec:CC [(reg:SI 15)] UNSPEC_TORC)] - "TARGET_REALLY_IWMMXT" - "torc<MMX_char>%?\\t r15" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_torc")] -) - -(define_insn "iwmmxt_torvsc<mode>3" - [(set (reg:CC CC_REGNUM) - (subreg:CC (unspec:VMMX [(const_int 0)] UNSPEC_TORVSC) 0)) - (unspec:CC [(reg:SI 15)] UNSPEC_TORVSC)] - "TARGET_REALLY_IWMMXT" - "torvsc<MMX_char>%?\\t r15" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_torvsc")] -) - -(define_insn "iwmmxt_textrc<mode>3" - [(set (reg:CC CC_REGNUM) - (subreg:CC (unspec:VMMX [(const_int 0) - (match_operand:SI 0 "immediate_operand" "i")] UNSPEC_TEXTRC) 0)) - (unspec:CC [(reg:SI 15)] UNSPEC_TEXTRC)] - "TARGET_REALLY_IWMMXT" - "textrc<MMX_char>%?\\t r15, %0" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_textrc")] -) diff --git a/gcc/config/arm/marvell-f-iwmmxt.md b/gcc/config/arm/marvell-f-iwmmxt.md deleted file mode 100644 index c9c7b00..0000000 --- a/gcc/config/arm/marvell-f-iwmmxt.md +++ /dev/null @@ -1,189 +0,0 @@ -;; Marvell WMMX2 pipeline description -;; Copyright (C) 2011-2025 Free Software Foundation, Inc. -;; Written by Marvell, Inc. - -;; This file is part of GCC. - -;; GCC is free software; you can redistribute it and/or modify it -;; under the terms of the GNU General Public License as published -;; by the Free Software Foundation; either version 3, or (at your -;; option) any later version. - -;; GCC is distributed in the hope that it will be useful, but WITHOUT -;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -;; License for more details. - -;; You should have received a copy of the GNU General Public License -;; along with GCC; see the file COPYING3. If not see -;; <http://www.gnu.org/licenses/>. - - -(define_automaton "marvell_f_iwmmxt") - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; Pipelines -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -;; This is a 7-stage pipelines: -;; -;; MD | MI | ME1 | ME2 | ME3 | ME4 | MW -;; -;; There are various bypasses modelled to a greater or lesser extent. -;; -;; Latencies in this file correspond to the number of cycles after -;; the issue stage that it takes for the result of the instruction to -;; be computed, or for its side-effects to occur. - -(define_cpu_unit "mf_iwmmxt_MD" "marvell_f_iwmmxt") -(define_cpu_unit "mf_iwmmxt_MI" "marvell_f_iwmmxt") -(define_cpu_unit "mf_iwmmxt_ME1" "marvell_f_iwmmxt") -(define_cpu_unit "mf_iwmmxt_ME2" "marvell_f_iwmmxt") -(define_cpu_unit "mf_iwmmxt_ME3" "marvell_f_iwmmxt") -(define_cpu_unit "mf_iwmmxt_ME4" "marvell_f_iwmmxt") -(define_cpu_unit "mf_iwmmxt_MW" "marvell_f_iwmmxt") - -(define_reservation "mf_iwmmxt_ME" - "mf_iwmmxt_ME1,mf_iwmmxt_ME2,mf_iwmmxt_ME3,mf_iwmmxt_ME4" -) - -(define_reservation "mf_iwmmxt_pipeline" - "mf_iwmmxt_MD, mf_iwmmxt_MI, mf_iwmmxt_ME, mf_iwmmxt_MW" -) - -;; An attribute to indicate whether our reservations are applicable. -(define_attr "marvell_f_iwmmxt" "yes,no" - (const (if_then_else (symbol_ref "arm_arch_iwmmxt") - (const_string "yes") (const_string "no")))) - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; instruction classes -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -;; An attribute appended to instructions for classification - -(define_attr "wmmxt_shift" "yes,no" - (if_then_else (eq_attr "type" "wmmx_wror, wmmx_wsll, wmmx_wsra, wmmx_wsrl") - (const_string "yes") (const_string "no")) -) - -(define_attr "wmmxt_pack" "yes,no" - (if_then_else (eq_attr "type" "wmmx_waligni, wmmx_walignr, wmmx_wmerge,\ - wmmx_wpack, wmmx_wshufh, wmmx_wunpckeh,\ - wmmx_wunpckih, wmmx_wunpckel, wmmx_wunpckil") - (const_string "yes") (const_string "no")) -) - -(define_attr "wmmxt_mult_c1" "yes,no" - (if_then_else (eq_attr "type" "wmmx_wmac, wmmx_wmadd, wmmx_wmiaxy,\ - wmmx_wmiawxy, wmmx_wmulw, wmmx_wqmiaxy,\ - wmmx_wqmulwm") - (const_string "yes") (const_string "no")) -) - -(define_attr "wmmxt_mult_c2" "yes,no" - (if_then_else (eq_attr "type" "wmmx_wmul, wmmx_wqmulm") - (const_string "yes") (const_string "no")) -) - -(define_attr "wmmxt_alu_c1" "yes,no" - (if_then_else (eq_attr "type" "wmmx_wabs, wmmx_wabsdiff, wmmx_wand,\ - wmmx_wandn, wmmx_wmov, wmmx_wor, wmmx_wxor") - (const_string "yes") (const_string "no")) -) - -(define_attr "wmmxt_alu_c2" "yes,no" - (if_then_else (eq_attr "type" "wmmx_wacc, wmmx_wadd, wmmx_waddsubhx,\ - wmmx_wavg2, wmmx_wavg4, wmmx_wcmpeq,\ - wmmx_wcmpgt, wmmx_wmax, wmmx_wmin,\ - wmmx_wsub, wmmx_waddbhus, wmmx_wsubaddhx") - (const_string "yes") (const_string "no")) -) - -(define_attr "wmmxt_alu_c3" "yes,no" - (if_then_else (eq_attr "type" "wmmx_wsad") - (const_string "yes") (const_string "no")) -) - -(define_attr "wmmxt_transfer_c1" "yes,no" - (if_then_else (eq_attr "type" "wmmx_tbcst, wmmx_tinsr,\ - wmmx_tmcr, wmmx_tmcrr") - (const_string "yes") (const_string "no")) -) - -(define_attr "wmmxt_transfer_c2" "yes,no" - (if_then_else (eq_attr "type" "wmmx_textrm, wmmx_tmovmsk,\ - wmmx_tmrc, wmmx_tmrrc") - (const_string "yes") (const_string "no")) -) - -(define_attr "wmmxt_transfer_c3" "yes,no" - (if_then_else (eq_attr "type" "wmmx_tmia, wmmx_tmiaph, wmmx_tmiaxy") - (const_string "yes") (const_string "no")) -) - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; Main description -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -(define_insn_reservation "marvell_f_iwmmxt_alu_c1" 1 - (and (eq_attr "marvell_f_iwmmxt" "yes") - (eq_attr "wmmxt_alu_c1" "yes")) - "mf_iwmmxt_pipeline") - -(define_insn_reservation "marvell_f_iwmmxt_pack" 1 - (and (eq_attr "marvell_f_iwmmxt" "yes") - (eq_attr "wmmxt_pack" "yes")) - "mf_iwmmxt_pipeline") - -(define_insn_reservation "marvell_f_iwmmxt_shift" 1 - (and (eq_attr "marvell_f_iwmmxt" "yes") - (eq_attr "wmmxt_shift" "yes")) - "mf_iwmmxt_pipeline") - -(define_insn_reservation "marvell_f_iwmmxt_transfer_c1" 1 - (and (eq_attr "marvell_f_iwmmxt" "yes") - (eq_attr "wmmxt_transfer_c1" "yes")) - "mf_iwmmxt_pipeline") - -(define_insn_reservation "marvell_f_iwmmxt_transfer_c2" 5 - (and (eq_attr "marvell_f_iwmmxt" "yes") - (eq_attr "wmmxt_transfer_c2" "yes")) - "mf_iwmmxt_pipeline") - -(define_insn_reservation "marvell_f_iwmmxt_alu_c2" 2 - (and (eq_attr "marvell_f_iwmmxt" "yes") - (eq_attr "wmmxt_alu_c2" "yes")) - "mf_iwmmxt_pipeline") - -(define_insn_reservation "marvell_f_iwmmxt_alu_c3" 3 - (and (eq_attr "marvell_f_iwmmxt" "yes") - (eq_attr "wmmxt_alu_c3" "yes")) - "mf_iwmmxt_pipeline") - -(define_insn_reservation "marvell_f_iwmmxt_transfer_c3" 4 - (and (eq_attr "marvell_f_iwmmxt" "yes") - (eq_attr "wmmxt_transfer_c3" "yes")) - "mf_iwmmxt_pipeline") - -(define_insn_reservation "marvell_f_iwmmxt_mult_c1" 4 - (and (eq_attr "marvell_f_iwmmxt" "yes") - (eq_attr "wmmxt_mult_c1" "yes")) - "mf_iwmmxt_pipeline") - -;There is a forwarding path from ME3 stage -(define_insn_reservation "marvell_f_iwmmxt_mult_c2" 3 - (and (eq_attr "marvell_f_iwmmxt" "yes") - (eq_attr "wmmxt_mult_c2" "yes")) - "mf_iwmmxt_pipeline") - -(define_insn_reservation "marvell_f_iwmmxt_wstr" 0 - (and (eq_attr "marvell_f_iwmmxt" "yes") - (eq_attr "type" "wmmx_wstr")) - "mf_iwmmxt_pipeline") - -;There is a forwarding path from MW stage -(define_insn_reservation "marvell_f_iwmmxt_wldr" 5 - (and (eq_attr "marvell_f_iwmmxt" "yes") - (eq_attr "type" "wmmx_wldr")) - "mf_iwmmxt_pipeline") diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index 75c06d9..c683ec2 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -806,14 +806,8 @@ ;;------------------------------------------------------------------------- ;; -;; iWMMXt predicates -;; - -(define_predicate "imm_or_reg_operand" - (ior (match_operand 0 "immediate_operand") - (match_operand 0 "register_operand"))) - ;; Neon predicates +;; (define_predicate "const_multiple_of_8_operand" (match_code "const_int") @@ -907,7 +901,8 @@ (define_predicate "mem_noofs_operand" (and (match_code "mem") - (match_code "reg" "0"))) + (match_code "reg" "0") + (match_operand 0 "memory_operand"))) (define_predicate "call_insn_operand" (ior (and (match_code "symbol_ref") diff --git a/gcc/config/arm/t-arm b/gcc/config/arm/t-arm index 641f8f5..670f574 100644 --- a/gcc/config/arm/t-arm +++ b/gcc/config/arm/t-arm @@ -50,11 +50,8 @@ MD_INCLUDES= $(srcdir)/config/arm/arm1020e.md \ $(srcdir)/config/arm/fa726te.md \ $(srcdir)/config/arm/fmp626.md \ $(srcdir)/config/arm/iterators.md \ - $(srcdir)/config/arm/iwmmxt.md \ - $(srcdir)/config/arm/iwmmxt2.md \ $(srcdir)/config/arm/ldmstm.md \ $(srcdir)/config/arm/ldrdstrd.md \ - $(srcdir)/config/arm/marvell-f-iwmmxt.md \ $(srcdir)/config/arm/mve.md \ $(srcdir)/config/arm/neon.md \ $(srcdir)/config/arm/predicates.md \ diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 172c974..019f9d4 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -235,7 +235,7 @@ (define_insn "*thumb2_movsi_insn" [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r,lk*r,m") (match_operand:SI 1 "general_operand" "rk,I,Py,K,j,mi,lk*r"))] - "TARGET_THUMB2 && !TARGET_IWMMXT && !TARGET_HARD_FLOAT + "TARGET_THUMB2 && !TARGET_HARD_FLOAT && ( register_operand (operands[0], SImode) || register_operand (operands[1], SImode))" { diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md index b72c871..e517b91 100644 --- a/gcc/config/arm/types.md +++ b/gcc/config/arm/types.md @@ -184,70 +184,6 @@ ; untyped insn without type information - default, and error, ; case. ; -; The classification below is for instructions used by the Wireless MMX -; Technology. Each attribute value is used to classify an instruction of the -; same name or family. -; -; wmmx_tandc -; wmmx_tbcst -; wmmx_textrc -; wmmx_textrm -; wmmx_tinsr -; wmmx_tmcr -; wmmx_tmcrr -; wmmx_tmia -; wmmx_tmiaph -; wmmx_tmiaxy -; wmmx_tmrc -; wmmx_tmrrc -; wmmx_tmovmsk -; wmmx_torc -; wmmx_torvsc -; wmmx_wabs -; wmmx_wdiff -; wmmx_wacc -; wmmx_wadd -; wmmx_waddbhus -; wmmx_waddsubhx -; wmmx_waligni -; wmmx_walignr -; wmmx_wand -; wmmx_wandn -; wmmx_wavg2 -; wmmx_wavg4 -; wmmx_wcmpeq -; wmmx_wcmpgt -; wmmx_wmac -; wmmx_wmadd -; wmmx_wmax -; wmmx_wmerge -; wmmx_wmiawxy -; wmmx_wmiaxy -; wmmx_wmin -; wmmx_wmov -; wmmx_wmul -; wmmx_wmulw -; wmmx_wldr -; wmmx_wor -; wmmx_wpack -; wmmx_wqmiaxy -; wmmx_wqmulm -; wmmx_wqmulwm -; wmmx_wror -; wmmx_wsad -; wmmx_wshufh -; wmmx_wsll -; wmmx_wsra -; wmmx_wsrl -; wmmx_wstr -; wmmx_wsub -; wmmx_wsubaddhx -; wmmx_wunpckeh -; wmmx_wunpckel -; wmmx_wunpckih -; wmmx_wunpckil -; wmmx_wxor -; ; The classification below is for NEON instructions. If a new neon type is ; added, please ensure this is added to the is_neon_type attribute below too. ; @@ -714,65 +650,6 @@ umull,\ umulls,\ untyped,\ - wmmx_tandc,\ - wmmx_tbcst,\ - wmmx_textrc,\ - wmmx_textrm,\ - wmmx_tinsr,\ - wmmx_tmcr,\ - wmmx_tmcrr,\ - wmmx_tmia,\ - wmmx_tmiaph,\ - wmmx_tmiaxy,\ - wmmx_tmrc,\ - wmmx_tmrrc,\ - wmmx_tmovmsk,\ - wmmx_torc,\ - wmmx_torvsc,\ - wmmx_wabs,\ - wmmx_wabsdiff,\ - wmmx_wacc,\ - wmmx_wadd,\ - wmmx_waddbhus,\ - wmmx_waddsubhx,\ - wmmx_waligni,\ - wmmx_walignr,\ - wmmx_wand,\ - wmmx_wandn,\ - wmmx_wavg2,\ - wmmx_wavg4,\ - wmmx_wcmpeq,\ - wmmx_wcmpgt,\ - wmmx_wmac,\ - wmmx_wmadd,\ - wmmx_wmax,\ - wmmx_wmerge,\ - wmmx_wmiawxy,\ - wmmx_wmiaxy,\ - wmmx_wmin,\ - wmmx_wmov,\ - wmmx_wmul,\ - wmmx_wmulw,\ - wmmx_wldr,\ - wmmx_wor,\ - wmmx_wpack,\ - wmmx_wqmiaxy,\ - wmmx_wqmulm,\ - wmmx_wqmulwm,\ - wmmx_wror,\ - wmmx_wsad,\ - wmmx_wshufh,\ - wmmx_wsll,\ - wmmx_wsra,\ - wmmx_wsrl,\ - wmmx_wstr,\ - wmmx_wsub,\ - wmmx_wsubaddhx,\ - wmmx_wunpckeh,\ - wmmx_wunpckel,\ - wmmx_wunpckih,\ - wmmx_wunpckil,\ - wmmx_wxor,\ \ neon_add,\ neon_add_q,\ diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index a03609d..c1ee972 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -21,7 +21,6 @@ ;; UNSPEC Usage: ;; Note: sin and cos are no-longer used. ;; Unspec enumerators for Neon are defined in neon.md. -;; Unspec enumerators for iwmmxt2 are defined in iwmmxt2.md (define_c_enum "unspec" [ UNSPEC_PUSH_MULT ; `push multiple' operation: @@ -42,17 +41,6 @@ ; and stack frame generation. Operand 0 is the ; register to "use". UNSPEC_CHECK_ARCH ; Set CCs to indicate 26-bit or 32-bit mode. - UNSPEC_WSHUFH ; Used by the intrinsic form of the iWMMXt WSHUFH instruction. - UNSPEC_WACC ; Used by the intrinsic form of the iWMMXt WACC instruction. - UNSPEC_TMOVMSK ; Used by the intrinsic form of the iWMMXt TMOVMSK instruction. - UNSPEC_WSAD ; Used by the intrinsic form of the iWMMXt WSAD instruction. - UNSPEC_WSADZ ; Used by the intrinsic form of the iWMMXt WSADZ instruction. - UNSPEC_WMACS ; Used by the intrinsic form of the iWMMXt WMACS instruction. - UNSPEC_WMACU ; Used by the intrinsic form of the iWMMXt WMACU instruction. - UNSPEC_WMACSZ ; Used by the intrinsic form of the iWMMXt WMACSZ instruction. - UNSPEC_WMACUZ ; Used by the intrinsic form of the iWMMXt WMACUZ instruction. - UNSPEC_CLRDI ; Used by the intrinsic form of the iWMMXt CLRDI instruction. - UNSPEC_WALIGNI ; Used by the intrinsic form of the iWMMXt WALIGN instruction. UNSPEC_TLS ; A symbol that has been treated properly for TLS usage. UNSPEC_PIC_LABEL ; A label used for PIC access that does not appear in the ; instruction stream. @@ -164,18 +152,6 @@ (define_c_enum "unspec" [ - UNSPEC_WADDC ; Used by the intrinsic form of the iWMMXt WADDC instruction. - UNSPEC_WABS ; Used by the intrinsic form of the iWMMXt WABS instruction. - UNSPEC_WQMULWMR ; Used by the intrinsic form of the iWMMXt WQMULWMR instruction. - UNSPEC_WQMULMR ; Used by the intrinsic form of the iWMMXt WQMULMR instruction. - UNSPEC_WQMULWM ; Used by the intrinsic form of the iWMMXt WQMULWM instruction. - UNSPEC_WQMULM ; Used by the intrinsic form of the iWMMXt WQMULM instruction. - UNSPEC_WQMIAxyn ; Used by the intrinsic form of the iWMMXt WMIAxyn instruction. - UNSPEC_WQMIAxy ; Used by the intrinsic form of the iWMMXt WMIAxy instruction. - UNSPEC_TANDC ; Used by the intrinsic form of the iWMMXt TANDC instruction. - UNSPEC_TORC ; Used by the intrinsic form of the iWMMXt TORC instruction. - UNSPEC_TORVSC ; Used by the intrinsic form of the iWMMXt TORVSC instruction. - UNSPEC_TEXTRC ; Used by the intrinsic form of the iWMMXt TEXTRC instruction. UNSPEC_GET_FPSCR_NZCVQC ; Represent fetch of FPSCR_nzcvqc content. ]) @@ -205,12 +181,7 @@ ; a 64-bit object. VUNSPEC_POOL_16 ; `pool-entry(16)'. An entry in the constant pool for ; a 128-bit object. - VUNSPEC_TMRC ; Used by the iWMMXt TMRC instruction. - VUNSPEC_TMCR ; Used by the iWMMXt TMCR instruction. VUNSPEC_ALIGN8 ; 8-byte alignment version of VUNSPEC_ALIGN - VUNSPEC_WCMP_EQ ; Used by the iWMMXt WCMPEQ instructions - VUNSPEC_WCMP_GTU ; Used by the iWMMXt WCMPGTU instructions - VUNSPEC_WCMP_GT ; Used by the iwMMXT WCMPGT instructions VUNSPEC_EH_RETURN ; Use to override the return address for exception ; handling. VUNSPEC_ATOMIC_CAS ; Represent an atomic compare swap. diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index a485d05..061165e 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -1,4 +1,4 @@ -;; Machine Description for shared bits common to IWMMXT and Neon. +;; Machine Description for shared bits common to Neon and MVE. ;; Copyright (C) 2006-2025 Free Software Foundation, Inc. ;; Written by CodeSourcery. ;; @@ -24,7 +24,6 @@ [(set (match_operand:VNIM1 0 "nonimmediate_operand") (match_operand:VNIM1 1 "general_operand"))] "TARGET_NEON - || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode)) || (TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))" { @@ -46,8 +45,7 @@ (define_expand "mov<mode>" [(set (match_operand:VNINOTM1 0 "nonimmediate_operand") (match_operand:VNINOTM1 1 "general_operand"))] - "TARGET_NEON - || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" + "TARGET_NEON" { gcc_checking_assert (aligned_operand (operands[0], <MODE>mode)); gcc_checking_assert (aligned_operand (operands[1], <MODE>mode)); @@ -83,7 +81,7 @@ }) ;; Vector arithmetic. Expanders are blank, then unnamed insns implement -;; patterns separately for Neon, IWMMXT and MVE. +;; patterns separately for Neon and MVE. (define_expand "add<mode>3" [(set (match_operand:VDQ 0 "s_register_operand") @@ -103,10 +101,7 @@ [(set (match_operand:VDQWH 0 "s_register_operand") (mult:VDQWH (match_operand:VDQWH 1 "s_register_operand") (match_operand:VDQWH 2 "s_register_operand")))] - "ARM_HAVE_<MODE>_ARITH - && (!TARGET_REALLY_IWMMXT - || <MODE>mode == V4HImode - || <MODE>mode == V2SImode)" + "ARM_HAVE_<MODE>_ARITH" ) (define_expand "smin<mode>3" @@ -216,13 +211,13 @@ (define_expand "one_cmpl<mode>2" [(set (match_operand:VDQ 0 "s_register_operand") (not:VDQ (match_operand:VDQ 1 "s_register_operand")))] - "ARM_HAVE_<MODE>_ARITH && !TARGET_REALLY_IWMMXT" + "ARM_HAVE_<MODE>_ARITH" ) (define_expand "<absneg_str><mode>2" [(set (match_operand:VDQWH 0 "s_register_operand" "") (ABSNEG:VDQWH (match_operand:VDQWH 1 "s_register_operand" "")))] - "ARM_HAVE_<MODE>_ARITH && !TARGET_REALLY_IWMMXT" + "ARM_HAVE_<MODE>_ARITH" ) (define_expand "cadd<rot><mode>3" @@ -295,8 +290,7 @@ [(set (match_operand:VDQ 0 "nonimmediate_operand") (unspec:VDQ [(match_operand:VDQ 1 "general_operand")] UNSPEC_MISALIGNED_ACCESS))] - "ARM_HAVE_<MODE>_LDST && !BYTES_BIG_ENDIAN - && unaligned_access && !TARGET_REALLY_IWMMXT" + "ARM_HAVE_<MODE>_LDST && !BYTES_BIG_ENDIAN && unaligned_access" { rtx *memloc; bool for_store = false; @@ -373,7 +367,7 @@ (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w,w") (match_operand:VDQIW 2 "imm_lshift_or_reg_neon" "w,Ds")] VSHLQ))] - "ARM_HAVE_<MODE>_ARITH && !TARGET_REALLY_IWMMXT" + "ARM_HAVE_<MODE>_ARITH" "@ <mve_insn>.<supf>%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2 * return neon_output_shift_immediate (\"vshl\", 'i', &operands[2], <MODE>mode, VALID_NEON_QREG_MODE (<MODE>mode), true);" @@ -385,7 +379,7 @@ [(set (match_operand:VDQIW 0 "s_register_operand" "") (ashift:VDQIW (match_operand:VDQIW 1 "s_register_operand" "") (match_operand:VDQIW 2 "imm_lshift_or_reg_neon" "")))] - "ARM_HAVE_<MODE>_ARITH && !TARGET_REALLY_IWMMXT" + "ARM_HAVE_<MODE>_ARITH" { emit_insn (gen_mve_vshlq_u<mode> (operands[0], operands[1], operands[2])); DONE; @@ -398,7 +392,7 @@ [(set (match_operand:VDQIW 0 "s_register_operand") (ashiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand") (match_operand:VDQIW 2 "imm_rshift_or_reg_neon")))] - "ARM_HAVE_<MODE>_ARITH && !TARGET_REALLY_IWMMXT" + "ARM_HAVE_<MODE>_ARITH" { if (s_register_operand (operands[2], <MODE>mode)) { @@ -416,7 +410,7 @@ [(set (match_operand:VDQIW 0 "s_register_operand") (lshiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand") (match_operand:VDQIW 2 "imm_rshift_or_reg_neon")))] - "ARM_HAVE_<MODE>_ARITH && !TARGET_REALLY_IWMMXT" + "ARM_HAVE_<MODE>_ARITH" { if (s_register_operand (operands[2], <MODE>mode)) { @@ -606,8 +600,7 @@ (define_expand "clz<mode>2" [(set (match_operand:VDQIW 0 "s_register_operand") (clz:VDQIW (match_operand:VDQIW 1 "s_register_operand")))] - "ARM_HAVE_<MODE>_ARITH - && !TARGET_REALLY_IWMMXT" + "ARM_HAVE_<MODE>_ARITH" ) (define_expand "vec_init<mode><V_elem_l>" [(match_operand:VDQX 0 "s_register_operand") |