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Diffstat (limited to 'gcc/config/arm/ldmstm.md')
-rw-r--r--gcc/config/arm/ldmstm.md114
1 files changed, 57 insertions, 57 deletions
diff --git a/gcc/config/arm/ldmstm.md b/gcc/config/arm/ldmstm.md
index 303303e..01fbb55 100644
--- a/gcc/config/arm/ldmstm.md
+++ b/gcc/config/arm/ldmstm.md
@@ -36,7 +36,7 @@
(const_int 12))))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"ldm%?\t%5, {%1, %2, %3, %4}"
- [(set_attr "type" "load4")
+ [(set_attr "type" "load_16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
@@ -55,7 +55,7 @@
(const_int 12))))])]
"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
"ldmia\t%5, {%1, %2, %3, %4}"
- [(set_attr "type" "load4")])
+ [(set_attr "type" "load_16")])
(define_insn "*ldm4_ia_update"
[(match_parallel 0 "load_multiple_operation"
@@ -74,7 +74,7 @@
(const_int 12))))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
"ldmia%?\t%5!, {%1, %2, %3, %4}"
- [(set_attr "type" "load4")
+ [(set_attr "type" "load_16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
@@ -95,7 +95,7 @@
(const_int 12))))])]
"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5"
"ldmia\t%5!, {%1, %2, %3, %4}"
- [(set_attr "type" "load4")])
+ [(set_attr "type" "load_16")])
(define_insn "*stm4_"
[(match_parallel 0 "store_multiple_operation"
@@ -109,7 +109,7 @@
(match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"stm%?\t%5, {%1, %2, %3, %4}"
- [(set_attr "type" "store4")
+ [(set_attr "type" "store_16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
@@ -127,7 +127,7 @@
(match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
"stmia%?\t%5!, {%1, %2, %3, %4}"
- [(set_attr "type" "store4")
+ [(set_attr "type" "store_16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
@@ -145,7 +145,7 @@
(match_operand:SI 4 "low_register_operand" ""))])]
"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5"
"stmia\t%5!, {%1, %2, %3, %4}"
- [(set_attr "type" "store4")])
+ [(set_attr "type" "store_16")])
(define_insn "*ldm4_ib"
[(match_parallel 0 "load_multiple_operation"
@@ -163,7 +163,7 @@
(const_int 16))))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 4"
"ldmib%?\t%5, {%1, %2, %3, %4}"
- [(set_attr "type" "load4")
+ [(set_attr "type" "load_16")
(set_attr "predicable" "yes")])
(define_insn "*ldm4_ib_update"
@@ -184,7 +184,7 @@
(const_int 16))))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 5"
"ldmib%?\t%5!, {%1, %2, %3, %4}"
- [(set_attr "type" "load4")
+ [(set_attr "type" "load_16")
(set_attr "predicable" "yes")])
(define_insn "*stm4_ib"
@@ -199,7 +199,7 @@
(match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 4"
"stmib%?\t%5, {%1, %2, %3, %4}"
- [(set_attr "type" "store4")
+ [(set_attr "type" "store_16")
(set_attr "predicable" "yes")])
(define_insn "*stm4_ib_update"
@@ -216,7 +216,7 @@
(match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 5"
"stmib%?\t%5!, {%1, %2, %3, %4}"
- [(set_attr "type" "store4")
+ [(set_attr "type" "store_16")
(set_attr "predicable" "yes")])
(define_insn "*ldm4_da"
@@ -234,7 +234,7 @@
(mem:SI (match_dup 5)))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 4"
"ldmda%?\t%5, {%1, %2, %3, %4}"
- [(set_attr "type" "load4")
+ [(set_attr "type" "load_16")
(set_attr "predicable" "yes")])
(define_insn "*ldm4_da_update"
@@ -254,7 +254,7 @@
(mem:SI (match_dup 5)))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 5"
"ldmda%?\t%5!, {%1, %2, %3, %4}"
- [(set_attr "type" "load4")
+ [(set_attr "type" "load_16")
(set_attr "predicable" "yes")])
(define_insn "*stm4_da"
@@ -269,7 +269,7 @@
(match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 4"
"stmda%?\t%5, {%1, %2, %3, %4}"
- [(set_attr "type" "store4")
+ [(set_attr "type" "store_16")
(set_attr "predicable" "yes")])
(define_insn "*stm4_da_update"
@@ -286,7 +286,7 @@
(match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 5"
"stmda%?\t%5!, {%1, %2, %3, %4}"
- [(set_attr "type" "store4")
+ [(set_attr "type" "store_16")
(set_attr "predicable" "yes")])
(define_insn "*ldm4_db"
@@ -305,7 +305,7 @@
(const_int -4))))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"ldmdb%?\t%5, {%1, %2, %3, %4}"
- [(set_attr "type" "load4")
+ [(set_attr "type" "load_16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
@@ -327,7 +327,7 @@
(const_int -4))))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
"ldmdb%?\t%5!, {%1, %2, %3, %4}"
- [(set_attr "type" "load4")
+ [(set_attr "type" "load_16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
@@ -343,7 +343,7 @@
(match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"stmdb%?\t%5, {%1, %2, %3, %4}"
- [(set_attr "type" "store4")
+ [(set_attr "type" "store_16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
@@ -361,7 +361,7 @@
(match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
"stmdb%?\t%5!, {%1, %2, %3, %4}"
- [(set_attr "type" "store4")
+ [(set_attr "type" "store_16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
@@ -484,7 +484,7 @@
(const_int 8))))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"ldm%?\t%4, {%1, %2, %3}"
- [(set_attr "type" "load3")
+ [(set_attr "type" "load_12")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
@@ -500,7 +500,7 @@
(const_int 8))))])]
"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"
"ldmia\t%4, {%1, %2, %3}"
- [(set_attr "type" "load3")])
+ [(set_attr "type" "load_12")])
(define_insn "*ldm3_ia_update"
[(match_parallel 0 "load_multiple_operation"
@@ -516,7 +516,7 @@
(const_int 8))))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"ldmia%?\t%4!, {%1, %2, %3}"
- [(set_attr "type" "load3")
+ [(set_attr "type" "load_12")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
@@ -534,7 +534,7 @@
(const_int 8))))])]
"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
"ldmia\t%4!, {%1, %2, %3}"
- [(set_attr "type" "load3")])
+ [(set_attr "type" "load_12")])
(define_insn "*stm3_"
[(match_parallel 0 "store_multiple_operation"
@@ -546,7 +546,7 @@
(match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"stm%?\t%4, {%1, %2, %3}"
- [(set_attr "type" "store3")
+ [(set_attr "type" "store_12")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
@@ -562,7 +562,7 @@
(match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"stmia%?\t%4!, {%1, %2, %3}"
- [(set_attr "type" "store3")
+ [(set_attr "type" "store_12")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
@@ -578,7 +578,7 @@
(match_operand:SI 3 "low_register_operand" ""))])]
"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
"stmia\t%4!, {%1, %2, %3}"
- [(set_attr "type" "store3")])
+ [(set_attr "type" "store_12")])
(define_insn "*ldm3_ib"
[(match_parallel 0 "load_multiple_operation"
@@ -593,7 +593,7 @@
(const_int 12))))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 3"
"ldmib%?\t%4, {%1, %2, %3}"
- [(set_attr "type" "load3")
+ [(set_attr "type" "load_12")
(set_attr "predicable" "yes")])
(define_insn "*ldm3_ib_update"
@@ -611,7 +611,7 @@
(const_int 12))))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 4"
"ldmib%?\t%4!, {%1, %2, %3}"
- [(set_attr "type" "load3")
+ [(set_attr "type" "load_12")
(set_attr "predicable" "yes")])
(define_insn "*stm3_ib"
@@ -624,7 +624,7 @@
(match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 3"
"stmib%?\t%4, {%1, %2, %3}"
- [(set_attr "type" "store3")
+ [(set_attr "type" "store_12")
(set_attr "predicable" "yes")])
(define_insn "*stm3_ib_update"
@@ -639,7 +639,7 @@
(match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 4"
"stmib%?\t%4!, {%1, %2, %3}"
- [(set_attr "type" "store3")
+ [(set_attr "type" "store_12")
(set_attr "predicable" "yes")])
(define_insn "*ldm3_da"
@@ -654,7 +654,7 @@
(mem:SI (match_dup 4)))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 3"
"ldmda%?\t%4, {%1, %2, %3}"
- [(set_attr "type" "load3")
+ [(set_attr "type" "load_12")
(set_attr "predicable" "yes")])
(define_insn "*ldm3_da_update"
@@ -671,7 +671,7 @@
(mem:SI (match_dup 4)))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 4"
"ldmda%?\t%4!, {%1, %2, %3}"
- [(set_attr "type" "load3")
+ [(set_attr "type" "load_12")
(set_attr "predicable" "yes")])
(define_insn "*stm3_da"
@@ -684,7 +684,7 @@
(match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 3"
"stmda%?\t%4, {%1, %2, %3}"
- [(set_attr "type" "store3")
+ [(set_attr "type" "store_12")
(set_attr "predicable" "yes")])
(define_insn "*stm3_da_update"
@@ -699,7 +699,7 @@
(match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 4"
"stmda%?\t%4!, {%1, %2, %3}"
- [(set_attr "type" "store3")
+ [(set_attr "type" "store_12")
(set_attr "predicable" "yes")])
(define_insn "*ldm3_db"
@@ -715,7 +715,7 @@
(const_int -4))))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"ldmdb%?\t%4, {%1, %2, %3}"
- [(set_attr "type" "load3")
+ [(set_attr "type" "load_12")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
@@ -734,7 +734,7 @@
(const_int -4))))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"ldmdb%?\t%4!, {%1, %2, %3}"
- [(set_attr "type" "load3")
+ [(set_attr "type" "load_12")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
@@ -748,7 +748,7 @@
(match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"stmdb%?\t%4, {%1, %2, %3}"
- [(set_attr "type" "store3")
+ [(set_attr "type" "store_12")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
@@ -764,7 +764,7 @@
(match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"stmdb%?\t%4!, {%1, %2, %3}"
- [(set_attr "type" "store3")
+ [(set_attr "type" "store_12")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
@@ -870,7 +870,7 @@
(const_int 4))))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
"ldm%?\t%3, {%1, %2}"
- [(set_attr "type" "load2")
+ [(set_attr "type" "load_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
@@ -883,7 +883,7 @@
(const_int 4))))])]
"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 2"
"ldmia\t%3, {%1, %2}"
- [(set_attr "type" "load2")])
+ [(set_attr "type" "load_8")])
(define_insn "*ldm2_ia_update"
[(match_parallel 0 "load_multiple_operation"
@@ -896,7 +896,7 @@
(const_int 4))))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"ldmia%?\t%3!, {%1, %2}"
- [(set_attr "type" "load2")
+ [(set_attr "type" "load_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
@@ -911,7 +911,7 @@
(const_int 4))))])]
"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"
"ldmia\t%3!, {%1, %2}"
- [(set_attr "type" "load2")])
+ [(set_attr "type" "load_8")])
(define_insn "*stm2_"
[(match_parallel 0 "store_multiple_operation"
@@ -921,7 +921,7 @@
(match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
"stm%?\t%3, {%1, %2}"
- [(set_attr "type" "store2")
+ [(set_attr "type" "store_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
@@ -935,7 +935,7 @@
(match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"stmia%?\t%3!, {%1, %2}"
- [(set_attr "type" "store2")
+ [(set_attr "type" "store_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
@@ -949,7 +949,7 @@
(match_operand:SI 2 "low_register_operand" ""))])]
"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"
"stmia\t%3!, {%1, %2}"
- [(set_attr "type" "store2")])
+ [(set_attr "type" "store_8")])
(define_insn "*ldm2_ib"
[(match_parallel 0 "load_multiple_operation"
@@ -961,7 +961,7 @@
(const_int 8))))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 2"
"ldmib%?\t%3, {%1, %2}"
- [(set_attr "type" "load2")
+ [(set_attr "type" "load_8")
(set_attr "predicable" "yes")])
(define_insn "*ldm2_ib_update"
@@ -976,7 +976,7 @@
(const_int 8))))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 3"
"ldmib%?\t%3!, {%1, %2}"
- [(set_attr "type" "load2")
+ [(set_attr "type" "load_8")
(set_attr "predicable" "yes")])
(define_insn "*stm2_ib"
@@ -987,7 +987,7 @@
(match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 2"
"stmib%?\t%3, {%1, %2}"
- [(set_attr "type" "store2")
+ [(set_attr "type" "store_8")
(set_attr "predicable" "yes")])
(define_insn "*stm2_ib_update"
@@ -1000,7 +1000,7 @@
(match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 3"
"stmib%?\t%3!, {%1, %2}"
- [(set_attr "type" "store2")
+ [(set_attr "type" "store_8")
(set_attr "predicable" "yes")])
(define_insn "*ldm2_da"
@@ -1012,7 +1012,7 @@
(mem:SI (match_dup 3)))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 2"
"ldmda%?\t%3, {%1, %2}"
- [(set_attr "type" "load2")
+ [(set_attr "type" "load_8")
(set_attr "predicable" "yes")])
(define_insn "*ldm2_da_update"
@@ -1026,7 +1026,7 @@
(mem:SI (match_dup 3)))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 3"
"ldmda%?\t%3!, {%1, %2}"
- [(set_attr "type" "load2")
+ [(set_attr "type" "load_8")
(set_attr "predicable" "yes")])
(define_insn "*stm2_da"
@@ -1037,7 +1037,7 @@
(match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 2"
"stmda%?\t%3, {%1, %2}"
- [(set_attr "type" "store2")
+ [(set_attr "type" "store_8")
(set_attr "predicable" "yes")])
(define_insn "*stm2_da_update"
@@ -1050,7 +1050,7 @@
(match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 3"
"stmda%?\t%3!, {%1, %2}"
- [(set_attr "type" "store2")
+ [(set_attr "type" "store_8")
(set_attr "predicable" "yes")])
(define_insn "*ldm2_db"
@@ -1063,7 +1063,7 @@
(const_int -4))))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
"ldmdb%?\t%3, {%1, %2}"
- [(set_attr "type" "load2")
+ [(set_attr "type" "load_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
@@ -1079,7 +1079,7 @@
(const_int -4))))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"ldmdb%?\t%3!, {%1, %2}"
- [(set_attr "type" "load2")
+ [(set_attr "type" "load_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
@@ -1091,7 +1091,7 @@
(match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
"stmdb%?\t%3, {%1, %2}"
- [(set_attr "type" "store2")
+ [(set_attr "type" "store_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
@@ -1105,7 +1105,7 @@
(match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"stmdb%?\t%3!, {%1, %2}"
- [(set_attr "type" "store2")
+ [(set_attr "type" "store_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
generated by cgit v1.1 at 2025-01-15 21:21:46 +0000