diff options
Diffstat (limited to 'gcc/config/arc/fpx.md')
| -rw-r--r-- | gcc/config/arc/fpx.md | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/gcc/config/arc/fpx.md b/gcc/config/arc/fpx.md index 231b809..1637981 100644 --- a/gcc/config/arc/fpx.md +++ b/gcc/config/arc/fpx.md @@ -151,7 +151,7 @@ ;; op0_reg = D1_reg.low (define_insn "*lr_double_lower" [(set (match_operand:SI 0 "register_operand" "=r") - (unspec_volatile:SI [(match_operand:DF 1 "arc_double_register_operand" "D")] VUNSPEC_LR ))] + (unspec_volatile:SI [(match_operand:DF 1 "arc_double_register_operand" "D")] VUNSPEC_ARC_LR ))] "TARGET_DPFP && !TARGET_DPFP_DISABLE_LRSR" "lr %0, [%1l] ; *lr_double_lower" [(set_attr "length" "8") @@ -160,7 +160,8 @@ (define_insn "*lr_double_higher" [(set (match_operand:SI 0 "register_operand" "=r") - (unspec_volatile:SI [(match_operand:DF 1 "arc_double_register_operand" "D")] VUNSPEC_LR_HIGH ))] + (unspec_volatile:SI [(match_operand:DF 1 "arc_double_register_operand" "D")] + VUNSPEC_ARC_LR_HIGH ))] "TARGET_DPFP && !TARGET_DPFP_DISABLE_LRSR" "lr %0, [%1h] ; *lr_double_higher" [(set_attr "length" "8") @@ -174,7 +175,7 @@ (match_operand:DF 1 "arc_double_register_operand" "D") (match_operand:SI 2 "shouldbe_register_operand" "r") ; r1 (match_operand:SI 3 "shouldbe_register_operand" "r") ; r0 - ] VUNSPEC_DEXCL )) + ] VUNSPEC_ARC_DEXCL )) ] "TARGET_DPFP" "dexcl%F1 %0, %2, %3" @@ -188,7 +189,7 @@ (match_operand:DF 0 "arc_double_register_operand" "D") (match_operand:SI 1 "shouldbe_register_operand" "r") ; r1 (match_operand:SI 2 "shouldbe_register_operand" "r") ; r0 - ] VUNSPEC_DEXCL_NORES ) + ] VUNSPEC_ARC_DEXCL_NORES ) ] "TARGET_DPFP" "dexcl%F0 0, %1, %2" @@ -199,7 +200,7 @@ ;; dexcl a,b,c pattern generated by the peephole2 above (define_insn "*dexcl_3op_peep2_insn_lr" [(parallel [(set (match_operand:SI 0 "register_operand" "=r") - (unspec_volatile:SI [(match_operand:DF 1 "arc_double_register_operand" "=D")] VUNSPEC_LR )) + (unspec_volatile:SI [(match_operand:DF 1 "arc_double_register_operand" "=D")] VUNSPEC_ARC_LR )) (set (match_dup 1) (match_operand:DF 2 "register_operand" "r"))] ) ] @@ -413,7 +414,7 @@ ;; (parallel [ ;; ;; (set (subreg:SI (match_dup 5) 0) ;; (set (match_dup 7) -;; (unspec_volatile [(match_dup 0)] VUNSPEC_LR )) +;; (unspec_volatile [(match_dup 0)] VUNSPEC_ARC_LR )) ;; (set (match_dup 0) (match_dup 6))] ;; ) ;; ] @@ -472,7 +473,7 @@ (parallel [ ;; (set (subreg:SI (match_dup 7) 0) (set (match_dup 9) - (unspec_volatile:SI [(match_dup 0)] VUNSPEC_LR )) + (unspec_volatile:SI [(match_dup 0)] VUNSPEC_ARC_LR )) (set (match_dup 0) (match_dup 8))] ) ] @@ -522,7 +523,7 @@ ;; (match_dup 3)]))]) ;; ; (set (subreg:SI (match_dup 5) 0) ;; (set (match_dup 6) -;; (unspec_volatile [(match_dup 0)] VUNSPEC_LR )) +;; (unspec_volatile [(match_dup 0)] VUNSPEC_ARC_LR )) ;; ] ;; "operands[6] = simplify_gen_subreg(SImode,operands[5],DFmode,0);" ;; ) @@ -572,7 +573,7 @@ (match_dup 3)]))]) ; (set (subreg:SI (match_dup 7) 0) (set (match_dup 8) - (unspec_volatile:SI [(match_dup 0)] VUNSPEC_LR )) + (unspec_volatile:SI [(match_dup 0)] VUNSPEC_ARC_LR )) ] "operands[8] = simplify_gen_subreg(SImode,operands[7],DFmode,0);" ) |