1 files changed, 52 insertions, 22 deletions

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 53ca039..82037a3 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -215,7 +215,7 @@ static const std::unordered_map<std::string, riscv_ext_info_t> riscv_ext_infos
 };
 
 static const riscv_ext_info_t &
-get_riscv_ext_info (const std::string &ext)
+get_riscv_ext_info (const char * ext)
 {
   auto itr = riscv_ext_infos.find (ext);
   if (itr == riscv_ext_infos.end ())
@@ -290,20 +290,36 @@ static const riscv_profiles riscv_profiles_table[] =
   /* RVA23 contains all mandatory base ISA for RVA22U64 and the new extension
      'v,zihintntl,zvfhmin,zvbb,zvkt,zicond,zimop,zcmop,zfa,zawrs' as mandatory
      extensions.  */
-  {"rva23u64", "rv64imafdcv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
+  {"rva23u64", "rv64imafdcbv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
    "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
    "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb"
-   "_zfa_zawrs"},
+   "_zfa_zawrs_supm"},
+
+  /* RVA23S contains all mandatory base ISA for RVA23U64 and the privileged
+     extensions as mandatory extensions.  */
+  {"rva23s64", "rv64imafdcbv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+   "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb"
+   "_zfa_zawrs_svbare_svade_ssccptr_sstvecd_sstvala_sscounterenw_svpbmt"
+   "_svinval_svnapot_sstc_sscofpmf_ssnpm_ssu64xl_sha_supm"
+  },
 
   /* RVB23 contains all mandatory base ISA for RVA22U64 and the new extension
      'zihintntl,zicond,zimop,zcmop,zfa,zawrs' as mandatory
      extensions.  */
-  {"rvb23u64", "rv64imafdc_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
+  {"rvb23u64", "rv64imafdcb_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
    "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
    "_zicboz_zfhmin_zkt_zihintntl_zicond_zimop_zcmop_zcb"
    "_zfa_zawrs"},
 
-  /* Currently we do not define S/M mode Profiles in gcc part.  */
+  /* RVB23S contains all mandatory base ISA for RVB23U64 and the privileged
+     extensions as mandatory extensions.  */
+  {"rvb23s64", "rv64imafdcb_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+   "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb"
+   "_zfa_zawrs_svbare_svade_ssccptr_sstvecd_sstvala_sscounterenw_svpbmt"
+   "_svinval_svnapot_sstc_sscofpmf_ssu64xl_supm"
+  },
 
   /* Terminate the list.  */
   {NULL, NULL}
@@ -980,8 +996,9 @@ riscv_subset_list::parse_base_ext (const char *p)
     }
   else
     {
-      error_at (m_loc, "%<-march=%s%>: ISA string must begin with rv32, rv64 "
-		"or Profiles", m_arch);
+      error_at (m_loc, "%<-march=%s%>: ISA string must begin with rv32, rv64,"
+		" a supported RVA profile or refer to a supported CPU",
+		m_arch);
       return NULL;
     }
 
@@ -1112,7 +1129,7 @@ riscv_subset_list::check_implied_ext ()
   for (itr = m_head; itr != NULL; itr = itr->next)
     {
       auto &ext = *itr;
-      auto &ext_info = get_riscv_ext_info (ext.name);
+      auto &ext_info = get_riscv_ext_info (ext.name.c_str ());
       for (auto &implied_ext : ext_info.implied_exts ())
 	{
 	  if (!implied_ext.match (this))
@@ -1128,8 +1145,10 @@ riscv_subset_list::check_implied_ext ()
 void
 riscv_subset_list::handle_combine_ext ()
 {
-  for (const auto &[ext_name, ext_info] : riscv_ext_infos)
+  for (const auto &pair : riscv_ext_infos)
     {
+      const std::string &ext_name = pair.first;
+      auto &ext_info = pair.second;
       bool is_combined = true;
       /* Skip if this extension don't need to combine.  */
       if (!ext_info.need_combine_p ())
@@ -1557,20 +1576,27 @@ riscv_set_arch_by_subset_list (riscv_subset_list *subset_list,
   if (opts)
     {
       /* Clean up target flags before we set.  */
-      for (const auto &[ext_name, ext_info] : riscv_ext_infos)
-	ext_info.clean_opts (opts);
+      for (const auto &pair : riscv_ext_infos)
+	{
+	  auto &ext_info = pair.second;
+	  ext_info.clean_opts (opts);
+	}
 
       if (subset_list->xlen () == 32)
 	opts->x_riscv_isa_flags &= ~MASK_64BIT;
       else if (subset_list->xlen () == 64)
 	opts->x_riscv_isa_flags |= MASK_64BIT;
 
-      for (const auto &[ext_name, ext_info] : riscv_ext_infos)
-	if (subset_list->lookup (ext_name.c_str ()))
-	  {
-	    /* Set the extension flag.  */
-	    ext_info.set_opts (opts);
-	  }
+      for (const auto &pair : riscv_ext_infos)
+	{
+	  const std::string &ext_name = pair.first;
+	  auto &ext_info = pair.second;
+	  if (subset_list->lookup (ext_name.c_str ()))
+	    {
+	      /* Set the extension flag.  */
+	      ext_info.set_opts (opts);
+	    }
+	}
     }
 }
 
@@ -1708,7 +1734,8 @@ riscv_handle_option (struct gcc_options *opts,
   switch (decoded->opt_index)
     {
     case OPT_march_:
-      riscv_parse_arch_string (decoded->arg, opts, loc);
+      if (riscv_find_cpu (decoded->arg) == NULL)
+	riscv_parse_arch_string (decoded->arg, opts, loc);
       return true;
 
     case OPT_mcpu_:
@@ -1725,15 +1752,18 @@ riscv_handle_option (struct gcc_options *opts,
 /* Expand arch string with implied extensions.  */
 
 const char *
-riscv_expand_arch (int argc ATTRIBUTE_UNUSED,
+riscv_expand_arch (int argc,
 		   const char **argv)
 {
   gcc_assert (argc == 1);
   location_t loc = UNKNOWN_LOCATION;
-  riscv_parse_arch_string (argv[0], NULL, loc);
+  /* Try to interpret the arch as CPU first.  */
+  const char *arch_str = riscv_expand_arch_from_cpu (argc, argv);
+  if (!strlen (arch_str))
+    riscv_parse_arch_string (argv[0], NULL, loc);
   const std::string arch = riscv_arch_str (false);
-  if (arch.length())
-    return xasprintf ("-march=%s", arch.c_str());
+  if (arch.length ())
+    return xasprintf ("-march=%s", arch.c_str ());
   else
     return "";
 }