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Diffstat (limited to 'gcc/ChangeLog')
| -rw-r--r-- | gcc/ChangeLog | 4160 |
1 files changed, 4159 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index eebaa03..d4ef4f9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,4161 @@ +2025-12-09 John Ericson <git@JohnEricson.me> + + * Makefile.in: No longer include TARGET_SYSTEM_ROOT in + libgcc.mvars. + +2025-12-09 John Ericson <git@JohnEricson.me> + + * Makefile.in:: Remove NO_PIE_CFLAGS logic, since it is now in + libgcc. + * configure: Regenerate. + * configure.ac: Remove the enable_default_pie substitution, since + libgcc now has its own logic. + +2025-12-09 Robin Dapp <rdapp@ventanamicro.com> + + PR tree-optimization/123074 + * tree-vect-loop.cc: Reset LOOP_VINFO_USING_SELECT_VL_P. + +2025-12-09 Pan Li <pan2.li@intel.com> + + * config/riscv/predicates.md: Append operator lt to + the comparison_swappable_operator. + * config/riscv/riscv-v.cc (get_swapped_cmp_rtx_code): Add + swappable operator lt handing. + +2025-12-09 Richard Biener <rguenther@suse.de> + + PR target/121230 + * config/i386/i386.cc (ix86_vector_costs::add_stmt_cost): + With FP mode and 387 math cost spill/reload. + +2025-12-09 Robin Dapp <rdapp@ventanamicro.com> + + * config/riscv/riscv.opt.urls: Regenerate. + +2025-12-09 Andrew Stubbs <ams@baylibre.com> + + * config/gcn/gcn.cc (gcn_init_cumulative_args): Only warn once. + Use "required" instead of "enabled" in the warning. + * config/gcn/mkoffload.cc (process_asm): Warn, don't error. + Use "required" instead of "on" in the warning. + +2025-12-09 Robin Dapp <rdapp@ventanamicro.com> + + PR tree-optimization/122635 + * gimple-fold.cc (enum mask_load_store_state): New enum. + (gimple_fold_partial_load_store_mem_ref): Only fold + "all active" loads/stores. + (partial_load_store_mask_state): New function to compute mask + state. + (gimple_fold_partial_load): Remove. + (gimple_fold_partial_load_store): New function. + (gimple_fold_partial_store): Remove. + (gimple_fold_call): Use new function. + +2025-12-09 Robin Dapp <rdapp@ventanamicro.com> + + * config/rs6000/predicates.md (lxvl_else_operand): New + predicate. + * config/rs6000/vsx.md: Add else operand. + * config/s390/predicates.md (vll_else_operand): New predicate. + * config/s390/vector.md: Add else operand. + * doc/md.texi: Document else operand. + * internal-fn.cc (internal_fn_len_index): Adjust IFN_LEN_LOAD. + (internal_fn_else_index): Add IFN_LEN_LOAD. + * optabs-tree.cc (target_supports_len_load_store_p): Get else + value for len_load. + * tree-vect-stmts.cc (vectorizable_load): Pun the else value + type. + +2025-12-09 Robin Dapp <rdapp@ventanamicro.com> + + * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::handle_max_vect): + New parser entry. + (riscv_target_attr_parser::update_settings): Set max-vect + option. + (riscv_process_one_target_attr): Change null-arg handling. + * config/riscv/riscv.cc (riscv_override_options_internal): Set + max-vect option. + * config/riscv/riscv.opt: Add -mmax-vectorization option. + * doc/extend.texi: Document new option. + * doc/invoke.texi: Ditto. + +2025-12-09 Robin Dapp <rdapp@ventanamicro.com> + + PR target/123022 + * config/riscv/vector.md: Add mode_idx attribute. + +2025-12-09 Robin Dapp <rdapp@ventanamicro.com> + + PR target/115325 + * config/riscv/riscv-c.cc (riscv_pragma_target_parse): New + function. + (riscv_register_pragmas): Register riscv_pragma_target_parse. + * config/riscv/riscv-protos.h (riscv_process_target_attr_for_pragma): + Declare. + (riscv_reset_previous_fndecl): Ditto. + * config/riscv/riscv-target-attr.cc (riscv_process_target_attr_for_pragma): + New function. + * config/riscv/riscv.cc (riscv_reset_previous_fndecl): Reset. + (riscv_option_save): New function. + (riscv_option_print): Ditto. + (riscv_get_interrupt_type): Adjust docs. + (TARGET_OPTION_SAVE): Implement. + (TARGET_OPTION_PRINT): Ditto. + * doc/extend.texi: Document that riscv can do target pragams. + +2025-12-09 Robin Dapp <rdapp@ventanamicro.com> + + * config/riscv/autovec.md (reduc_sbool_and_scal_<mode>): New + expander. + (reduc_sbool_ior_scal_<mode>): Ditto. + (reduc_sbool_xor_scal_<mode>): Ditto. + * config/riscv/riscv-protos.h (expand_mask_reduction): Declare. + * config/riscv/riscv-v.cc (expand_mask_reduction): New function. + +2025-12-09 Richard Biener <rguenther@suse.de> + + PR target/123027 + * config/i386/i386-expand.cc (ix86_expand_sse_fp_minmax): + With !HONOR_NANS we can handle LE by swapping and inverting. + +2025-12-08 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR tree-optimization/46555 + * tree-cfgcleanup.cc (execute_cleanup_cfg_post_optimizing): + Don't set todo to include cleanupcfg; do it manually. + Call make_forwarders_with_degenerate_phis if optimizing. + +2025-12-08 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * tree-cfg.cc (make_forwarders_with_degenerate_phis): Add debug + dump. + +2025-12-08 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * tree-ssa-dce.cc (sort_phi_args): Move to tree-cfg.cc. + (make_forwarders_with_degenerate_phis): Move to tree-cfg.cc. + (perform_tree_ssa_dce): Update for the updated return type + of make_forwarders_with_degenerate_phis. + * tree-cfg.cc (sort_phi_args): Moved from tree-ssa-dce.cc. + (make_forwarders_with_degenerate_phis): Moved from tree-ssa-dce.cc. + Update return type to bool and return true if an edge was split. + * tree-cfg.h (make_forwarders_with_degenerate_phis): New decl. + +2025-12-08 Eric Botcazou <ebotcazou@adacore.com> + + PR target/80881 + * config/mingw/winnt.cc (mingw_pe_unique_section): Put two dollar + signs for TLS sections after the prefix. + (mingw_pe_asm_named_section): Deal with all TLS sections uniformly. + +2025-12-08 Ezra Sitorus <Ezra.Sitorus@arm.com> + + * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add C1-Nano, + C1-Pro, C1-Premium and C1-Ultra. + * config/aarch64/aarch64-tune.md: Regenerate. + * doc/invoke.texi: Document C1 cores. + +2025-12-08 Richard Biener <rguenther@suse.de> + + PR tree-optimization/123040 + * tree-ssa-sccvn.cc (vn_nary_build_or_lookup_1): Only insert + nary results. + +2025-12-08 Josef Melcr <josef.melcr@suse.com> + + PR ipa/122798 + * cgraph.cc (cgraph_edge::redirect_callee): Use + iterate_referring instead of referred_to_p. + * cgraphclones.cc (set_new_clone_decl_and_node_flags): Set local + to true iff the node does not have its address taken. + +2025-12-08 Richard Biener <rguenther@suse.de> + + PR tree-optimization/123038 + * tree-vect-patterns.cc (vect_recog_ctz_ffs_pattern): Reject + pattern for reductions when the call argument is used multiple + times. + +2025-12-08 Tamar Christina <tamar.christina@arm.com> + + PR target/123026 + * config/aarch64/aarch64-simd.md (reduc_sbool_ior_scal_<mode>, + reduc_sbool_and_scal_<mode>): Fix tmp operands[1] override. + +2025-12-08 Tamar Christina <tamar.christina@arm.com> + + PR tree-optimization/122868 + * tree-vect-stmts.cc (vectorizable_load): Move check for invariant loads + down into the loop. + +2025-12-08 H.J. Lu <hjl.tools@gmail.com> + + PR target/122343 + * config/i386/sse.md (*<avx512>_cmp<mode>3_dup_op): Don't allow + 2 volatile memory references. + +2025-12-07 Jason Merrill <jason@redhat.com> + + * config/darwin-c.cc (find_subframework_header): Use + _cpp_get_file_*. + +2025-12-07 H.J. Lu <hjl.tools@gmail.com> + + PR target/122343 + * common.opt: Add -ffuse-ops-with-volatile-access. + * common.opt.urls: Regenerated. + * recog.cc (general_operand): Allow volatile memory reference if + -ffuse-ops-with-volatile-access is enabled. + * simplify-rtx.cc (simplify_binary_operation_1): Keep PLUS for 2 + volatile memory references. + * doc/invoke.texi: Document -ffuse-ops-with-volatile-access. + +2025-12-07 Alexandre Oliva <oliva@adacore.com> + + * cselib.cc (dump_cselib_val): Split out of and rename to... + (dump_cselib_val_ptr): ... this. + (dump_cselib_table): Adjust. Skip cselib_preserved_hash_table + when not allocated. + +2025-12-06 Alexandre Oliva <oliva@adacore.com> + + PR rtl-optimization/122947 + * calls.cc (expand_call): Add stack function usage in + non-ACCUMULATE_OUTGOING_ARGS configurations. + +2025-12-06 Alexandre Oliva <oliva@adacore.com> + + PR target/91420 + * config/riscv/riscv.cc (riscv_symbolic_constant_p): Require + offsets smaller than +/- 1GiB for PCREL symbols. + +2025-12-06 Jakub Jelinek <jakub@redhat.com> + + * attribs.cc (decl_attributes): Use attribute_value_equal to + compare attribute values instead of simple_cst_equal. + +2025-12-06 Dimitar Dimitrov <dimitar@dinux.eu> + + PR rtl-optimization/122675 + * bb-reorder.cc (edge_order): Fix BB edge ordering to be + descending. + +2025-12-05 Vladimir N. Makarov <vmakarov@redhat.com> + + PR rtl-optimization/122215 + * ira-color.cc (improve_allocation): Use register filter for all + loop on hard regs. + +2025-12-05 Richard Earnshaw <rearnsha@arm.com> + + PR target/122999 + * config/arm/arm.cc (arm_canonicalize_comparison): Defer + initializing maxval until we know we are dealing with an + integer mode. + +2025-12-05 Richard Biener <rguenther@suse.de> + + * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p): + When peeling for gaps we always need an epilog. + +2025-12-05 Richard Biener <rguenther@suse.de> + + PR tree-optimization/120939 + * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p): + Remove eliding an epilogue based on not computed + LOOP_VINFO_COST_MODEL_THRESHOLD and estimated max stmt executions. + +2025-12-05 Richard Biener <rguenther@suse.de> + + PR tree-optimization/123002 + * tree-vectorizer.h (supportable_widening_operation): Remove + vinfo and stmt_info parameters, add flag to indicate whether + the context would allow OP_{EVEN,ODD}. + * tree-vect-patterns.cc (vect_recog_abd_pattern): Adjust + and pass false. + (vect_recog_widen_op_pattern): Likewise. + (vect_recog_widen_abd_pattern): Likewise. + * tree-vect-stmts.cc (vectorizable_conversion): Move + even/odd validity check here, from supportable_widening_operation. + Adjust it to be conservative. + (supportable_widening_operation): Get flag whether even/odd + is OK to use and remove then unused parameters and code. + +2025-12-05 Richard Biener <rguenther@suse.de> + + * tree-pretty-print.cc (dump_mem_ref): Dump clique : base + specifier for MEM_REF and TARGET_MEM_REF when dumping + GIMPLE format. + +2025-12-05 Tobias Burnus <tburnus@baylibre.com> + + * gimplify.cc (gimplify_scan_omp_clauses): Handle + OMP_CLAUSE_DYN_GROUPPRIVATE by printing 'sorry, unimplemented'. + * tree-core.h (enum omp_clause_code): Add OMP_CLAUSE_DYN_GROUPPRIVATE. + (enum omp_clause_fallback_kind): New. + (struct tree_omp_clause): Add fallback_kind union member. + * tree-nested.cc (convert_nonlocal_omp_clauses, + convert_local_omp_clauses): Handle OMP_CLAUSE_DYN_GROUPPRIVATE. + * tree.cc (omp_clause_num_ops, omp_clause_code_name): Add + OMP_CLAUSE_DYN_GROUPPRIVATE. + * tree-pretty-print.cc (dump_omp_clause): Handle + OMP_CLAUSE_DYN_GROUPPRIVATE. + * tree.h (OMP_CLAUSE_DYN_GROUPPRIVATE_EXPR, + OMP_CLAUSE_DYN_GROUPPRIVATE_KIND): New #define. + +2025-12-05 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR middle-end/99782 + * config/i386/i386-expand.cc (ix86_gen_ccmp_next): Move the check + for mode earlier before expand_operands. + * config/aarch64/aarch64.cc (aarch64_gen_ccmp_next): Likewise. + +2025-12-05 Daniel Barboza <dbarboza@ventanamicro.com> + Jeff Law <jlaw@ventanamicro.com> + + * match.pd (`x & c ? (x - c) | (x | c)`): New pattern. + (`x & c ? (x & ~c) | (x | c)`): Likewise. + +2025-12-05 Pan Li <pan2.li@intel.com> + + * config/riscv/autovec-opt.md (*pred_cmp_swapped<mode>_scalar): + Add new pattern to match vec_dup > vec for vmsltu. + * config/riscv/predicates.md (comparison_swappable_operator): + Add new iterator for above pattern + * config/riscv/riscv-protos.h (expand_vx_cmp_vec_dup_vec): Add + new func to emit vmsltu.vx. + * config/riscv/riscv-v.cc (get_swapped_cmp_rtx_code): Add new + func to convert cmp code to swapped, like gtu to ltu. + (expand_vx_cmp_vec_dup_vec): Add new func decl. + +2025-12-04 Jakub Jelinek <jakub@redhat.com> + + PR target/122991 + * config/aarch64/aarch64.md (crc_rev<ALLI:mode><ALLX:mode>4, + crc<ALLI:mode><ALLX:mode>4): Use const_int_operand predicate for + the last operand. + +2025-12-04 Richard Biener <rguenther@suse.de> + + PR tree-optimization/122776 + * tree-vectorizer.h (vect_simd_clone_data::clone, + vect_simd_clone_data::clone_inbranch): New fields for + the two selected clones. + * tree-vect-stmts.cc (vectorizable_simd_clone_call): Record + both a possibly notinbranch and a inbranch clone. Delay + the choice between both to code generation based on + LOOP_VINFO_FULLY_MASKED_P. + +2025-12-04 Martin Jambor <mjambor@suse.cz> + + * gimple-range-fold.h (class fold_using_range): New member + function range_from_readonly_var. + * gimple-range-fold.cc (fold_using_range::fold_stmt): Call + range_from_readonly_var on assignments. + (range_from_missing_constructor_part): New function. + (range_from_readonly_load): Likewise. + (fold_using_range::range_from_readonly_var): Likewise. + * params.opt (param_vrp_cstload_limit): New. + * doc/invoke.texi (vrp-cstload-limit): Likewise. + +2025-12-04 Jakub Jelinek <jakub@redhat.com> + + PR target/122991 + * config/i386/i386.md (crc_rev<SWI124:mode>si4): Use const_int_operand + predicate for the last input argument. + +2025-12-04 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org> + + * lra-constraints.cc (get_reload_reg): Honor exclude start regs + while reusing reloads. + +2025-12-04 Kugan Vivekanandarajah <kvivekananda@nvidia.com> + + Revert: + 2025-12-02 Kugan Vivekanandarajah <kvivekananda@nvidia.com> + + * ipa-inline.cc (inline_functions_by_afdo): Remove resetting bool inlined. + +2025-12-03 Vladimir N. Makarov <vmakarov@redhat.com> + + PR rtl-optimization/85072 + * lra-assigns.cc (init_live_reload_and_inheritance_pseudos): + Improve calculation of live_reload_and_inheritance_pseudos and set + a constraint to do this. + * params.opt + (lra-max-pseudos-points-log2-considered-for-preferences): New. + * doc/invoke.texi + (lra-max-pseudos-points-log2-considered-for-preferences): Document + it. + +2025-12-03 Eric Botcazou <ebotcazou@adacore.com> + + PR tree-optimization/122934 + * tree-ssa-loop-niter.cc (simplify_using_initial_conditions): Use + singleton_p predicate even with boolean ranges. + +2025-12-03 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/122943 + * tree-switch-conversion.cc (switch_conversion::build_arrays): + Always gimplify subtraction in utype without cast to tidxtype + and set m_arr_ref_first to the last stmt of that. Remove unneeded + update_stmt call. If tidxtype is not utype, append after that stmt + cast to tidxtype and set tidx to the lhs of that cast. + +2025-12-03 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/122898 + * gimple-range-fold.cc (fur_source::register_relation): Return a bool; + (fur_depend::register_relation): Ditto. + (fur_relation::register_relation): Ditto. + * gimple-range-fold.h (fur_source::register_relation): Adjust prototype. + (fur_depend::register_relation): Ditto. + * gimple-range-path.cc (jt_fur_source::register_relation): Return bool. + * value-relation.cc (equiv_oracle::add_partial_equiv): Return a bool. + (equiv_oracle::record): Return a bool. + (relation_oracle::record): Return a bool. + (dom_oracle::record): Return a bool. + (dom_oracle::set_one_relation): Remove some debug output. + (path_oracle::equiv_set): Return a bool. + (path_oracle::register_equiv): Return a bool. + (path_oracle::record): Return a bool. + * value-relation.h (relation_oracle::record): Adjust prototype. + (equiv_oracle::add_partial_equiv): Ditto + (equiv_oracle::record): Ditto. + (dom_oracle::record): Ditto. + (path_oracle::equiv_set): Ditto. + (path_oracle::register_equiv): Ditto. + (path_oracle::record): Ditto. + +2025-12-03 Jose E. Marchesi <jose.marchesi@oracle.com> + + PR algol68/122964 + * dwarf2out.cc (gen_compile_unit_die): Set LVERSION to 1978 for + Algol 68 and add dwarf_version >= 5 to guard. + +2025-12-03 Tamar Christina <tamar.christina@arm.com> + + PR tree-optimization/122969 + * tree-vect-loop-manip.cc (vect_update_ivs_after_vectorizer): handle + non-ssa name IV var args. + +2025-12-03 Mathias Krause <minipli@grsecurity.net> + + * config/i386/i386.cc (x86_print_call_or_nop): Fix 16-bit NOP + generation. + +2025-12-03 Tamar Christina <tamar.christina@arm.com> + + PR middle-end/122959 + * tree-vect-loop-manip.cc (vect_do_peeling): Delay setting update_e. + +2025-12-03 liuhongt <hongtao.liu@intel.com> + + PR target/71921 + * config/i386/predicates.md (ieee_maxmin_comparison_operator): + New predicator. + * config/i386/sse.md (*minmax<mode>3_3): New define_insn_and_split. + (*minmax<mode>3_4): Ditto. + (*minmax<mode>3_1): Extend operands[2]/operands[4] to handle + immediate_operand. + +2025-12-02 John David Anglin <danglin@gcc.gnu.org> + + PR target/122874 + * config/pa/pa.cc (pa_emit_move_sequence): Break out large + REG+D addresses from MEM operands. Also, don't allow + unscaled indexed source operands till reload completes. + +2025-12-02 Robin Dapp <rdapp.gcc@gmail.com> + + PR target/122656 + * config/riscv/riscv-vector-builtins-bases.cc: Use + use_contiguous_load for vlsegff. + * config/riscv/riscv-vector-builtins.cc (function_expander::use_exact_insn): + Only add rounding mode operand if insn requires it and number of + arguments is < required. + (function_expander::use_ternop_insn): Ditto. + (function_expander::use_widen_ternop_insn): Ditto. + * config/riscv/vector.md: Use vector-mode source operand. + +2025-12-02 Kito Cheng <kito.cheng@sifive.com> + + * config/riscv/riscv-vector-builtins.cc + (function_builder::add_function): Remove placeholder_p parameter. + (function_builder::add_unique_function): Update call. + (function_builder::add_overloaded_function): Likewise. + * config/riscv/riscv-vector-builtins.h + (function_builder::add_function): Update declaration. + +2025-12-02 Robin Dapp <rdapp@ventanamicro.com> + + * tree-vect-stmts.cc (vectorizable_scan_store): Pass loop_lens + to vect_get_data_ptr_increment. + +2025-12-02 Tamar Christina <tamar.christina@arm.com> + + PR tree-optimization/122868 + * tree-vect-stmts.cc (vectorizable_load): Don't hoist loop invariant + conditional loads unless in header. + +2025-12-02 Kugan Vivekanandarajah <kvivekananda@nvidia.com> + + * ipa-inline.cc (inline_functions_by_afdo): Remove resetting bool inlined. + +2025-12-02 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR target/122912 + * config/aarch64/t-aarch64 (TM_H): Add aarch64-tuning-enums.def. + +2025-12-02 Alexandre Oliva <oliva@adacore.com> + + * hard-reg-set.h (hard_reg_set_iter_init): Drop unnecessary + increment of min. + (hard_reg_set_iter_set): Use ctz_hwi, and compute + word-advanced regno from word_no. + (hard_reg_set_iter_next): Only clear the cached LSB. + +2025-12-02 David Guillen Fandos <david@davidgf.net> + + * config/mips/mips.h (ISA_HAS_MADD_MSUB): Include allegrex. + * config/mips/mips.md: Tweak mul_acc_si/mul_sub_si to make it + work when MUL3 is not available. + +2025-12-02 David Guillen Fandos <david@davidgf.net> + + * config/mips/mips.h (ISA_HAS_WSBW): Defined a new macro. + * config/mips/mips.md (bswapsi2): Add new instruction. + (wsbwsi2): Replace with expand to support both wsbw and wsbh. + +2025-12-02 David Guillen Fandos <david@davidgf.net> + + * config/mips/mips.h (ISA_HAS_MIN_MAX): Defined a new macro. + * config/mips/mips.md (sminsi3): Defined a new instruction. + (smaxsi3): Defined a new instruction. + +2025-12-02 David Guillen Fandos <david@davidgf.net> + + * config/mips/mips-cpus.def (MIPS_CPU): Added a new CPU. + * config/mips/mips-tables.opt: Regenerated table. + * config/mips/mips.cc: Added cost table for the new CPU. + * config/mips/mips.h (TARGET_ALLEGREX): Defined a new macro. + (TUNE_ALLEGREX): Defined a new macro. + (ISA_HAS_CONDMOVE): Added Allegrex CPU to the list. + (ISA_HAS_LDC1_SDC1): Exclude Allegrex from the list. + (ISA_HAS_COND_TRAP): Exclude Allegrex from the list. + (ISA_HAS_COND_TRAPI): Exclude Allegrex from the list. + (ISA_HAS_CLZ_CLO): Added Allegrex CPU to the list. + (ISA_HAS_ROR): Added Allegrex CPU to the list. + (ISA_HAS_WSBH): Added Allegrex CPU to the list. + (ISA_HAS_SEB_SEH): Added Allegrex CPU to the list. + (ISA_HAS_EXT_INS): Added Allegrex CPU to the list. + (ISA_HAS_XFER_DELAY): Exclude Allegrex from the list. + (ISA_HAS_HILO_INTERLOCKS): Added Allegrex CPU to the list. + * config/mips/mips.md: Added Allegrex CPU as a new processor. + * doc/invoke.texi: Documented Allegrex as a new arch + +2025-12-02 Saurabh Jha <saurabh.jha@arm.com> + Radek Barton <radek.barton@microsoft.com> + + * config.gcc: Add new Makefile fragment and new object file. + * config/aarch64/aarch64-builtins.cc + (aarch64_ms_variadic_abi_init_builtins): Initialize builtin + variadic functions for aarch64-w64-mingw32. + * config/aarch64/aarch64-protos.h + (aarch64_ms_variadic_abi_init_builtins): Initialize builtin + variadic functions for aarch64-w64-mingw32. + * config/aarch64/aarch64.cc + (handle_aarch64_vector_pcs_attribute): Add support for + ARM_PCS_MS_VARIADIC. + (aarch64_ms_variadic_abi): Return descriptor to variadic + function call ABI for aarch64-w64-mingw32 target. + (aarch64_fntype_abi): Add support for variadic functions for + aarch64-w64-mingw32 target. + (aarch64_reg_save_mode): Add support for ARM_PCS_MS_VARIADIC. + (num_pcs_arg_regs): Add support for ARM_PCS_MS_VARIADIC. + (get_pcs_arg_reg): Add support for ARM_PCS_MS_VARIADIC. + (aarch64_arg_size): Returns size of argument. + (aarch64_ms_variadic_abi_layout_arg): aarch64-w64-mingw32 + specific support for variadic ABI. + (aarch64_layout_arg): Add support for ARM_PCS_MS_VARIADIC. + (aarch64_function_arg): Implement TARGET_FUNCTION_ARG. + (aarch64_function_arg_advance): Add support for + ARM_PCS_MS_VARIADIC. + (aarch64_function_arg_regno_p): Add support for + ARM_PCS_MS_VARIADIC. + (aarch64_init_builtins): Add support for TARGET_AARCH64_MS_ABI. + (aarch64_ms_variadic_abi_build_builtin_va_list): Setup va_list + for aarch64-w64-mingw32. + (aarch64_build_builtin_va_list): Add support for + TARGET_AARCH64_MS_ABI. + (aarch64_ms_variadic_abi_expand_builtin_va_start): Implement + TARGET_BUILD_BUILTIN_VA_START. + (aarch64_setup_incoming_varargs): Implement + TARGET_SETUP_INCOMING_VARARGS. + (aarch64_mangle_type): Implement TARGET_MANGLE_TYPE. + (aarch64_variadic_abi_strict_argument_naming): Implement + TARGET_STRICT_ARGUMENT_NAMING. + * config/aarch64/aarch64.h + (aarch64_frame): Add new field + unaligned_saved_varargs_size. + (enum arm_pcs): Add new enum option + ARM_PCS_MS_VARIADIC. + * config/aarch64/cygming.h + (SUBTARGET_ATTRIBUTE_TABLE): Add support for ms_abi. + * config/mingw/winnt.cc + (aarch64_handle_ms_abi_attribute): Handle ms_abi attribue. + * config/mingw/winnt.h + (aarch64_handle_ms_abi_attribute): Handle ms_abi attribute. + * config/aarch64/aarch64-abi-ms-protos.h: + (aarch64_arg_partial_bytes): Declare. + (aarch64_ms_variadic_abi_canonical_va_list_type): Declare. + (aarch64_ms_variadic_abi_enum_va_list): Declare. + (aarch64_ms_variadic_abi_fn_abi_va_list): Implement + TARGET_FN_ABI_VA_LIST. + * config/aarch64/aarch64-abi-ms.cc: + (aarch64_arg_partial_bytes): Implement TARGET_ARG_PARTIAL_BYTES. + (aarch64_ms_variadic_abi_canonical_va_list_type): Implement + TARGET_CANONICAL_VA_LIST_TYPE. + (aarch64_ms_variadic_abi_enum_va_list): Implement + TARGET_ENUM_VA_LIST_P. + (aarch64_ms_variadic_abi_fn_abi_va_list): Implement + TARGET_FN_ABI_VA_LIST. + * config/aarch64/t-aarch64-mingw: New Makefile fragment. + +2025-12-02 Saurabh Jha <saurabh.jha@arm.com> + Radek Barton <radek.barton@microsoft.com> + Martin Vejbora <mvejbora@microsoft.com> + + * config/aarch64/aarch64-abi-ms.h + (TARGET_LONG_DOUBLE_128): Set this to 0. + * config/aarch64/aarch64.cc + (aarch64_scalar_mode_supported_p): Make long double 64 bits. + (aarch64_c_mode_for_floating_type): Return true for TFmode. + * config/aarch64/aarch64.h + (TARGET_LONG_DOUBLE_128): Set this to 1. + +2025-12-02 Saurabh Jha <saurabh.jha@arm.com> + + * config/aarch64/aarch64-abi-ms.h + (ASM_COMMENT_START): Specify start of comment. + (ASM_OUTPUT_TYPE_DIRECTIVE): Moved from aarch64-coff.h. + (ASM_DECLARE_FUNCTION_SIZE): Specify end of function as comment. + * config/aarch64/aarch64-coff.h + (ASM_OUTPUT_TYPE_DIRECTIVE): Moved to aarch64-abi-ms.h. + (ASM_DECLARE_FUNCTION_SIZE): Moved to aarch64-abi-ms.h. + +2025-12-01 Peter Bergner <bergner@tenstorrent.com> + + PR target/122942 + * config/riscv/riscv-profiles.def (rva23s64): Add zifencei. + (rvb23s64): Likewise. + +2025-12-01 Jose E. Marchesi <jose.marchesi@oracle.com> + + * doc/install.texi (Downloading the source): Mention Algol 68. + +2025-12-01 Christophe Lyon <christophe.lyon@linaro.org> + + PR target/122858 + * config/arm/constraints.md (Ph): New constraint. + * config/arm/mve.md (mve_asrl_imm, mve_lsll_imm): Fix constraints + of operand 1 and handle 32 as special shift amount. + +2025-12-01 Robin Dapp <rdapp@ventanamicro.com> + + PR target/122652 + * config/riscv/riscv-vsetvl.cc: Add nullptr check. + +2025-12-01 Paul-Antoine Arras <parras@baylibre.com> + + PR fortran/120505 + * omp-low.cc (lower_omp_target): Set GOMP_MAP_IMPLICIT flag. + +2025-12-01 H.J. Lu <hjl.tools@gmail.com> + + PR target/122906 + * config/i386/i386-features.cc (ix86_emit_tls_call): Emit the + TLS call after deleted instructions. + +2025-11-30 Tamar Christina <tamar.christina@arm.com> + + PR tree-optimization/115120 + PR tree-optimization/119577 + PR tree-optimization/119860 + * tree-vect-loop-manip.cc (vect_can_advance_ivs_p): Check for nonlinear + mult induction and early break. + (vect_update_ivs_after_vectorizer): Support early break exits. + (vect_do_peeling): Support scalar IVs. + * tree-vect-loop.cc (vect_peel_nonlinear_iv_init): Support early break. + (vect_update_nonlinear_iv): use `unsigned_type_for` such that function + works for both vector and scalar types. + (vectorizable_induction, vectorizable_live_operation): Remove vector + early break IV code. + (vect_update_ivs_after_vectorizer_for_early_breaks): New. + (vect_transform_loop): Support new scalar IV for early break. + * tree-vect-slp.cc (vect_analyze_slp): Remove SLP build for early break + IVs. + * tree-vect-stmts.cc (vect_stmt_relevant_p): No longer mark early break + IVs as completely unused rather than used_only_live. They no longer + contribute to the vector loop and so should not be analyzed. + (can_vectorize_live_stmts): Remove vector early vreak IV code. + * tree-vectorizer.h (LOOP_VINFO_EARLY_BRK_NITERS_VAR): New. + (class loop_vec_info): Add early_break_niters_var. + +2025-11-30 Jose E. Marchesi <jose.marchesi@oracle.com> + + * Makefile.in (OPT_URLS_HTML_DEPS): Add ga68/Option-Index.html. + +2025-11-30 Jose E. Marchesi <jose.marchesi@oracle.com> + + * doc/install.texi (Configuration): Mention algol68 option for + --enable-languages. + (Algol 68-Specific Options): New section. + * doc/sourcebuild.texi (Top Level): Add entry for libga68. + +2025-11-30 Jose E. Marchesi <jose.marchesi@oracle.com> + + * config/rs6000/rs6000-logue.cc (rs6000_output_function_epilogue): + Handle "GNU Algol 68" in language_string. + +2025-11-30 Jose E. Marchesi <jose.marchesi@oracle.com> + + * config/darwin.h: Adapt specs for libga68.a. + +2025-11-30 Jose E. Marchesi <jose.marchesi@oracle.com> + + * dwarf2out.cc: Set DW_LANG_Algol68 an DW_LNAME_Algol68. + +2025-11-30 Jose E. Marchesi <jose.marchesi@oracle.com> + + * common.opt: New option -static-libga68. + * common.opt.urls: Generate. + * gcc.cc: Handle OPT_static_libga68. + * regenerate-opt-urls.py (PER_LANGUAGE_OPTION_INDEXES): Add Algol68. + +2025-11-30 Jose E. Marchesi <jose.marchesi@oracle.com> + + * Makefile.def (libga68): New module. + (configure-target-libga68): Likewise. + * Makefile.tpl (GA68): Define. + (GA68_FOR_BUILD): Likewise. + (GA68FLAGS): Likewise. + * configure.ac (--enable-libga68): New option. + (--enable-algol68-gc): Likewise. + (GA68): Subst. + (GA68FLAGS): Likewise. + Invoke ACX_PROG_GA68. + * configure: Regenerate. + * Makefile.in: Likewise. + +2025-11-29 Sandra Loosemore <sloosemore@baylibre.com> + + * common.opt.urls: Regenerated. + * config/aarch64/aarch64.opt.urls: Regenerated. + * config/alpha/alpha.opt.urls: Regenerated. + * config/arm/arm.opt.urls: Regenerated. + * config/avr/avr.opt.urls: Regenerated. + * config/bpf/bpf.opt.urls: Regenerated. + * config/c6x/c6x.opt.urls: Regenerated. + * config/cris/cris.opt.urls: Regenerated. + * config/cris/elf.opt.urls: Regenerated. + * config/csky/csky.opt.urls: Regenerated. + * config/darwin.opt.urls: Regenerated. + * config/epiphany/epiphany.opt.urls: Regenerated. + * config/frv/frv.opt.urls: Regenerated. + * config/ft32/ft32.opt.urls: Regenerated. + * config/gcn/gcn.opt.urls: Regenerated. + * config/i386/i386.opt.urls: Regenerated. + * config/ia64/ia64.opt.urls: Regenerated. + * config/loongarch/loongarch.opt.urls: Regenerated. + * config/m68k/m68k.opt.urls: Regenerated. + * config/microblaze/microblaze.opt.urls: Regenerated. + * config/mips/mips.opt.urls: Regenerated. + * config/mmix/mmix.opt.urls: Regenerated. + * config/or1k/or1k.opt.urls: Regenerated. + * config/pa/pa.opt.urls: Regenerated. + * config/pdp11/pdp11.opt.urls: Regenerated. + * config/rs6000/rs6000.opt.urls: Regenerated. + * config/s390/s390.opt.urls: Regenerated. + * config/sparc/sparc.opt.urls: Regenerated. + * config/v850/v850.opt.urls: Regenerated. + * config/vax/vax.opt.urls: Regenerated. + * config/visium/visium.opt.urls: Regenerated. + +2025-11-29 Sandra Loosemore <sloosemore@baylibre.com> + + * doc/invoke.texi (Options Summary): Switch ordering of FRV + and FT32. + (Submodel Options): Likewise in the menu and section ordering. + +2025-11-29 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/122243 + * doc/invoke.texi: Document -mno-android. + +2025-11-29 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/122243 + * config/frv/frv.opt (mbranch-cost=): Mark as Undocumented. + (mcond-exec-insns=): Likewise. + (mcond-exec-tempss=): Likewise. + * doc/invoke.texi (Option Summary) <FRV Options>: Remove duplicate + positive/negative forms from the list. + (FRV Options): Combine documentation of positive/negative forms + where they were listed separately. Add @opindex entries for + negative forms. + +2025-11-29 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/122243 + * config/ft32/ft32.opt (mlra): Mark obsolete option as Undocumented. + * doc/invoke.texi (Option Summary) <FT32 Options>: Remove -mlra. + (FT32 Options): Likewise. Add @opindex entries for negative + option forms. + +2025-11-29 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/122243 + * doc/invoke.texi (FR30 Options): Add @opindex for -mno-small-model. + +2025-11-29 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/122243 + * doc/invoke.texi (Option Summary) <eBPF Options>: Fix formatting + issues. Remove redundant entry for -mno-co-re. + (eBPF Options): Add missing @opindex entries. Combine documentation + for -mco-re and -mno-co-re. + +2025-11-29 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/122243 + * config/alpha/alpha.opt (mgas): Mark as Undocumented. + * doc/invoke.texi (Option Summary) <DEC Alpha Options>: Add + -mtls-kernel, -mtls-size=, -mlong-double-128, and -mlong-double-64. + (DEC Alpha Options): Likewise. + +2025-11-29 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/122243 + * config/darwin.opt (findirect-virtual-calls): Mark as Undocumented. + (fterminated-vtables): Likewise. + (multi_module): Likewise. + (multiply_defined): Likewise. + (multiply_defined_unused): Likewise. + (no_dead_strip_inits_and_terms): Likewise. + (noprefixbinding): Likewise. + (nomultidefs): Likewise. + (noprebind): Likewise. + (noseglinkedit): Likewise. + (ObjC, ObjC++): Add documentation strings. + (object): Mark as Undocumented. + (prebind): Likewise. + (prebind_all_twolevel_modules): Likewise. + (private_bundle): Likewise. + (sectobjectsymbols): Likewise. + (sectorder): Likewise. + (seg_addr_table_filename): Likewise. + (segcreate): Likewise. + (seglinkedit): Likewise. + (single_module): Likewise. + (X): Likewise. + (y): Likewise. + (Mach): Likewise. + * doc/invoke.texi (Option Summary) <Darwin Options>: Improve + alphabetization of the list. Remove obsolete/undocumented + options and add missing entries. + (Darwin Options): Add documentation for -arch, -dependency-file, + -fapple-kext, -matt-stubs, -fconstant-cfstrings, -mdynamic-no-pic, + -asm_macosx_version_min, -msymbol-stubs, -mtarget-linker, + -ObjC, -ObjC++, -Wnonportable-cfstrings. Update the list + of options passed to the linker to remove obsolete options + and add missing ones; also move the block of @opindex entries + before the list items instead of putting it in the middle. + +2025-11-29 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/122243 + * doc/invoke.texi (Option Summary) <Cygwin and MinGW Options>: + Correct spelling of -mthreads and add missing options. + (Cygwin and MinGW Options): Add @opindex for negative forms. + +2025-11-29 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/122243 + * doc/invoke.texi (Option Summary) <C-SKY Options>: Remove + entries for "Undocumented" options -EB, -EL, -mhard-float, + -msoft-float, and nonexistent option -mcse-cc. + (C-SKY Options): Likewise. Also remove references to "Undocumented" + option -mstm and uniformly index/document the -mno- forms for + consistency with other options in this section that already do so. + +2025-11-29 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/122243 + * config/cris/cris.opt (m32-bit, m16-bit, m8-bit): Remove + Undocumented property. + (m32bit, m8bit): Add Undocumented property. + * doc/invoke.texi (Option Summary) <CRIS Options>: Remove + obsolete -melf and -maout options from table, plus redundant + -mno-mul-bug-workaround. + (CRIS Options): Add @opindex for -mno- forms that didn't already + have one. Remove obsolete -melf documentation. Document + -mbest-lib-options, -moverride-best-lib-options, + -mtrap-using-break8, -mtrap-unaligned-atomic, and + -munaligned-atomic-may-use-library. + +2025-11-29 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/122243 + * doc/invoke.texi (Option Summary) <C6X Options>: Add -mdbst + and -mlong-calls. + (C6X Options): Likewise. + +2025-11-29 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/122243 + * doc/invoke.texi (Option Summary) <Blackfin Options>: + Remove redundant -mno- entries. + (Blackfin Options): Combine explicit -mno-* documentation + with that for the corresponding positive form of the option. + Add @opindex entries for the negative forms of options that + didn't already have one. + +2025-11-29 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/122243 + * config/arm/arm.opt (mapcs-reentrant): Mark as "Undocumented", + updatehelp string for internal documentation. + (mapcs-stack-check): Likewise update help string. + (mprint-tune-info, mneon-for-64bits): Mark as "Undocumented". + * doc/invoke.texi (Option Summary) <ARM Options>: Remove duplicate + entries for negative forms and entries for options that are + explicitly "Undocumented". Add missing entry for + -mpic-data-is-text-relative. Fix some formatting issues. + (ARM Options): Remove documentation for -mapcs-stack-check, + -mapcs-reentrant, -mflip-thumb, -mneon-for-64-bits, + -mprint-tune-info, and -mverbose-cost-dump. Add index entries + for -mno- option forms. Minor editing for clarity. + +2025-11-29 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/122243 + PR target/122288 + * config/gcn/gcn.opt (m32, m64, mgomp): Mark "Undocumented" + since these options don't actually do anything useful. + (flag_bypass_init_error, stack_size_opt, gang_size_opt): Correct + opt file syntax. + (mstack-size=): Mark "Undocumented" since it's obsolete. + * doc/invoke.texi (Option Summary) <AMD GCN Options>: + Remove obsolete options, add missing entries for + -mgang-private-size=, -msram-ecc=, and -mxnack=. + (AMD GCN Options): Likewise. + +2025-11-29 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/122243 + * config/epiphany/epiphany.opt (mlong-calls): Make it do something + useful. + (may-round-for-trunc): Make this undocumented option with a weird + name an alias for -mmay-round-for-trunc. + (mfp-iarith): Fix doc string. + * doc/invoke.texi (Option Summary) <Adapteva Epiphany Options>: + Add missing options. + (Adapteva Epiphany Options): Document negative forms also when + that is not the default, or where it's unclear. Document + -may-round-for-trunc and -mfp-iarith. Fix spelling of + -mpost-inc and -mpost-modify. + +2025-11-29 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/122243 + * config/aarch64/aarch64.opt (Wexperimental-fmv-target): Mark + as "Undocumented". + * doc/invoke.texi (Option Summary) <AArch64 Options>: Don't + list "Undocumented" aarch64 options -mverbose-cost-dump or + -Wexperimental-fmv-target, or both positive and negative forms + of other options. Add missing options. Fix whitespace problems. + (AArch64 Options): Light copy-editing. Add missing @opindex + entries to match the documented options. Undocument + -mverbose-cost-dump and -Wexperimental-fmv-target. + +2025-11-28 Jakub Jelinek <jakub@redhat.com> + + * config/rs6000/rs6000.cc (complex_multiply_builtin_code): + Avoid arithmetics between enumerators from different enum types. + (complex_divide_builtin_code): Likewise. + +2025-11-28 Jakub Jelinek <jakub@redhat.com> + + * config/loongarch/loongarch.cc (loongarch_unspec_address_offset): + Avoid arithmetics between enumerators from different enum types. + (loongarch_call_tls_get_addr): Likewise. + +2025-11-28 Jakub Jelinek <jakub@redhat.com> + + * config/mips/mips.cc (mips_unspec_address_offset): Avoid + arithmetics between enumerators from different enum types. + +2025-11-28 Jakub Jelinek <jakub@redhat.com> + + * config/riscv/riscv-v.cc (expand_const_vector_onestep): Avoid + bitwise ops between enumerators from different enum types. + (emit_vec_cvt_x_f): Likewise. + (emit_vec_cvt_x_f_rtz): Likewise. + * config/riscv/riscv.cc (riscv_unspec_address_offset): Avoid + arithmetics between enumerators from different enum types. + +2025-11-28 Sam James <sam@gentoo.org> + + * crc-verification.cc (crc_symbolic_execution::is_used_outside_the_loop): + Fix 'assignment' typo. + +2025-11-28 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/122686 + * range-op.cc (operator_bitwise_and::op1_range): Check for + undefined bitmask. + * value-range.cc (prange::intersect): Handle undefined bitmask + intersection. + (irange::get_bitmask): Ditto. + (irange::intersect_bitmask): Ditto. + * value-range.h (irange_bitmask::intersect): Return false if the + result is UNDEFINED. + +2025-11-28 Tobias Burnus <tburnus@baylibre.com> + + * config.gcc (amdgcn-*-*): Use gfx90a for 'with_arch'. + For TM_MULTILIB_CONFIG, replace specific archs by + gfx{9,9-4,10-3,11}-generic, keep gfx90{8,a}. + * config/gcn/gcn.opt (march=, mtune=): Use gfx90a. + * doc/install.texi (amdgcn): Update accordingly. + +2025-11-28 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org> + + * config/s390/s390-builtins.h + (S390_OVERLOADED_BUILTIN_VAR_OFFSET,S390_ALL_BUILTIN_MAX): Fix + enum arithmetic. + * config/s390/s390.cc (OB_DEF): Ditto. + +2025-11-28 Richard Biener <rguenther@suse.de> + + PR tree-optimization/122844 + * tree-vect-slp.cc (vect_analyze_slp_reduc_chain): Only + try stripping sign conversions around ops where this is valid. + +2025-11-28 Jim Lin <jim@andestech.com> + + * config/riscv/riscv.cc (riscv_output_move): Use \n\t instead + of semicolon to separate instructions in fmv.x.h emulation. + +2025-11-28 Charlie Jenkins <charlie@rivosinc.com> + + * config.gcc: Add cpu to supported configure options + * config/riscv/riscv.h (riscv_arch_help): Use --with-cpu during + compilation + * doc/install.texi: Mention in docs that --with-cpu is supported + +2025-11-28 Mark Zhuang <mark.zhuang@spacemit.com> + + * config/riscv/riscv-cores.def (RISCV_CORE): Add xsmtvdot to + spacemit-x60 + * config/riscv/riscv-ext.def: Add xsmtvdot + * config/riscv/riscv-ext.opt: Ditto + * config/riscv/t-riscv: Ditto + * doc/riscv-ext.texi: Ditto + * config/riscv/riscv-ext-spacemit.def: Define xsmtvdot + +2025-11-28 Mark Zhuang <mark.zhuang@spacemit.com> + + * config/riscv/riscv-ext.opt: Generated file. + +2025-11-28 Kuan-Lin Chen <rufus@andestech.com> + + * config/riscv/riscv-cores.def (RISCV_TUNE): Add andes-45-sereis. + (RISCV_CORE): Add Andes 45 series cpu list. + * config/riscv/riscv-opts.h + (enum riscv_microarchitecture_type): Add andes_45_series. + * config/riscv/riscv.cc: Add andes_45_tune_info. + * config/riscv/riscv.md: Add andes_45. + * doc/riscv-mcpu.texi: Regenerated for Andes cpu list. + * doc/riscv-mtune.texi: Regenerated for andes-45-series. + * config/riscv/andes-45-series.md: New file. + +2025-11-28 Kuan-Lin Chen <rufus@andestech.com> + + * config/riscv/riscv-cores.def (RISCV_TUNE): Add andes-23-series. + (RISCV_CORE): Add Andes 23-series cpu list. + * config/riscv/riscv-opts.h + (enum riscv_microarchitecture_type): Add andes_23_series. + * config/riscv/riscv.cc: Add andes_23_tune_info. + * config/riscv/riscv.md: Add andes_23. + * doc/riscv-mcpu.texi: Regenerated for Andes cpu list. + * doc/riscv-mtune.texi: Regenerated for andes-23-series. + * config/riscv/andes-23-series.md: New file. + +2025-11-28 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/122733 + * gimple-match-head.cc (gimple_match_range_of_expr): Return false + even when range_of_expr returns true, but the range is undefined_p. + * match.pd ((mult (plus:s@5 (mult:s@4 @0 @1) @2) @3)): Remove + vr0.undefined_p () check. + ((plus (mult:s@5 (plus:s@4 @0 @1) @2) @3)): Likewise. + ((X + M*N) / N -> X / N + M): Remove vr4.undefined_p () check. + ((X - M*N) / N -> X / N - M): Likewise. + ((y << x) == x, (y << x) != x): Use convert2? instead of + nop_convert2? and test INTEGRAL_TYPE_P on TREE_TYPE (@0) rather than + TREE_TYPE (@1). + ((y << x) {<,<=,>,>=} x): New simplification. + (((T)(A)) + CST -> (T)(A + CST)): Remove vr.undefined_p () check. + (x_5 == cstN ? cst4 : cst3): Remove r.undefined_p () check. + +2025-11-28 Tamar Christina <tamar.christina@arm.com> + + PR middle-end/122890 + * optabs.cc (emit_cmp_and_jump_insns): Check for SSA Name. + +2025-11-27 Matthieu Longo <matthieu.longo@arm.com> + + * config/aarch64/aarch64-c.cc (aarch64_define_unconditional_macros): Define + __ARM_BUILDATTR64_FV when BA support is detected in GAS. + +2025-11-27 Wilco Dijkstra <wilco.dijkstra@arm.com> + + * config/aarch64/aarch64.md (ctz<mode>2): Use compact syntax. + +2025-11-27 Wilco Dijkstra <wilco.dijkstra@arm.com> + + * config/aarch64/aarch64.md (ffs<mode>2): Use gen_ctz. + (ctz<mode>2): Model ctz as a single target instruction. + +2025-11-27 Wilco Dijkstra <wilco.dijkstra@arm.com> + + * config/aarch64/atomics.md (*dmb): Expand release fence into dmb ishld + and dmb ishst. + +2025-11-27 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * tree-ssa-reassoc.cc (rewrite_expr_tree): Swap + oe1 and oe2 if commutative code and not in + canonical order. + +2025-11-27 Georg-Johann Lay <avr@gjlay.de> + + * config/avr/avr-mcus.def (AVR_MCUS): Add avr16la14, avr16la20, + avr16la28, avr16la32, avr32la14, avr32la20, avr32la28, avr32la32. + * doc/avr-mmcu.texi: Rebuild. + +2025-11-27 Robin Dapp <rdapp@ventanamicro.com> + + PR tree-optimization/122855 + PR tree-optimization/122850 + * tree-ssa-forwprop.cc (simplify_vector_constructor): Nop + convert input if necessary. + +2025-11-27 Andrew Stubbs <ams@baylibre.com> + + * config/gcn/gcn.cc (gcn_init_cumulative_args): Emit a warning if the + -mxnack setting looks wrong. + * config/gcn/mkoffload.cc: Include tree.h and omp-general.h. + (process_asm): Add omp_requires parameter. + Emit HSA_XNACK code into mkoffload_setup, as required. + (main): Modify HSACO_ATTR_OFF to preserve user-set -mxnack. + Pass omp_requires to process_asm. + +2025-11-27 Jakub Jelinek <jakub@redhat.com> + + PR target/122714 + * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Adjust + MEM_REFs offset for bitint_big_endian if ltype doesn't have the + same byte size as m_limb_type. + +2025-11-27 Richard Biener <rguenther@suse.de> + + * tree-vect-stmts.cc (vectorizable_simd_clone_call): Fix + recording of the mask type again. Adjust placing of + mask arguments for non-masked calls. + +2025-11-27 Dhruv Chawla <dhruvc@nvidia.com> + + PR tree-optimization/122733 + * match.pd ((y << x) {<,<=,>,>=} x): Remove. + ((y << x) {==,!=} x): Call constant_boolean_node instead of + build_one_cst/build_zero_cst and combine into one pattern. + +2025-11-27 Jakub Jelinek <jakub@redhat.com> + + * fold-const.h (expr_not_equal_to): Add gimple * argument defaulted + to NULL. + * fold-const.cc (expr_not_equal_to): Likewise, pass it through to + range_of_expr. + * generic-match-head.cc (gimple_match_ctx): New static inline. + * match.pd (X % -Y -> X % Y): Capture NEGATE and pass + gimple_match_ctx (@2) as new 3rd argument to expr_not_equal_to. + ((A * C) +- (B * C) -> (A+-B) * C): Pass gimple_match_ctx (@3) + as new 3rd argument to expr_not_equal_to. + (a rrotate (bitsize-b) -> a lrotate b): Likewise. + +2025-11-27 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/119683 + * gimple-match.h (gimple_match_ctx): Move to ... + * gimple-match-head.cc (gimple_match_ctx): ... here. Make static. + (gimple_match_range_of_expr): New static inline. + * match.pd ((mult (plus:s (mult:s @0 @1) @2) @3)): Use + gimple_match_range_of_expr. + ((plus (mult:s (plus:s @0 @1) @2) @3)): Likewise. + ((t * u) / u -> t): Likewise. + ((t * u) / v -> t * (u / v)): Likewise. + ((X + M*N) / N -> X / N + M): Likewise. + ((X - M*N) / N -> X / N - M): Likewise. + ((X + C) / N -> X / N + C / N): Likewise. + (((T)(A)) + CST -> (T)(A + CST)): Likewise + (x_5 == cstN ? cst4 : cst3): Likewise. Do r.set_varying + even when gimple_match_range_of_expr failed. + +2025-11-27 Christophe Lyon <christophe.lyon@linaro.org> + + * config/arm/arm-builtins.cc (arm_init_mve_builtins): Remove + volatile qualifier. + +2025-11-27 Richard Biener <rguenther@suse.de> + + PR tree-optimization/122885 + * tree-vect-loop.cc (vect_find_reusable_accumulator): Reject + mask vectors which do not use integer vector modes. + (vect_create_partial_epilog): Assert the same. + +2025-11-27 liuhongt <hongtao.liu@intel.com> + + * config/i386/i386-options.cc (set_ix86_tune_features): Set + gather/scatter tune if OPTION_SET_P. + * config/i386/i386.opt: Refactor mgather/mscatter. + +2025-11-27 Lulu Cheng <chenglulu@loongson.cn> + + * doc/extend.texi: Remove the incorrect prompt message. + +2025-11-27 Sandra Loosemore <sloosemore@baylibre.com> + + * doc/invoke.texi (Option Summary) <C++ Langauge Options>: + Add --compile-std-module. + +2025-11-26 Jeff Law <jlaw@ventanamicro.com> + + Revert: + 2025-10-14 Zhongyao Chen <chenzhongyao.hit@gmail.com> + + * common/config/riscv/riscv-common.cc (riscv_subset_list::get_profile_name): + New function. + * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Define + profile macro if a profile is detected. + * config/riscv/riscv-subset.h (riscv_subset_list::get_profile_name): Declare. + +2025-11-26 Alejandro Colomar <alx@kernel.org> + + * doc/extend.texi (Syntax Extensions): Document _Maxof & _Minof. + +2025-11-26 Tamar Christina <tamar.christina@arm.com> + + * optabs.cc (emit_cmp_and_jump_insns): Check for non-single use. + +2025-11-26 Jeff Law <jlaw@ventanamicro.com> + + PR rtl-optimization/122735 + * simplify-rtx.cc (simplify_binary_operation_1): When moving a SUBREG + from an outer expression to an inner operand, make sure to avoid + trying to create invalid SUBREGs. + +2025-11-26 Richard Earnshaw <rearnsha@arm.com> + + PR target/122867 + * config/arm/arm.cc (arm_print_operand): Use %- to + emit LOCAL_LABEL_PREFIX. + (arm_print_operand_punct_valid_p): Allow %- for punct + and make %_ valid for all compilation variants. + * config/arm/thumb2.md (*thumb2_cbz): Handle very + large branch ranges that exceed the limit of b<cond>. + (*thumb2_cbnz): Likewise. + +2025-11-26 Richard Biener <rguenther@suse.de> + + PR tree-optimization/110571 + * tree-vectorizer.h (vect_need_peeling_or_partial_vectors_p): Remove. + * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p): + Fix when called on epilog loops. Make static. + * tree-vect-loop-manip.cc (vect_do_peeling): Do not + re-compute LOOP_VINFO_PEELING_FOR_NITER. + +2025-11-26 Tamar Christina <tamar.christina@arm.com> + + PR tree-optimization/122861 + * optabs.cc (emit_cmp_and_jump_insns): Check argument instead of result. + +2025-11-26 Jakub Jelinek <jakub@redhat.com> + + * doc/invoke.texi (gnu++17): Remove comment about the default. + (c++20): Remove note about experimental support, except add a note + that modules are still experimental and need to be enabled separately. + (gnu++20): Likewise. Move here comment about the default. + (fcoroutines): Mention it is enabled by default for C++20 and later. + * doc/standards.texi: Document that the default for C++ is + -std=gnu++20. + +2025-11-26 Richard Biener <rguenther@suse.de> + + * tree-vect-stmts.cc (vectorizable_simd_clone_call): Handle + AVX512 masking for loop masked SIMD clone call. + +2025-11-26 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/122835 + * tree-eh.cc (replace_goto_queue_1): Handle GIMPLE_ASM. + (maybe_record_in_goto_queue): Likewise. + (lower_eh_constructs_2): Likewise. + +2025-11-26 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/119683 + * gimple-match.h (gimple_match_ctx): New inline function. + * match.pd ((mult (plus:s (mult:s @0 @1) @2) @3)): Capture + PLUS, use get_range_query (cfun) instead of + get_global_range_query () and pass gimple_match_ctx (@5) + as 3rd argument to range_of_expr. + ((plus (mult:s (plus:s @0 @1) @2) @3)): Similarly for MULT, + with @4 instead of @5. + ((t * u) / u -> t): Similarly with @2 instead of @4. + ((t * u) / v -> t * (u / v)): Capture MULT, pass gimple_match_ctx (@3) + as 3rd argument to range_of_expr. + ((X + M*N) / N -> X / N + M): Pass gimple_match_ctx (@3) or + gimple_match_ctx (@4) as 3rd arg to some range_of_expr calls. + ((X - M*N) / N -> X / N - M): Likewise. + ((X + C) / N -> X / N + C / N): Similarly. + (((T)(A)) + CST -> (T)(A + CST)): Capture CONVERT, use + get_range_query (cfun) instead of get_global_range_query () + and pass gimple_match_ctx (@2) as 3rd argument to range_of_expr. + (x_5 == cstN ? cst4 : cst3): Capture EQNE and pass + gimple_match_ctx (@4) as 3rd argument to range_of_expr. + +2025-11-26 Soumya AR <soumyaa@nvidia.com> + + * config/aarch64/aarch64-json-tunings-parser.cc: Include + aarch64-json-tunings-parser-generated.inc. + * config/aarch64/aarch64-json-tunings-printer.cc: Include + aarch64-json-tunings-printer-generated.inc. + * config/aarch64/aarch64-opts.h (AARCH64_LDP_STP_POLICY): Use + aarch64-tuning-enums.def. + * config/aarch64/aarch64-protos.h (AARCH64_AUTOPREFETCH_MODE): Use + aarch64-tuning-enums.def. + * config/aarch64/t-aarch64: Invoke + aarch64-generate-json-tuning-routines.py if the schema is modified. + * config/aarch64/aarch64-generate-json-tuning-routines.py: New + maintenance script to generate JSON parser/printer routines. + * config/aarch64/aarch64-json-tunings-parser-generated.inc: New file. + * config/aarch64/aarch64-json-tunings-printer-generated.inc: New file. + * config/aarch64/aarch64-tuning-enums.def: New file. + +2025-11-26 Soumya AR <soumyaa@nvidia.com> + + * config.gcc: Add aarch64-json-tunings-parser.o. + * config/aarch64/aarch64.cc (aarch64_override_options_internal): Invoke + aarch64_load_tuning_params_from_json if -muser-provided-CPU= is + (aarch64_json_tunings_tests): Extern aarch64_json_tunings_tests(). + (aarch64_run_selftests): Add aarch64_json_tunings_tests(). + * config/aarch64/aarch64.opt: New option. + * config/aarch64/t-aarch64 (aarch64-json-tunings-parser.o): New define. + * config/aarch64/aarch64-json-schema.h: New file. + * config/aarch64/aarch64-json-tunings-parser.cc: New file. + * config/aarch64/aarch64-json-tunings-parser.h: New file. + +2025-11-26 Soumya AR <soumyaa@nvidia.com> + + * json.h (class object): Add get_map () method. + (is_a_helper<json::literal *>, is_a_helper<const json::literal *>): + New template specializations. + +2025-11-26 Soumya AR <soumyaa@nvidia.com> + + * config.gcc: Add aarch64-json-tunings-printer.o. + * config/aarch64/aarch64.cc (aarch64_override_options_internal): Invoke + aarch64_print_tune_params if -fdump-tuning-model= is specified. + * config/aarch64/aarch64.opt: New option. + * config/aarch64/t-aarch64 (aarch64-json-tunings-printer.o): New define. + * config/aarch64/aarch64-json-tunings-printer.cc: New file. + * config/aarch64/aarch64-json-tunings-printer.h: New file. + +2025-11-26 Soumya AR <soumyaa@nvidia.com> + + * config/aarch64/aarch64-protos.h + (struct scale_addr_mode_cost): Remove const from struct members. + (struct cpu_addrcost_table): Likewise. + (struct cpu_regmove_cost): Likewise. + (struct simd_vec_cost): Likewise. + (struct sve_vec_cost): Likewise. + (struct aarch64_base_vec_issue_info): Likewise. + (struct aarch64_simd_vec_issue_info): Likewise. + (struct aarch64_sve_vec_issue_info): Likewise. + (struct aarch64_vec_issue_info): Likewise. + (struct cpu_vector_cost): Likewise. + (struct cpu_branch_cost): Likewise. + (struct cpu_approx_modes): Likewise. + (struct cpu_prefetch_tune): Likewise. + * config/arm/aarch-common-protos.h + (struct alu_cost_table): Remove const from struct members. + (struct mult_cost_table): Likewise. + (struct mem_cost_table): Likewise. + (struct fp_cost_table): Likewise. + (struct vector_cost_table): Likewise. + (struct cpu_cost_table): Likewise. + +2025-11-26 Dhruv Chawla <dhruvc@nvidia.com> + + PR middle-end/116815 + * config/aarch64/aarch64.md + (*aarch64_plus_within_<optab><mode>3_<ovf_commutate>): New pattern. + (*aarch64_minus_within_<optab><mode>3): Likewise. + * config/aarch64/iterators.md (ovf_add_cmp): New code attribute. + (udf_sub_cmp): Likewise. + (UMAXMIN): New code iterator. + (ovf_commutate): New iterator. + (ovf_comm_opp): New int attribute. + +2025-11-26 Pan Li <pan2.li@intel.com> + + * match.pd: Add pattern for SAT_MUL form 7 include + mul and widen_mul. + +2025-11-26 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * tree-ssa-phiprop.cc (propagate_with_phi): Only + calculate on demand post dom info when the new store + might trap. + +2025-11-26 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR tree-optimization/122847 + * tree-ssa-phiprop.cc (propagate_with_phi): Add type + check for reuse of the phi for the delayed statements. + +2025-11-25 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> + + * configure.ac (gcc_cv_header_zstd_h): Save, restore CXXFLAGS, + LDFLAGS. + * configure: Regenerate. + +2025-11-25 Tamar Christina <tamar.christina@arm.com> + + PR target/118974 + * config/aarch64/aarch64-simd.md (xor<mode>3<vczle><vczbe>): Rename ... + (@xor<mode>3<vczle><vczbe>): .. to this. + (cbranch<mode>4): Update comments. + (<optab><mode>): New. + * config/aarch64/aarch64-sve.md (cbranch<mode>4): Update comment. + (<optab><mode>): New. + (aarch64_ptest<mode>): Rename to ... + (@aarch64_ptest<mode>): .. this. + * config/aarch64/iterators.md (UNSPEC_CMP_ALL, UNSPEC_CMP_ANY, + UNSPEC_COND_CMP_ALL, UNSPEC_COND_CMP_ANY): New. + (optabs): Add them. + (CBRANCH_CMP, COND_CBRANCH_CMP, cbranch_op): New. + * config/aarch64/predicates.md (aarch64_cbranch_compare_operation): New. + +2025-11-25 Tamar Christina <tamar.christina@arm.com> + + PR target/118974 + * tree-vect-stmts.cc (supports_vector_compare_and_branch): New. + (vectorizable_early_exit): Use it. + +2025-11-25 Tamar Christina <tamar.christina@arm.com> + + PR target/118974 + * optabs.def (vec_cbranch_any_optab, vec_cbranch_all_optab, + cond_vec_cbranch_any_optab, cond_vec_cbranch_all_optab, + cond_len_vec_cbranch_any_optab, cond_len_vec_cbranch_all_optab): New. + * doc/md.texi: Document them. + * optabs.cc (prepare_cmp_insn): Refactor to take optab to check for + instead of hardcoded cbranch and support mask and len. + (emit_cmp_and_jump_insn_1, emit_cmp_and_jump_insns): Implement them. + (emit_conditional_move, emit_conditional_add, gen_cond_trap): Update + after changing function signatures to support new optabs. + +2025-11-25 Jason Merrill <jason@redhat.com> + + * doc/invoke.texi: Document --compile-std-module. + * gcc.cc (struct infile): Add artificial field. + (add_infile): Set it. + (driver::prepare_infiles): Check it. + +2025-11-25 Jason Merrill <jason@redhat.com> + + * doc/invoke.texi (C++ Modules): Remove TU-local caveat. + +2025-11-25 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/120052 + * gimplify.cc (gimplify_call_expr): For IFN_UBSAN_BOUNDS + call with integer_onep first argument, change that argument + to 0 and add TYPE_MAX_VALUE (TYPE_DOMAIN (arr_type)) to + 3rd argument before gimplification. + +2025-11-25 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/120564 + * omp-expand.cc (extract_omp_for_update_vars): Use build2 instead of + fold_build2 to build argument for gimple_build_cond_empty. + +2025-11-25 Jakub Jelinek <jakub@redhat.com> + + * alias.cc (get_alias_set): Fix comment typo, TYPE_CANOINCAL + -> TYPE_CANONICAL. + +2025-11-25 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/122624 + * tree.cc (build_bitint_type): Use type_hash_canon_hash. + +2025-11-25 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> + + * doc/sourcebuild.texi (Add Options): Document + check_function_bodies. + +2025-11-24 Alexandre Oliva <oliva@adacore.com> + + PR rtl-optimization/122767 + * ira-color.cc (allocno_hard_regs_compare): Break ties + using... + * hard-reg-set.h (hard_reg_set_first_diff): ... this. New + HARD_REG_SET API entry point. + +2025-11-24 Robin Dapp <rdapp@ventanamicro.com> + + * tree-vect-slp.cc (vect_bb_vectorization_profitable_p): + Multiply scalar cost by vect-scalar-cost-multiplier. + +2025-11-24 Robin Dapp <rdapp.gcc@gmail.com> + + * config/riscv/autovec.md (select_vl<mode>): Rename to... + (select_vl<V:mode><P:mode>): ...this. + * doc/md.texi: Document new behavior. + * internal-fn.cc (select_vl_direct): Make + (expand_select_vl_optab_fn): Adjust for convert optab. + (direct_select_vl_optab_supported_p): Ditto. + * internal-fn.def (SELECT_VL): Ditto. + * optabs.def (OPTAB_CD): Add select_vl. + (OPTAB_D): Remove select_vl. + * tree-vect-loop-manip.cc (vect_set_loop_controls_directly): + Adjust for convert select_vl optab. + * tree-vect-loop.cc: Ditto. + +2025-11-24 Robin Dapp <rdapp.gcc@gmail.com> + + * config/riscv/autovec.md: Use V_VLS_ZVFH for vec_set. + * config/riscv/riscv-modes.def (RVV_NF4_MODES): Add BF mdoes. + (ADJUST_PRECISION): Ditto. + (VECTOR_MODE_WITH_PREFIX): Ditto. + (VLS_MODES): Ditto. + * config/riscv/riscv-v.cc (can_be_broadcast_p): Add BF handling. + * config/riscv/riscv-vector-switch.def (VLS_ENTRY): Add BF + modes. + * config/riscv/riscv.md: Ditto. + * config/riscv/vector-iterators.md: Document modes. + * config/riscv/vector.md: Add BF modes. + +2025-11-24 Robin Dapp <rdapp@ventanamicro.com> + + PR tree-optimization/122797 + * tree-vect-slp.cc (vect_load_perm_consecutive_p): Check + permutation start at element 0 with value instead of starting + at a given element. + (vect_optimize_slp_pass::remove_redundant_permutations): + Use start value of 0. + * tree-vectorizer.h (vect_load_perm_consecutive_p): Set default + value to to UINT_MAX. + +2025-11-24 Robin Dapp <rdapp@ventanamicro.com> + + * tree-ssa-forwprop.cc (simplify_vector_constructor): + Allow nop conversions. + +2025-11-24 John David Anglin <danglin@gcc.gnu.org> + + * config/pa/pa.h (REGS_OK_FOR_BASE_INDEX): New define. + * config/pa/pa.md: Update peephole2 patterns for scaled/unscaled + indexed loads and stores. + +2025-11-24 Richard Biener <rguenther@suse.de> + + PR tree-optimization/122826 + * tree-vect-stmts.cc (vectorizable_simd_clone_call): Only + use single-lane SLP for SIMD_CLONE_ARG_TYPE_UNIFORM + and SIMD_CLONE_ARG_TYPE_LINEAR_[REF_]CONSTANT_STEP. + +2025-11-24 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + Richard Biener <rguenther@suse.de> + + PR tree-optimization/116835 + * tree-ssa-phiprop.cc (propagate_with_phi): Admend the + post-dom check to deal with ssa cycles. + +2025-11-24 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR tree-optimization/60183 + * tree-ssa-phiprop.cc (propagate_with_phi): Delay the decision + of always rejecting proping into the loop until all are done. + if there was some delay stmts and a phi was created fill them in. + +2025-11-24 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR tree-optimization/60183 + * tree-ssa-phiprop.cc (propagate_with_phi): Allow + known non-trapping loads to happen back into the + loop. + +2025-11-24 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * tree-ssa-forwprop.cc (do_simple_agr_dse): Allow + for mismatched clobbers. + +2025-11-24 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR tree-optimization/122633 + * tree-ssa-forwprop.cc (do_simple_agr_dse): Remove + lhs of dead store for a call (or the whole call stmt). + +2025-11-24 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * match.pd (`(ptr_diff (ptr_plus @0 @2) (ptr_plus @1 @2))`): Move pattern + earlier to the other `(ptr_diff (ptr_plus) (ptr_plus))` pattern. + +2025-11-24 Richard Biener <rguenther@suse.de> + + * tree-vect-stmts.cc (vectorizable_simd_clone_call): Move + all SIMD clone validity checks to SIMD clone selection. + Remove late constant/external def vector type setting and + verification. + +2025-11-24 Jeff Law <jlaw@ventanamicro.com> + + PR rtl-optimization/122782 + * ext-dce.cc (ext_dct_process_uses): Guard against undefined shifts + by properly checking modes on the input object. + +2025-11-24 Yury Khrustalev <yury.khrustalev@arm.com> + + PR debug/121964 + * dwarf2out.cc (gen_array_type_die): Add DW_AT_bit_stride attribute + for array types based on element type bit precision for integer and + boolean element types. + +2025-11-24 Yury Khrustalev <yury.khrustalev@arm.com> + + * machmode.def (VECTOR_BOOL_MODE): Fix comment. + +2025-11-24 Eric Botcazou <ebotcazou@adacore.com> + + PR ada/33994 + * fold-const.h (int_const_convert): New prototype. + * fold-const.cc (fold_convert_const_int_from_int): Rename to... + (int_const_convert): ...this, remove static keyword and add third + parameter OVERFLOWABLE. + (fold_convert_const): Call int_const_convert if ARG1 is an integer + constant. + +2025-11-24 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org> + + * config.gcc (aarch64-*-mingw*): Set native_system_header_dir. + +2025-11-23 John David Anglin <danglin@gcc.gnu.org> + + * config/pa/pa64-linux.h (GLIBC_DYNAMIC_LINKER): Define. + +2025-11-23 John David Anglin <danglin@gcc.gnu.org> + + PR target/113932 + PR target/113933 + * config/pa/pa.opt (mlra): Default to LRA instead of reload. + +2025-11-23 John David Anglin <danglin@gcc.gnu.org> + + * config/pa/pa.cc (pa_print_operand): Use REG_POINTER + flag to select base and index registers on targets with + non-equivalent space registers. + (pa_legitimate_address_p): Don't allow scaled and unscaled + indexed addresses until reload is complete. Allow any + register order in unscaled addresses as long as the + REG_POINTER flag is correctly set/unset in the base/index + registers. + * config/pa/predicates.md (mem_operand): Remove code to + delay creating move insns with unscaled indexed addresses + until CSE is not expected. + (move_src_operand): Likewise. + +2025-11-23 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * match.pd (1/x): Use fold_before_rtl_expansion_p. + (`(m1 CMP m2) * d`): Likewise. + +2025-11-23 Pan Li <pan2.li@intel.com> + + * match.pd: Remove unnecessary outer convert and add + c for the outer bit_ior. + +2025-11-23 Pan Li <pan2.li@intel.com> + + * match.pd: Add simplfy to fold outer convert of bit_op + to inner captures. + +2025-11-23 Kugan Vivekanandarajah <kvivekananda@nvidia.com> + + * ipa-split.cc (pass_split_functions::gate): Do not run when + flag_auto_profile. + (pass_feedback_split_functions::gate): Run when flag_auto_profile. + +2025-11-23 Kugan Vivekanandarajah <kvivekananda@nvidia.com> + + * tree-ssa-loop-im.cc (is_self_write): New. + (ref_indep_loop_p): Allow hoisting when aliasing references + form a self write pattern. + +2025-11-22 Jeff Law <jlaw@ventanamicro.com> + + PR rtl-optimization/122701 + * ext-dce.cc (ext_dce_try_optimize_rshift): Emit a fresh reg->reg + copy rather than modifying the existing right shift. + +2025-11-22 Sandra Loosemore <sloosemore@baylibre.com> + + * omp-general.cc (omp_context_selector_matches): Add an optional + bool argument for the code elision case. + * omp-general.h (omp_context_selector_matches): Likewise. + +2025-11-22 Sandra Loosemore <sloosemore@baylibre.com> + + * omp-general.cc (omp_mangle_variant_name): New. + (omp_check_for_duplicate_variant): New. + (omp_copy_trait_set): New. + (omp_trait_selectors_equivalent): New. + (omp_combine_trait_sets): New. + (omp_merge_context_selectors): New. + * omp-general.h (omp_mangle_variant_name): Declare. + (omp_check_for_duplicate_variant): Declare. + (omp_merge_context_selectors): Declare. + +2025-11-22 zhaozhou <zhaozhou@loongson.cn> + + * config/loongarch/loongarch.cc: Extract plus operation. + +2025-11-22 Deng Jianbo <dengjianbo@loongson.cn> + + * config/loongarch/loongarch.md + (*bstrins_w_for_ior_ashift_and_extend): New template. + (*bstrins_d_for_ior_ashift_and): New template. + * config/loongarch/predicates.md (const_uimm63_operand): New + predicate. + +2025-11-22 zhaozhou <zhaozhou@loongson.cn> + + * config/loongarch/lsx.md (lsx_vshuf4i_mem_w_0): Add template. + (lsx_vldrepl_merge_w_0): Ditto. + +2025-11-22 Kees Cook <kees@kernel.org> + + * config/aarch64/aarch64-protos.h (aarch64_indirect_branch_asm): + Declare. + * config/aarch64/aarch64.cc (aarch64_indirect_branch_asm): New + function to generate indirect branch with SLS barrier. + * config/aarch64/aarch64.md (*sibcall_insn): Use + aarch64_indirect_branch_asm. + (*sibcall_value_insn): Likewise. + +2025-11-21 Vladimir N. Makarov <vmakarov@redhat.com> + + PR target/118358 + * lra-constraints.cc (curr_insn_transform): Move insn reloading + constant into a register right before insn using it. + +2025-11-21 Richard Biener <rguenther@suse.de> + + PR tree-optimization/122762 + PR tree-optimization/122736 + PR tree-optimization/122790 + * cgraph.h (cgraph_simd_clone_arg::linear_step): Document + use for SIMD_CLONE_ARG_TYPE_MASK. + * omp-simd-clone.cc (simd_clone_adjust_argument_types): + Record the number of mask arguments in linear_step if + mask_mode is not VOIDmode. + * tree-vect-stmts.cc (vectorizable_simd_clone_call): + Remove num_mask_args computation, use a proper ncopies + to query/register loop masks, use linear_step for the + number of mask arguments when determining the number of + mask elements in a mask argument. + +2025-11-21 Richard Biener <rguenther@suse.de> + + PR tree-optimization/122778 + * tree-vect-stmts.cc (vectorizable_simd_clone_call): Honor + a loop mask when passing the conditional mask with AVX512 + style masking. + +2025-11-21 Jakub Jelinek <jakub@redhat.com> + + PR target/122598 + * config/i386/predicates.md (const_vec_dup_operand): Remove. + * config/i386/sse.md (cond<<insn><mode> with VI1_AVX512VL iterator): + Remove. + +2025-11-21 Eric Botcazou <ebotcazou@adacore.com> + + * doc/invoke.texi (Optimize Options) <-fmalloc-dce>: Remove + trailing space. + (AArch64 Options) <-march>: Fix pasto. + +2025-11-21 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/122773 + * gimplify.cc (collect_fallthrough_labels): Check whether + gimple_goto_dest is a LABEL_DECL before testing VACUOUS_INIT_LABEL_P. + (expand_FALLTHROUGH_r): Likewise. + +2025-11-21 Loeka Rogge <loeka@synopsys.com> + Keith Packard <keithp@keithp.com> + + PR target/120375 + * config/arc/arc.md (*<insn>si3_nobs): merged with <insn>si3_loop. + (<insn>si3_loop): splits to relevant pattern or emits loop assembly. + (<insn>si3_cnt1_clobber): Removes clobber for shift or rotate by + const1. + +2025-11-21 Claudiu Zissulescu <claziss@gmail.com> + Michiel Derhaeg <michiel@synopsys.com> + + * config/arc/arc.md: Modify define_insn_and_split "*extvsi_n_0" + +2025-11-21 Josef Melcr <josef.melcr@suse.com> + + * attr-callback.cc (callback_edge_callee_has_attr): New + function. + * attr-callback.h (callback_edge_callee_has_attr): New function + decl. + * ipa-prop.cc (ipa_compute_jump_functions_for_bb): Don't skip + callback carriers when calculating jump functions. + +2025-11-21 Josef Melcr <josef.melcr@suse.com> + + PR ipa/122768 + * attr-callback.cc (callback_edge_useful_p): Rewrite the + heuristic, now consider clones as well as icf bodies. + +2025-11-21 Deng Jianbo <dengjianbo@loongson.cn> + + * config/loongarch/constraints.md: Update constraint YI to support + more numbers. + * config/loongarch/loongarch-protos.h + (loongarch_const_vector_vrepli): Rename. + (loongarch_const_vector_vldi): Ditto. + * config/loongarch/loongarch.cc (VLDI_NEG_MASK): New macro. + (loongarch_parse_vldi_const): New function to check if numbers can + be generated by {x}vldi instruction. + (loongarch_const_vector_vrepli): Rename. + (loongarch_const_vector_vldi): Use above function. + (loongarch_const_insns): Call renamed function. + (loongarch_split_vector_move_p): Ditto. + (loongarch_output_move): Ditto. + +2025-11-21 zhaozhou <zhaozhou@loongson.cn> + + * config/loongarch/lsx.md: Fix predicate. + +2025-11-20 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/121345 + * gimple-range-phi.cc (phi_group::calculate_using_modifier): Restore + performance loss by being more selective when iterating. + +2025-11-20 Kito Cheng <kito.cheng@sifive.com> + + * config/riscv/riscv-opt-popretz.cc: New file. + * config/riscv/riscv-passes.def: Insert pass_combine_popretz before + pass_shorten_branches. + * config/riscv/riscv-protos.h (make_pass_combine_popretz): New + declaration. + * config/riscv/t-riscv: Add riscv-opt-popretz.o build rule. + * config.gcc (riscv*): Add riscv-opt-popretz.o to extra_objs. + +2025-11-20 Pan Li <pan2.li@intel.com> + + PR target/122692 + * config/riscv/riscv.cc (riscv_expand_ustrunc): Leverage + riscv_extend_to_xmode_reg to take care of src rtx. + +2025-11-20 Tamar Christina <tamar.christina@arm.com> + + * target.def (instruction_selection): New. + * doc/tm.texi.in: Document it. + * doc/tm.texi: Regenerate + * gimple-isel.cc (pass_gimple_isel::execute): Use it. + * targhooks.cc (default_instruction_selection): New. + * targhooks.h (default_instruction_selection): New. + +2025-11-20 Josef Melcr <josef.melcr@suse.com> + + PR ipa/122358 + * cgraph.cc (cgraph_add_edge_to_call_site_hash): Add an early + return when the hashed edge is a callback-carrying edge. + +2025-11-20 Arsen Arsenović <aarsenovic@baylibre.com> + + * doc/rtl.texi (Regs and Memory): Use @table instead of @itemize + for lists with named items. + +2025-11-20 Xinhui Yang <cyan@cyano.uk> + + PR bootstrap/105664 + * Makefile.in (install-driver): detect name collision when + installing the driver program. + +2025-11-20 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> + + * config/i386/sol2.h: Replace USE_GAS by HAVE_GNU_AS. + Replace USE_GLD by HAVE_GNU_LD. + * config/sol2.h: Likewise. + * config/sparc/sol2.h: Likewise. + * config/i386/i386.cc (i386_solaris_elf_named_section) + [TARGET_SOLARIS]: Replace USE_GAS by HAVE_GNU_AS. + * config/ia64/hpux.h: Likewise. + * config.gcc: Remove usegas.h, usegld.h. + * config/usegas.h: Remove. + * config/usegld.h: Remove + +2025-11-20 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> + + * config/sol2.h (LINK_ARCH32_SPEC_BASE): Don't provide -YP + defaults. Rename to ... + (LINK_ARCH_SPEC_BASE): ... this. + (LINK_ARCH32_SPEC): Remove. + (LINK_ARCH64_SPEC_BASE): Remove. + (LINK_ARCH64_SPEC): Rename to ... + (LINK_ARCH_SPEC_1): ... this. + [!USE_GLD]: Simplify map.below4G use. + (LINK_ARCH_ERROR_SPEC): New macro. + (LINK_ARCH32_SPEC): Remove. + (LINK_ARCH_DEFAULT_SPEC): Remove. + (LINK_ARCH_SPEC): Simplify using LINK_ARCH_ERROR_SPEC, + LINK_ARCH_SPEC_1. + (SUBTARGET_EXTRA_SPECS): Remove link_arch32, link_arch64 + link_arch_default. + +2025-11-20 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/lsx.md (vec_perm<mode>): Expand directly with + RTL template. + * config/loongarch/loongarch-protos.h + (loongarch_expand_vec_perm): Delete. + * config/loongarch/loongarch.cc (loongarch_expand_vec_perm): + Delete. + +2025-11-20 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/lasx.md (lasx_xvpermi_d): Add "@". + * config/loongarch/loongarch.cc (loongarch_expand_vec_perm_1): + Use gen_lasx_xvpermi_d instead of + gen_lasx_xvpermi_d_{v32qi,v16hi} to deduplicate the logic. Do + structrual programming instead of goto and label. + +2025-11-20 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/loongarch.cc (loongarch_expand_vec_perm_1): + Clamp the selector using the twice of actual number of elements. + Compare the clamped selector with the element number to get the + blending mask. + +2025-11-20 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/lasx.md (lasx_xvshuf_b): Remove. + (lasx_xvshuf_<lasxfmt_f): Remove. + (unspec): Remove UNSPEC_LASX_XVSHUF and UNSPEC_LASX_XVSHUF_B. + * config/loongarch/lsx.md (lsx_vshuf_b): Remove. + (lsx_vshuf_<lasxfmt_f): Remove. + (unspec): Remove UNSPEC_LSX_VSHUF and UNSPEC_LSX_VSHUF_B. + * config/loongarch/simd.md (unspec): Add UNSPEC_SIMD_VSHUF. + (@simd_vshuf): New define_insn. + (<simd_isa>_<x>vshuf_<simdfmt><_f>): New define_expand. + * config/loongarch/loongarch.cc + (loongarch_try_expand_lsx_vshuf_const): Call gen_simd_vshuf + instead of gen_lasx_xvshuf and gen_lasx_xvshuf_b. + (loongarch_expand_vec_perm_const): Likewise. + +2025-11-20 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/lasx.md (lasx_xvperm_<lasxfmt_f_wd>): Add + "@" for gen_lasx_xvperm helper. + * config/loongarch/loongarch.cc (loongarch_expand_vec_perm_1): + Call gen_lasx_xvperm to unify V8SF and V8SI handling. + +2025-11-20 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/loongarch.cc (loongarch_expand_vec_perm_1): + Use lasx_xvpackev_h (mask * 2, mask * 2 + 1) to "expand" the + V4DI selector to V8SI. + +2025-11-20 Xi Ruoyao <xry111@xry111.site> + + PR target/122695 + * config/loongarch/loongarch.cc (loongarch_expand_vec_perm_1): + Simplify and fix the logic preventing the xvshuf.* unpredictable + behavior. + +2025-11-19 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/122756 + * gimple-range-fold.cc (range_of_ssa_name_with_loop_info): Do + not invoke SCEV if already in a SCEV call. + +2025-11-19 Martin Liska <martin.liska@hey.com> + + * common.opt.urls: Include -fuse-ld=wild + +2025-11-19 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR tree-optimization/122754 + * gimple-fold.cc (get_range_strlen_tree): Use POINTER_TYPE_P instead + of direct comparing to POINTER_TYPE. + * gimple-ssa-sprintf.cc (format_integer): Likewise. + * gimple-ssa-warn-access.cc (maybe_warn_nonstring_arg): Likewise. + * gimple-ssa-warn-restrict.cc (pass_wrestrict::check_call): Likewise. + * tree-ssa-strlen.cc (maybe_set_strlen_range): Likewise. + (is_strlen_related_p): Likewise. + (strlen_pass::handle_assign): Likewise. + +2025-11-19 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * tree-ssa-dce.cc (simple_dce_from_worklist): Use FOR_EACH_IMM_USE_FAST instead of + FOR_EACH_IMM_USE_STMT. + +2025-11-19 Alfie Richards <alfie.richards@arm.com> + + PR target/122763 + * config/aarch64/aarch64.cc (aarch64_layout_arg): Return NULL_RTX for + arguments of size 0. + (aarch64_function_arg_advance): Remove assert. + +2025-11-19 Alfie Richards <alfie.richards@arm.com> + + * doc/extend.texi (preserve_none): Minor grammar fix. + +2025-11-19 Martin Liska <martin.liska@hey.com> + + * collect2.cc (main): Add wild linker to -fuse-ld. + * common.opt: Likewise. + * configure: Regenerate. + * configure.ac: Add detection for wild linker. + * doc/invoke.texi: Document -fuse-ld=wild. + * gcc.cc (driver_handle_option): Support -fuse-ld=wild. + * opts.cc (common_handle_option): Likewise. + +2025-11-19 Tamar Christina <tamar.christina@arm.com> + + * config/aarch64/aarch64-sve.md (vec_extract<mode><v128>, + vec_extract<mode><v64>): New. + * config/aarch64/iterators.md (V64, v64): New. + * config/aarch64/predicates.md (const0_to_1_operand): New. + +2025-11-19 Jeff Law <jlaw@ventanamicro.com> + + * config/riscv/riscv-string.cc (riscv_expand_block_move_scalar): + Fix signed vs unsigned warning. + +2025-11-19 Richard Biener <rguenther@suse.de> + + * tree-vect-stmts.cc (vectorizable_load): Make dr_chain + an auto_vec, move down to where we use it to avoid creating + it twice. + +2025-11-19 Richard Biener <rguenther@suse.de> + + PR tree-optimization/122722 + * tree-vect-slp.cc (vect_analyze_slp_reductions): New + function, split out from vect_analyze_slp. Try SLP + sub-groups. + (vect_analyze_slp_reduction_group): New helper. + +2025-11-19 Richard Biener <rguenther@suse.de> + + PR tree-optimization/122747 + * tree-vect-stmts.cc (vectorizable_call): Handle reduction + operations that are already conditional. + +2025-11-19 Jakub Jelinek <jakub@redhat.com> + + * tree-ssanames.cc (get_known_nonzero_bits): Fix a pasto in + function comment, this function returns 0 if unknown rather + than -1. + +2025-11-19 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/122184 + * tree-ssa-live.cc (remove_unused_locals): Drop .DEFERRED_INIT + calls with MEM_REF lhs based on uninitialized SSA_NAME. + +2025-11-19 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> + + * genmultilib: Check $enable_multilib to define DISABLE_MULTILIB. + +2025-11-19 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> + + * config/sol2.h: Check USE_GLD instead of USE_GNU_LD. + +2025-11-19 Avinash Jayakar <avinashd@linux.ibm.com> + + PR target/119130 + * config/rs6000/altivec.md (convert_4f32_8f16): Use same operand + order for both endian format. + +2025-11-19 Haochen Jiang <haochen.jiang@intel.com> + + * common/config/i386/i386-common.cc: Adjust to P_PROC_AVX10_1. + * config/i386/driver-i386.cc (host_detect_local_cpu): + Move Nova Lake to under AVX512 part. + * config/i386/i386.h (PTA_NOVALAKE): Add AVX10.1, AVX10.2, + APX_F and MOVRS. + * config/i386/x86-tune-sched.cc (ix86_issue_rate): Set to 8. + * config/i386/x86-tune.def (X86_TUNE_AVX256_OPTIMAL): Add Nova + Lake. + * doc/invoke.texi: Adjust documentation. + +2025-11-18 Edwin Lu <ewlu@rivosinc.com> + + * config/riscv/riscv-string.cc (riscv_expand_block_move_scalar): + Add length check. + (expand_block_move): Ditto. + (expand_vec_setmem): Ditto. + * config/riscv/riscv.opt: Add param flags. + +2025-11-18 Christophe Lyon <christophe.lyon@linaro.org> + + * config/arm/arm_mve.h (__ARM_mve_typeid): Delete. + (__ARM_mve_coerce): Delete. + (__ARM_mve_coerce_i_scalar): Delete. + (__ARM_mve_coerce_s8_ptr): Delete. + (__ARM_mve_coerce_u8_ptr): Delete. + (__ARM_mve_coerce_s16_ptr): Delete. + (__ARM_mve_coerce_u16_ptr): Delete. + (__ARM_mve_coerce_s32_ptr): Delete. + (__ARM_mve_coerce_u32_ptr): Delete. + (__ARM_mve_coerce_s64_ptr): Delete. + (__ARM_mve_coerce_u64_ptr): Delete. + (__ARM_mve_coerce_f_scalar): Delete. + (__ARM_mve_coerce_f16_ptr): Delete. + (__ARM_mve_coerce_f32_ptr): Delete. + +2025-11-18 Christophe Lyon <christophe.lyon@linaro.org> + + * config/arm/arm-mve-builtins-shapes.cc (build_one): Add + which_overload parameter. + (inherent): Derive from overloaded_base<0>. Add support for + overloaded version. + * config/arm/arm-mve-builtins-shapes.h (inherent): Update comment. + * config/arm/arm-mve-builtins.cc (add_unique_function): Add + support for new which_overload parameter. + (pop_and_resolve_to): New. + * config/arm/arm-mve-builtins.h (NONOVERLOADED_FORM) + (OVERLOADED_FORM): New. + (add_unique_function): Update prototype. + (pop_and_resolve_to): New prototype. + * config/arm/arm_mve.h (vuninitializedq): Delete. + (vuninitializedq_u8): Delete. + (vuninitializedq_u16): Delete. + (vuninitializedq_u32): Delete. + (vuninitializedq_u64): Delete. + (vuninitializedq_s8): Delete. + (vuninitializedq_s16): Delete. + (vuninitializedq_s32): Delete. + (vuninitializedq_s64): Delete. + (vuninitializedq_f16): Delete. + (vuninitializedq_f32): Delete. + (__arm_vuninitializedq): Delete. + +2025-11-18 Christophe Lyon <christophe.lyon@linaro.org> + + * config/arm/arm-mve-builtins-base.cc (class + mve_function_vset_vget_lane): New. + (vgetq_lane, vsetq_lane): New. + * config/arm/arm-mve-builtins-base.def (vgetq_lane, vsetq_lane): + New. + * config/arm/arm-mve-builtins-base.h (vgetq_lane, vsetq_lane): + New. + * config/arm/arm-mve-builtins-shapes.cc (struct getq_lane) + (setq_lane): New. + * config/arm/arm-mve-builtins-shapes.h (getq_lane, setq_lane): + New. + * config/arm/arm_mve.h (vsetq_lane): Delete. + (vgetq_lane): Delete. + (vsetq_lane_f16): Delete. + (vsetq_lane_f32): Delete. + (vsetq_lane_s16): Delete. + (vsetq_lane_s32): Delete. + (vsetq_lane_s8): Delete. + (vsetq_lane_s64): Delete. + (vsetq_lane_u8): Delete. + (vsetq_lane_u16): Delete. + (vsetq_lane_u32): Delete. + (vsetq_lane_u64): Delete. + (vgetq_lane_f16): Delete. + (vgetq_lane_f32): Delete. + (vgetq_lane_s16): Delete. + (vgetq_lane_s32): Delete. + (vgetq_lane_s8): Delete. + (vgetq_lane_s64): Delete. + (vgetq_lane_u8): Delete. + (vgetq_lane_u16): Delete. + (vgetq_lane_u32): Delete. + (vgetq_lane_u64): Delete. + (__ARM_NUM_LANES): Delete. + (__ARM_LANEQ): Delete. + (__ARM_CHECK_LANEQ): Delete. + (__arm_vsetq_lane_s16): Delete. + (__arm_vsetq_lane_s32): Delete. + (__arm_vsetq_lane_s8): Delete. + (__arm_vsetq_lane_s64): Delete. + (__arm_vsetq_lane_u8): Delete. + (__arm_vsetq_lane_u16): Delete. + (__arm_vsetq_lane_u32): Delete. + (__arm_vsetq_lane_u64): Delete. + (__arm_vgetq_lane_s16): Delete. + (__arm_vgetq_lane_s32): Delete. + (__arm_vgetq_lane_s8): Delete. + (__arm_vgetq_lane_s64): Delete. + (__arm_vgetq_lane_u8): Delete. + (__arm_vgetq_lane_u16): Delete. + (__arm_vgetq_lane_u32): Delete. + (__arm_vgetq_lane_u64): Delete. + (__arm_vsetq_lane_f16): Delete. + (__arm_vsetq_lane_f32): Delete. + (__arm_vgetq_lane_f16): Delete. + (__arm_vgetq_lane_f32): Delete. + (__arm_vsetq_lane): Delete. + (__arm_vgetq_lane): Delete. + * config/arm/mve.md (mve_vec_extract<mode><V_elem_l>): Add '@' + prefix. + (mve_vec_set<mode>_internal): Likewise. + +2025-11-18 Christophe Lyon <christophe.lyon@linaro.org> + + * doc/extend.texi (Half-precision Floating-point): __fp16 is now + always available on arm. Move x86 paragraph closer to the rest of + the x86 information, and make it use present tense. + +2025-11-18 Christophe Lyon <christophe.lyon@linaro.org> + + PR target/117814 + * config/arm/arm-builtins.cc (arm_init_fp16_builtins): Always + register __fp16 type. + * config/arm/arm-mve-builtins.cc (register_builtin_tuple_types): + Remove special handling when TARGET_HAVE_MVE_FLOAT is false. + (register_vector_type): Likewise. + (register_builtin_tuple_types): Likewise. + * config/arm/arm-opts.h (arm_fp16_format_type): Add + ARM_FP16_FORMAT_DEFAULT. + * config/arm/arm.cc (arm_vector_mode_supported_p): Accept + floating-point vector modes even if TARGET_HAVE_MVE_FLOAT is + false. + (arm_option_reconfigure_globals): Apply ARM_FP16_FORMAT_NONE if + requested. + * config/arm/arm.opt (mfp16-format): Default to + ARM_FP16_FORMAT_DEFAULT. + * config/arm/arm_mve_types.h (float16_t, float32_t): Define + unconditionally. + * doc/sourcebuild.texi (ARM-specific attributes): Document + arm_v8_1m_mve_nofp_ok. + +2025-11-18 Richard Biener <rguenther@suse.de> + + PR tree-optimization/122736 + * tree-vect-stmts.cc (vectorizable_simd_clone_call): Compute + num_mask_args for all mask modes. Pass the mask vector + type to vect_record_loop_mask and adjust ncopies according + to the number of mask arguments. + +2025-11-18 Austin Law <austinkylelaw@gmail.com> + + * config/riscv/riscv-cores.def: Add RISCV_TUNE and RISCV_CORE entries + for the spacemit-x60 design. + * config/riscv/riscv-opts.h (riscv_microarchitecture_type): Add entry + for spacemit-x60 design. + * config/riscv/riscv.cc (spacemit_x60_tune_info): New tune structure + for the spacemit-x60 design. + * config/riscv/riscv.md (tune): Add spacemit_x60. + Include spacemit-x60.md. + * config/riscv/spacemit-x60.md: New file + * doc/riscv-mtune.texi: Regenerate. + * doc/riscv-mcpu.texi: Regenerate. + +2025-11-18 Richard Biener <rguenther@suse.de> + + PR tree-optimization/122723 + * tree-vect-loop.cc (vect_reduction_update_partial_vector_usage): + Handle incoming .COND_* operation. + (vect_transform_reduction): Likewise. Handle .COND_* + operation when not using COND_EXPR masking in a masked loop. + +2025-11-18 Richard Biener <rguenther@suse.de> + + PR tree-optimization/122723 + * tree-vect-stmts.cc (supportable_widening_operation): + Correct optab to query in the multi-step case when it is + supposed to hit the sbool case. + +2025-11-18 liuhongt <hongtao.liu@intel.com> + + PR target/103750 + * config/i386/sse.md (*<avx512>_eq<mode>3_and15): New + define_insn. + (*avx512vl_eqv2di_and3): Ditto. + * config/i386/i386.md (*ior<mode>_ccz_1): Fix the typo in the + comments above. + +2025-11-17 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/122626 + * tree-logical-location.cc + (tree_logical_location_manager::get_parent): Return null when + TYPE_CONTEXT is a TRANSLATION_UNIT_DECL so that we don't fail + the assertion in assert_valid_tree. + +2025-11-17 Evgeny Karpov <evgeny@kmaps.co> + + PR diagnostics/122666 + * config/i386/x-mingw32 (LIBS): Add -lws2_32 + * diagnostics/sarif-sink.cc: Move sockets includes to before + config.h and support __MINGW32__. + +2025-11-17 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR middle-end/97894 + * attr-fnspec.h (attr_fnspec): arg_idx, known_p, arg_specified_p, + arg_direct_p, arg_used_p, arg_readonly_p, + arg_maybe_read_p, arg_maybe_written_p, + arg_max_access_size_given_by_arg_p, + arg_access_size_given_by_type_p, + arg_copied_to_arg_p, arg_noescape_p, returns_arg, + returns_noalias_p, global_memory_read_p, + global_memory_written_p, errno_maybe_written_p, arg_eaf_flags, + and get_str as const methods. + +2025-11-17 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * tree-cfgcleanup.cc (maybe_remove_forwarder_block): Move a few + checks earlier. + +2025-11-17 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * tree-cfgcleanup.cc (tree_forwarder_block_p): Merge this and ... + (remove_forwarder_block): This into ... + (maybe_remove_forwarder_block): Here. + (cleanup_tree_cfg_bb): Call only maybe_remove_forwarder_block. + (pass_merge_phi::execute): Likewise. + +2025-11-17 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * tree-cfgcleanup.cc (pass_merge_phi::execute): Add stats for the removed + blocks. + +2025-11-17 Jeff Law <jlaw@ventanamicro.com> + + PR rtl-optimization/122575 + * simplify-rtx.cc (simplify_context::simplify_relational_operation_1): + Use correct mode for simplified IOR expression inside equality + conditional. + +2025-11-17 Xi Ruoyao <xry111@xry111.site> + + * simplify-rtx.cc (simplify_const_binary_operation): Simplify + VEC_CONCAT two constant vectors. + +2025-11-17 Richard Biener <rguenther@suse.de> + + * tree-ssa-loop-im.cc (move_computations_worker): Avoid newline + between 'Moving statement' and actual statement dump in dumpfile. + +2025-11-17 Richard Biener <rguenther@suse.de> + + * tree-ssa-loop-im.cc (fill_always_executed_in): Skip + blocks not in loops when looking for possibly not returning + calls. + +2025-11-17 Victor Do Nascimento <vicdon01@ip-10-248-139-187.eu-west-1.compute.internal> + + * cfgloop.cc (loop_exits_to_bb_p): Change return type. + (loop_exits_from_bb_p): Likewise. + * cfgloop.h: (loop_exits_to_bb_p): Likewise. + (loop_exits_from_bb_p): Likewise. + +2025-11-17 Alfie Richards <alfie.richards@arm.com> + + * doc/extend.texi: (ARM C Language Extensions (ACLE)) Update ACLE URL + and description. + +2025-11-17 Artemiy Volkov <artemiy.volkov@arm.com> + + * tree-ssa-forwprop.cc (optimize_vector_load): Inhibit + optimization when all uses are through subvectors without + extension. + +2025-11-17 Jakub Jelinek <jakub@redhat.com> + + * tree-core.h (enum built_in_function): Avoid arithmetics or + bitwise operations between enumerators from different enums. + * lto-streamer.h (lto_tag_is_gimple_code_p): Likewise. + * gimple.h (gimple_omp_atomic_set_memory_order): Likewise. + * common/config/i386/i386-cpuinfo.h (M_CPU_SUBTYPE_START, + M_CPU_TYPE): Likewise. + * tree-complex.cc (expand_complex_libcall): Likewise. + * ipa-modref-tree.h (modref_access_node::operator ==): Change + argument type from modref_access_node & to + const modref_access_node &. + * ipa-modref-tree.cc (modref_access_node::operator ==): Likewise. + +2025-11-17 Richard Biener <rguenther@suse.de> + + PR tree-optimization/122573 + * config/i386/i386.cc (ix86_vector_costs::finish_cost): Avoid + using masked epilogues when an SSE epilogue would have a VF of one. + +2025-11-17 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> + + * configure.ac (gcc_cv_ld_compress_debug) <*-*-solaris2*>: Check + for zstd compression support. + * configure: Regenerate. + * doc/invoke.texi (Debugging Options, gz): Document zstd. + +2025-11-16 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/121345 + * gimple-range-phi.cc (phi_group::phi_group): Add modifier name. + (phi_group::is_modifier_p): Set modifier stmt operand name. + (phi_group::calculate_using_modifier): Bound the iteration range + by known global range. + (phi_analyzer::process_phi): Allow single PHIS if they meet certain + criteria. + * gimple-range-phi.h (m_modifier_name): New member. + (is_modifier_p): Adjust prototype. + +2025-11-16 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-fold.cc (fold_using_range::range_of_phi): Remove + the PHI analysis query. + * gimple-range-phi.cc (phi_analysis_object): Delete. + (phi_analysis_initialize): Delete. + (phi_analysis_finalize): Delete. + (phi_analysis_available_p): Delete. + (phi_analysis): Invoke a phi analyzer. + (phi_analyzer::phi_analyzer): Preprocess all phi nodes and set + global values for them in a query. + (phi_analyzer::process_phi): Use query, and export any inital + values found to the query. + * gimple-range-phi.h (m_global): Delete. + (phi_analysis_initialize): Delete. + (phi_analysis_finalize): Delete. + (phi_analysis_available_p): Delete. + (phi_analysis): Change prototype. + * tree-vrp.cc (execute_ranger_vrp): Call phi_analysis. + +2025-11-16 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-cache.cc (ranger_cache::update_consumers): New. + * gimple-range-cache.h (update_consumers): New prototype. + * gimple-range-fold.cc (fur_depend::fur_depend): Add cache ptr. + (fur_depend::register_relation): call update_consumers. + * gimple-range-fold.h (fur_depend): Add a cache pointer. + * gimple-range.cc (gimple_ranger::fold_range_internal): Add cache ptr. + +2025-11-16 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range.cc (gimple_ranger::update_range_info): New. + * gimple-range.h (update_range_info): New prototype. + * tree-ssanames.cc (set_range_info): Update the range info for + the current range query. + * value-query.h (update_range_info): New prototype. + * value-query.cc (update_range_info): New default stub. + +2025-11-16 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * tree-cfgcleanup.cc (tree_forwarder_block_p): Restore check on + LOOPS_HAVE_PREHEADERS. + +2025-11-16 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> + + * config/sol2.h (MD_EXEC_PREFIX): Remove. + +2025-11-16 Richard Biener <rguenther@suse.de> + + * tree-vect-loop.cc (_loop_vec_info::_loop_vec_info): + Initialize can_use_partial_vectors_p to true. + (vect_determine_partial_vectors_and_peeling): Add masked_p + parameter and honor it. + (vect_analyze_loop_2): Pass through masked_p. + (vect_analyze_loop_1): Pass down masked_p. + (vect_analyze_loop): Simplify check on possible masking of + the epilog when there's no .WHILE_ULT. + +2025-11-16 Richard Biener <rguenther@suse.de> + + * tree-vect-loop.cc (vect_determine_partial_vectors_and_peeling): + Remove resetting of LOOP_VINFO_USING_SELECT_VL_P. + (vect_analyze_loop_2): Decide on partial vectors before + deciding on decrementing IV or .SELECT_VL usage. + +2025-11-16 Richard Biener <rguenther@suse.de> + + * tree-vectorizer.h (vect_determine_partial_vectors_and_peeling): + Remove. + (vect_need_peeling_or_partial_vectors_p): Declare. + * tree-vect-loop.cc (vect_determine_partial_vectors_and_peeling): + Make static. + (vect_need_peeling_or_partial_vectors_p): Export. + * tree-vect-loop-manip.cc (vect_do_peeling): Do not call + vect_determine_partial_vectors_and_peeling but instead + re-compute LOOP_VINFO_PEELING_FOR_NITER using + vect_need_peeling_or_partial_vectors_p. + +2025-11-16 Richard Biener <rguenther@suse.de> + + * tree-vectorizer.h (_loop_vec_info::epil_using_partial_vectors_p): + Remove. + (LOOP_VINFO_EPIL_USING_PARTIAL_VECTORS_P): Likewise. + * tree-vect-loop.cc (_loop_vec_info::_loop_vec_info): + Do not initialize epil_using_partial_vectors_p. + (vect_determine_partial_vectors_and_peeling): Do not set it. + +2025-11-16 Lewis Hyatt <lhyatt@gmail.com> + + * diagnostics/context.cc (num_digits): Change argument type from + `int' to `uint64_t'. + (test_num_digits): Add test for 64-bit argument. + * diagnostic.h (num_digits): Adjust prototype. + * input.cc (write_digit): Accept argument in range 0-9 instead of + an arbitrary int. + (write_digit_row): Adjust to change in write_digit(). + +2025-11-15 Jason Xu <bravejason@outlook.com> + + * config.gcc (aarch64-*-mingw*): Set use_gcc_stdint to wrap. + +2025-11-15 Jeff Law <jlaw@ventanamicro.com> + + * config/riscv/riscv.cc (risc_legitimize_move): Use convert_modes + rather than gen_extend_insn for most cases. + * config/riscv/riscv.md (addv<mode>4): Likewise. + (uaddv<mode>4, subv<mode>4, usubv<mode>4): Likewise. + (mulv<mode>4, umulv<mode>4): Likewise. + * config/riscv/sync.md (atomic_compare_and_swap<mode>): Likewise. + +2025-11-15 Karl Meakin <karl.meakin@arm.com> + + * config/aarch64/aarch64.md (mov<GPF:mode><GPI:mode>cc): Delete. + +2025-11-15 Karl Meakin <karl.meakin@arm.com> + + * config/aarch64/aarch64.md(mov<ALLI_GPF:mode>cc): Use new predicate. + (mov<GPF:mode><GPI:mode>cc): Likewise. + (<neg_not_op><mode>cc): Likewise. + * config/aarch64/predicates.md (aarch64_comparison_operator_cc): + New predicate. + +2025-11-15 Karl Meakin <karl.meakin@arm.com> + + * config/aarch64/aarch64.md (mov<ALLI_GPF:mode>): Delete + redundant check. + (mov<GPF:mode><GPI:mode>cc): Likewise. + (<neg_not_op><mode>cc): Likewise. + +2025-11-15 Karl Meakin <karl.meakin@arm.com> + + * config/aarch64/aarch64.md (mov<ALLI>cc): Merge with ... + (mov<ALLI>cc): ... this. + * config/aarch64/iterators.md(ALLI_GPF): New mode iterator. + +2025-11-15 Karl Meakin <karl.meakin@arm.com> + + * config/aarch64/aarch64.md(mov<GPF>cc): Accept MODE_CC + conditions directly; reject QI/HImode conditions. + +2025-11-14 Kuan-Lin Chen <rufus@andestech.com> + + * config/riscv/riscv.cc (andes_25_tune_info): Add prefer-agnostic. + +2025-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + * config/arm/arm-mve-builtins-base.cc (enum which_scalar_shift): + Add ss_SQRSHR, ss_SQSHL, ss_SRSHR, ss_UQRSHL, ss_UQSHL, and + ss_URSHR. + (mve_function_scalar_shift): Add support for ss_SQRSHR, ss_SQSHL, + ss_SRSHR, ss_UQRSHL, ss_UQSHL, and ss_URSHR. + (sqrshr, sqshl, srshr, uqrshl, uqshl, urshr): New. + * config/arm/arm-mve-builtins-base.def (sqrshr, sqshl, srshr) + (uqrshl, uqshl, urshr): New. + * config/arm/arm-mve-builtins-base.h (sqrshr, sqshl, srshr) + (uqrshl, uqshl, urshr): New. + * config/arm/arm-mve-builtins-shapes.cc (scalar_s32_shift): New. + (scalar_s32_shift_imm): New. + (scalar_u32_shift): New. + (scalar_u32_shift_imm): New. + * config/arm/arm-mve-builtins-shapes.h (scalar_s32_shift): New. + (scalar_s32_shift_imm): New. + (scalar_u32_shift): New. + (scalar_u32_shift_imm): New. + * config/arm/arm_mve.h (sqrshr): Delete. + (sqshl): Delete. + (srshr): Delete. + (uqrshl): Delete. + (uqshl): Delete. + (urshr): Delete. + (__arm_uqrshl): Delete. + (__arm_sqrshr): Delete. + (__arm_uqshl): Delete. + (__arm_urshr): Delete. + (__arm_sqshl): Delete. + (__arm_srshr): Delete. + * config/arm/mve.md (mve_sqshl_si, mve_srshr_si): Fix operand 1 + mode. + +2025-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + * config/arm/arm-mve-builtins-base.cc (enum which_scalar_shift): + Add ss_SQSHLL, ss_SRSHRL, ss_UQSHLL, ss_URSHRL. + (mve_function_scalar_shift): Add support for ss_SQSHLL, ss_SRSHRL, + ss_UQSHLL, ss_URSHRL. + * config/arm/arm-mve-builtins-base.def (sqshll, srshrl, uqshll) + (urshrl): New. + * config/arm/arm-mve-builtins-base.h (sqshll, srshrl, uqshll) + (urshrl): New. + * config/arm/arm-mve-builtins-shapes.cc (scalar_s64_shift_imm) + (scalar_u64_shift_imm): New. + * config/arm/arm-mve-builtins-shapes.h (scalar_s64_shift_imm) + (scalar_u64_shift_imm): New. + * config/arm/arm_mve.h (sqshll): Delete. + (srshrl): Delete. + (uqshll): Delete. + (urshrl): Delete. + (__arm_uqshll): Delete. + (__arm_urshrl): Delete. + (__arm_srshrl): Delete. + (__arm_sqshll): Delete. + +2025-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + * config/arm/arm-mve-builtins-base.cc (enum which_scalar_shift): + Add ss_SQRSHRL, ss_SQRSHRL_SAT48. + (mve_function_scalar_shift): Add support for ss_SQRSHRL, + ss_SQRSHRL_SAT48. + (sqrshrl, sqrshrl_sat48): New. + * config/arm/arm-mve-builtins-base.def (sqrshrl, sqrshrl_sat48): New. + * config/arm/arm-mve-builtins-base.h (sqrshrl, sqrshrl_sat48): New. + * config/arm/arm_mve.h (sqrshrl): Delete. + (sqrshrl_sat48): Delete. + (__arm_sqrshrl): Delete. + (__arm_sqrshrl_sat48): Delete. + * config/arm/mve.md (mve_sqrshrl_sat<supf>_di): Add '@' prefix. + +2025-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + * config/arm/arm-mve-builtins-base.cc (enum which_scalar_shift): + Add ss_UQRSHLL, ss_UQRSHLL_SAT48. + (mve_function_scalar_shift): Add support for ss_UQRSHLL, + ss_UQRSHLL_SAT48. + * config/arm/arm-mve-builtins-base.def (uqrshll, uqrshll_sat48): + New. + * config/arm/arm-mve-builtins-base.h (uqrshll, uqrshll_sat48): + New. + * config/arm/arm_mve.h (uqrshll): Delete. + (uqrshll_sat48): Delete. + (__arm_uqrshll): Delete. + (__arm_uqrshll_sat48): Delete. + * config/arm/mve.md (mve_uqrshll_sat<supf>_di): Add '@' prefix. + +2025-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + * config/arm/arm-mve-builtins-base.cc (class mve_function_vpnot): New. + (vpnot): New. + * config/arm/arm-mve-builtins-base.def (vpnot): New. + * config/arm/arm-mve-builtins-base.h (vpnot): New. + * config/arm/arm-mve-builtins-shapes.cc (struct vpnot): New. + * config/arm/arm-mve-builtins-shapes.h (vpnot): New. + * config/arm/arm_mve.h (vpnot): Delete. + (__arm_vpnot): Delete. + +2025-11-14 Filip Kastl <fkastl@suse.cz> + + * doc/invoke.texi: Remove mention of switch-lower-slow-alg-max-cases. + * params.opt: Remove switch-lower-slow-alg-max-cases. + +2025-11-14 Uros Bizjak <ubizjak@gmail.com> + + * config/i386/i386.md (*sub<mode>_3): + Remove 'i' from operand 0 constraint. + +2025-11-14 Richard Biener <rguenther@suse.de> + + PR ipa/122663 + * ipa-param-manipulation.cc (purge_all_uses): Collect + stmts to remove and process that list in reverse. + +2025-11-14 Richard Biener <rguenther@suse.de> + + PR tree-optimization/122573 + * tree-vect-slp.cc (vect_build_slp_tree_1): Support + groups of invariant loads. + (vect_build_slp_tree_2): Likewise. + (vect_transform_slp_perm_load_1): Likewise. + * tree-vect-stmts.cc (vectorizable_load): Handle non-splat + SLP for invaraint loads. + +2025-11-14 Richard Biener <rguenther@suse.de> + + PR tree-optimization/122680 + * tree-vect-stmts.cc (vectorizable_conversion): Avoid range + queries during transform. + +2025-11-14 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> + + PR target/121458 + PR target/121457 + * configure.ac: Fix typos. + <*-*-solaris2*>: Require GNU ld 2.30. + (comdat_group) <*-*-solaris2.1[1-9]*>: Always set to yes. + (ld_ix86_gld_32_opt): Only use -melf_i386_sol2 for Solaris target. + (ld_ix86_gld_64_opt): Likewise with -melf_x86_64_sol. + (gcc_cv_ld_eh_frame_hdr) <*-*-solaris2*>: Likewise. + (gcc_cv_ld_pie) <*-*-solaris2*>: Remove special cases. + (gcc_cv_ld_compress_debug) <*-*-solaris2*>: Remove guard. + (gcc_cv_ld_as_needed): Simplify guard. + (gcc_cv_ld_sol2_emulation): Remove. + (gcc_cv_solaris_crts): Remove. + * configure: Regenerate. + * config.in: Regenerate. + * config/sol2.h (STARTFILE_CRTBEGIN_SPEC): Remove !HAVE_LD_PIE + support. + (ENDFILE_CRTEND_SPEC): Likewise. + (LD_PIE_SPEC): Likewise. + [USE_GLD] (LINK_EH_SPEC): Set unconditionally. + * config/i386/sol2.h [USE_GLD]: Remove !HAVE_LD_SOL2_EMULATION + support. + * config/sparc/sol2.h: Likewise. + * doc/install.texi (Specific, *-*-solaris2*): Update bundled gcc + versions. + Raise required binutils version. + Remove binutils 2.44 caveat. + +2025-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + PR target/122216 + * config/arm/arm-mve-builtins-base.cc (enum which_scalar_shift): New. + (mve_function_scalar_shift): New. + (asrl, lsll): New. + * config/arm/arm-mve-builtins-base.def (asrl, lsll): New. + * config/arm/arm-mve-builtins-base.h (asrl, lsll): New. + * config/arm/arm_mve.h (asrl): Delete. + (lsll): Delete. + (__arm_asrl): Delete. + (__arm_lsll): Delete. + +2025-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + PR target/122216 + * config/arm/arm-mve-builtins-shapes.cc (scalar_s64_shift): New. + (scalar_u64_shift): New. + * config/arm/arm-mve-builtins-shapes.h: Likewise. + +2025-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + PR target/122216 + * config/arm/arm.md (ashldi3, ashrdi3): Force shift amount into + QImode. + * config/arm/constraints.md: Fix comment, Pg is valid in Thumb-2 + state only. + * config/arm/mve.md (mve_asrl): Handle various shift amount ranges. + (mve_asrl_imm, mve_asrl_internal): New patterns. + (mve_lsll): Handle various shift amount ranges. + (mve_lsll_imm, mve_lsll_internal): New patterns. + +2025-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + PR target/122216 + * config/arm/thumb2.md (thumb2_asrl, thumb2_lsll, thumb2_lsrl): + Move to ... + * config/arm/mve.md (mve_asrl, mve_lsll, mve_lsrl): ... here. Use + match_operand instead of match_dup. + * config/arm/arm.md (ashldi3, ashrdi3, lshrdi3): Remove useless + copy. Update for new prototype. + +2025-11-14 Xi Ruoyao <xry111@xry111.site> + + * configure: Regenerate. + +2025-11-14 zhaozhou <zhaozhou@loongson.cn> + + * config/loongarch/lasx.md (lasx_xvbsrl_d_f): New template. + * config/loongarch/loongarch.cc (emit_reduc_half): Replace insn. + +2025-11-14 zhaozhou <zhaozhou@loongson.cn> + + * config/loongarch/predicates.md: Update ops. + +2025-11-14 zhaozhou <zhaozhou@loongson.cn> + + * config.gcc: Add target_gtfiles. + * config/loongarch/loongarch-builtins.cc: Add header file. + +2025-11-13 Alexandre Oliva <oliva@adacore.com> + Olivier Hainque <hainque@adacore.com> + + * config/vxworks/base/b_NULL.h: New. + * config.gcc (extra_headers) <*-*-vxworks*>: Add it. + * Makefile.in (stmp-int-hdrs): Support /././ markers in USER_H + to mark the beginning of the install name. Document. + * doc/sourcebuild.texi (Headers): Document /././ marker. + +2025-11-13 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * tree-cfgcleanup.cc (tree_forwarder_block_p): Remove must argument. + (remove_forwarder_block): Add can_split + argument. Handle the splitting case (iff phis in bb). + (cleanup_tree_cfg_bb): Update argument to tree_forwarder_block_p. + (remove_forwarder_block_with_phi): Remove. + (pass_merge_phi::execute): Update argument to tree_forwarder_block_p + and call remove_forwarder_block instead of remove_forwarder_block_with_phi. + +2025-11-13 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR tree-optimization/122493 + * tree-cfgcleanup.cc (tree_forwarder_block_p): Change bool argument + to a must have phi and allow phis if it is false. + (remove_forwarder_block): Add support for merging of forwarder blocks + with phis. + +2025-11-13 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * tree-cfg.cc (copy_phi_arg_into_existing_phi): Use the original location + if the mapped location is unknown. + +2025-11-13 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * tree-cfg.cc (copy_phi_arg_into_existing_phi): New use_map argument. + * tree-cfg.h (copy_phi_arg_into_existing_phi): Update declaration. + * tree-cfgcleanup.cc (remove_forwarder_block_with_phi): Use + copy_phi_arg_into_existing_phi instead of inlining it. + +2025-11-13 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * tree-cfgcleanup.cc (remove_forwarder_block): Move + variable declaration ei into for loop. + +2025-11-13 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * tree-cfgcleanup.cc (remove_forwarder_block_with_phi): Use + edge iterator instead of while loop. + +2025-11-13 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * tree-cfgcleanup.cc (remove_forwarder_block): Remove check + on the available dominator information. + +2025-11-13 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * tree-cfgcleanup.cc (tree_forwarder_block_p): Reject bb which has a single + predecessor which has a single successor. + +2025-11-13 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * tree-cfgcleanup.cc (pass_merge_phi::execute): Move + check for abnormal or no phis to remove_forwarder_block_with_phi + and the check on dominated to tree_forwarder_block_p. + (remove_forwarder_block_with_phi): here. + +2025-11-13 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * tree-cfgcleanup.cc (remove_forwarder_block_with_phi): Remove check on non-local label. + (remove_forwarder_block): Remove check on non-label/eh landing pad. + (tree_forwarder_block_p): Add check on lable for an eh landing pad. + +2025-11-13 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * tree-cfgcleanup.cc (remove_forwarder_block): Remove check for infinite loop. + (remove_forwarder_block_with_phi): Likewise. Also remove check for loop header. + +2025-11-13 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * tree-cfgcleanup.cc (pass_merge_phi::execute): Remove worklist. + +2025-11-13 Jeff Law <jlaw@ventanamicro.com> + + * ext-dce.cc (ext_dce_try_optimize_rshift): New function to optimize a + shift pair implementing a zero/sign extension. + (ext_dce_try_optimize_extension): Renamed from + ext_dce_try_optimize_insn. + (ext_dce_process_uses): Handle shift pairs implementing extensions. + +2025-11-13 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR tree-optimization/122637 + * tree-scalar-evolution.cc (final_value_replacement_loop): Fix order + of gimplification and constant prop. + +2025-11-13 Jeff Law <jlaw@ventanamicro.com> + + PR rtl-optimization/122627 + * lra-constraints.cc (update_equiv): Remove patch from last week + related to pr122321. + (lra_constraints): Expand the equivalence array after eliminations + are complete. + +2025-11-13 Xi Ruoyao <xry111@xry111.site> + + * configure.ac (HAVE_AS_16B_ATOMIC): Define if the assembler + supports LSX and sc.q. + * configure: Regenerate. + * config.in: Regenerate. + * config/loongarch/loongarch-opts.h (HAVE_AS_16B_ATOMIC): + Defined to 0 if undefined yet. + * config/loongarch/linux.h (HAVE_IFUNC_FOR_LIBATOMIC_16B): + Define as HAVE_AS_16B_ATOMIC && OPTION_GLIBC. + * config/loongarch/loongarch-protos.h + (loongarch_16b_atomic_lock_free_p): New prototype. + * config/loongarch/loongarch.cc + (loongarch_16b_atomic_lock_free_p): Implement. + * config/loongarch/sync.md (atomic_storeti_lsx): Require + loongarch_16b_atomic_lock_free_p. + (atomic_storeti): Likewise. + (atomic_exchangeti_scq): Likewise. + (atomic_exchangeti): Likewise. + (atomic_compare_and_swapti): Likewise. + (atomic_fetch_<amop_ti_fetch>ti_scq): Likewise. + (atomic_fetch_<amop_ti_fetch>ti): Likewise. + (ALL_SC): Likewise for TImode. + (atomic_storeti_scq): Remove. + +2025-11-13 Richard Biener <rguenther@suse.de> + + * config/i386/i386-features.cc (pass_x86_cse::x86_cse): Delete + loads. + +2025-11-13 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> + + PR other/122638 + * doc/install.texi (Configuration, --enable-x86-64-mfentry): Fix + typo. + +2025-11-13 liuhongt <hongtao.liu@intel.com> + + * config/i386/i386.md (*ior<mode>_ccz_1): New define_insn. + +2025-11-13 Alice Carlotti <alice.carlotti@arm.com> + + * config/aarch64/driver-aarch64.cc + (host_detect_local_cpu): Extend feature string syntax. + +2025-11-13 Richard Biener <rguenther@suse.de> + + * tree-ssa-dce.cc (simple_dce_from_worklist): For calls + with side-effects remove their LHS. + +2025-11-13 Andre Vieira <andre.simoesdiasvieira@arm.com> + + * config/aarch64/aarch64-simd.md (*eor3q<mode>4): New insn to be used by + combine after reload to optimize any grouping of eor's that are using FP + registers for scalar modes. + +2025-11-13 Kuan-Lin Chen <rufus@andestech.com> + + * config/riscv/riscv-target-attr.cc (riscv_process_target_str): Clean + the final byte of str_to_check. + +2025-11-12 David Malcolm <dmalcolm@redhat.com> + + PR diagnostics/115970 + * diagnostics/sarif-sink.cc (maybe_open_sarif_sink_for_socket): + Add "%m" to error messages, so that we print the string form of + errno. + +2025-11-12 David Malcolm <dmalcolm@redhat.com> + + * diagnostics/sarif-sink.cc (class unique_fd): New. + (sarif_socket_sink::sarif_socket_sink): Convert "fd" arg and m_fd + from int to unique_fd. + (~sarif_socket_sink): Drop. + (sarif_socket_sink::dump_kind): Update for m_fd becoming a + unique_fd. + (sarif_socket_sink::m_fd): Convert from "int" to "unique_fd". + (maybe_open_sarif_sink_for_socket): Likewise for "sfd". + +2025-11-12 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add ampere1c. + * config/aarch64/aarch64-tune.md: Regenerate. + * doc/invoke.texi: Document the above. + +2025-11-12 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org> + + * config/i386/i386.opt.urls: Regenerate. + * config/s390/s390.opt.urls: Ditto. + * doc/invoke.texi: Add documentation for + -mstack-protector-guard= and -mstack-protector-guard-record. + +2025-11-12 Arsen Arsenović <arsen@aarsen.me> + + * doc/invoke.texi (Diagnostic Message Formatting Options): Add + index entries for SARIF and HTML output formats. + +2025-11-12 Richard Biener <rguenther@suse.de> + + PR tree-optimization/122653 + * tree-scalar-evolution.cc (interpret_rhs_expr): Handle + POINTER_DIFF_EXPR. + +2025-11-12 Christophe Lyon <christophe.lyon@linaro.org> + Richard Earnshaw <rearnsha@arm.com> + + PR target/122175 + * config/arm/iterators.md (asm_const_size): New mode attr. + * config/arm/mve.md (@mve_<mve_insn>q_n_<supf><mode>): Use it. + +2025-11-12 Andre Vieira <andre.simoesdiasvieira@arm.com> + + PR target/122539 + * config/arm/arm.cc (comp_not_to_clear_mask_str_un): Skip partial + register clearing logic for FP_REGS. + (compute_not_to_clear_mask): Likewise. + +2025-11-12 Andre Vieira <andre.simoesdiasvieira@arm.com> + + PR target/122539 + * config/arm/arm.cc (comp_not_to_clear_mask_str_un): Update + not_to_clear_reg_mask for union members. + +2025-11-12 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org> + + * config/s390/s390-opts.h (enum stack_protector_guard): Define + SP_TLS and SP_GLOBAL. + * config/s390/s390.h (TARGET_SP_GLOBAL_GUARD): Define predicate. + (TARGET_SP_TLS_GUARD): Define predicate. + * config/s390/s390.md (stack_protect_global_guard_addr<mode>): + New insn. + (stack_protect_set): Also deal with a global guard. + (stack_protect_test): Also deal with a global guard. + * config/s390/s390.opt (-mstack-protector-guard={global,tls}): + New option. + (-mstack-protector-guard-record) New option. + +2025-11-12 Richard Biener <rguenther@suse.de> + + PR tree-optimization/122647 + * tree-vect-stmts.cc (vectorizable_conversion): Fix guard on + bool to non-bool conversion. + * tree-vect-patterns.cc (vect_recog_bool_pattern): Also handle + FLOAT_EXPR from bool. + +2025-11-12 Kuan-Lin Chen <rufus@andestech.com> + + * config/riscv/andes-25-series.md: New file. + * config/riscv/riscv-cores.def (RISCV_TUNE): Add andes-25-series. + (RISCV_CORE): Add Andes 25-series cpu list. + * config/riscv/riscv-opts.h + (enum riscv_microarchitecture_type): Add andes_25_series_. + * config/riscv/riscv.cc: Add andes_25_tune_info. + * config/riscv/riscv.md: Add andes_25. + * doc/riscv-mcpu.texi: Regenerated for Andes cpu list. + * doc/riscv-mtune.texi: Regenerated for andes-25-series. + +2025-11-11 Andrew Stubbs <ams@baylibre.com> + + * config/gcn/mkoffload.cc (process_asm): Replace "configure_stack_size" + constructor with a new regular function, "mkoffload_setup". + (process_obj): Call mkoffload_setup from the "init" constructor. + +2025-11-11 David Malcolm <dmalcolm@redhat.com> + + PR diagnostics/115970 + * diagnostics/sarif-sink.cc: Include <sys/un.h> and <sys/socket.h>. + (sarif_builder::end_group): Update comment. + (sarif_sink::on_end_group): Drop "final". + (class sarif_socket_sink): New subclass. + (maybe_open_sarif_sink_for_socket): New function. + * diagnostics/sarif-sink.h: (maybe_open_sarif_sink_for_socket): + New decl. + * doc/invoke.texi (EXPERIMENTAL_SARIF_SOCKET): Document new + environment variable. + * toplev.cc: Define INCLUDE_VECTOR. Add include of + "diagnostics/sarif-sink.h". + (toplev::main): Call + diagnostics::maybe_open_sarif_sink_for_socket. + +2025-11-11 Richard Biener <rguenther@suse.de> + + PR tree-optimization/122587 + * tree-vectorizer.cc (pass_vectorize::execute): Enable + ranger around analysis and code generation. + +2025-11-11 Richard Biener <rguenther@suse.de> + + * tree-ssa-loop-niter.cc (simplify_using_initial_conditions): + Use the active ranger to simplify boolean expressions. + +2025-11-11 Jeff Law <jlaw@ventanamicro.com> + + * config/riscv/crypto.md (packf splitters): Variant with + operands reversed. Add variants with the ashift/sign extend + exchanged as well. + +2025-11-11 Jeff Law <jlaw@ventanamicro.com> + + * config/riscv/riscv.cc (riscv_extend_to_xmode_reg): Simplify + by using convert_modes + force_reg. + +2025-11-11 Richard Biener <rguenther@suse.de> + + * gimple-range.cc (gimple_ranger::range_on_edge): Pass + the edge as 'edge' to get_tree_range. + (dom_ranger::range_on_edge): Likewise. + +2025-11-11 Andrew MacLeod <amacleod@redhat.com> + + * value-query.cc (range_query::invoke_range_of_expr): New + edge argument. If set invoke range_on_edge. + (range_query::get_tree_range): Likewise and adjust. + * value-query.h (range_query::invoke_range_of_expr): New + edge argument. + (range_query::get_tree_range): Likewise. + +2025-11-11 Dhruv Chawla <dhruvc@nvidia.com> + + * match.pd: New patterns. + +2025-11-11 Lulu Cheng <chenglulu@loongson.cn> + + * doc/extend.texi: Add description for LoongArch function + attributes. + +2025-11-11 Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/loongarch.cc (loongarch_can_inline_p): + Do not inline when callee is versioned but caller is not. + +2025-11-11 Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/loongarch.cc + (loongarch_option_same_function_versions): Compare the target + attributes in two functions to determine which function’s + features get higher priority. + (TARGET_OPTION_SAME_FUNCTION_VERSIONS): Define. + +2025-11-11 Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/loongarch-protos.h + (loongarch_parse_fmv_features): Modify the type of parameter. + (loongarch_compare_version_priority): Function declaration. + * config/loongarch/loongarch-target-attr.cc + (enum features_prio): Define LA_PRIO_MAX to indicate the + highest priority of supported attributes. + (loongarch_parse_fmv_features): Added handling of setting + priority in attribute string. + (loongarch_compare_version_priority): Likewise. + * config/loongarch/loongarch.cc + (loongarch_process_target_version_attr): Likewise. + (get_feature_mask_for_version): Likewise. + (loongarch_compare_version_priority): Delete. + +2025-11-11 Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/loongarch.cc + (loongarch_compare_version_priority): Returns true if DECL1 + and DECL2 are versions of the same function. + (TARGET_COMPARE_VERSION_PRIORITY): Define. + +2025-11-11 Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/genopts/gen-evolution.awk: + * config/loongarch/loongarch-evol-attr.def: Regenerate. + * config/loongarch/loongarch-protos.h + (loongarch_parse_fmv_features): Function declaration. + (get_feature_mask_for_version): Likewise. + * config/loongarch/loongarch-target-attr.cc + (enum features_prio): Defining the priority of features. + (struct loongarch_attribute_info): Add members about + features. + (LARCH_ATTR_MASK): Likewise. + (LARCH_ATTR_ENUM): Likewise. + (LARCH_ATTR_BOOL): Likewise. + (loongarch_parse_fmv_features): Parse a function + multiversioning feature string STR. + * config/loongarch/loongarch.cc + (get_suffixed_assembler_name): Return an identifier for the + base assembler name of a versioned function. + (get_feature_mask_for_version): Get the mask and priority of + features. + (add_condition_to_bb): Insert judgment statements for different + features functions. + (dispatch_function_versions): Generates the dispatch function for + multi-versioned functions. + (make_resolver_func): Make the resolver function decl to dispatch + the versions of a multi-versioned function. + (loongarch_generate_version_dispatcher_body): Generate the + dispatcher logic to invoke the right function version at run-time + for a given set of function versions. + (TARGET_GENERATE_VERSION_DISPATCHER_BODY): Define. + * common/config/loongarch/cpu-features.h: New file. + +2025-11-11 Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/loongarch.cc (INCLUDE_STRING): Include. + (loongarch_mangle_decl_assembler_name): New function. + (TARGET_MANGLE_DECL_ASSEMBLER_NAME): Define. + +2025-11-11 Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/loongarch.cc + (loongarch_get_function_versions_dispatcher): New function. + (TARGET_GET_FUNCTION_VERSIONS_DISPATCHER): Define. + +2025-11-11 Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/loongarch.cc + (loongarch_process_target_version_attr): New function. + (loongarch_option_valid_version_attribute_p): New function. + (TARGET_OPTION_VALID_VERSION_ATTRIBUTE_P): Define. + * config/loongarch/loongarch.h + (TARGET_HAS_FMV_TARGET_ATTRIBUTE): Define it to 0. + +2025-11-11 Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/genopts/gen-evolution.awk: Output the + info needed for handling evolution features when parsing + the target pragma and attribute. + * config/loongarch/genopts/genstr.sh: Add support for + generating *.def files. + * config/loongarch/loongarch-target-attr.cc + (struct loongarch_attribute_info): Add structure member + record option mask. + (LARCH_ATTR_MASK): New macro. + (LARCH_ATTR_ENUM): Likewise. + (LARCH_ATTR_BOOL): Likewise. + (loongarch_handle_option): Support for new options. + (loongarch_process_one_target_attr): Added support for + the la64v1.1 extended instruction set. + * config/loongarch/t-loongarch: Generate loongarch-evol-attr.def. + * doc/extend.texi: Add new attribute description information. + * config/loongarch/loongarch-evol-attr.def: Generate. + +2025-11-11 Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/loongarch-target-attr.cc + (loongarch_process_one_target_attr): Fix ICE. + +2025-11-11 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR tree-optimization/122629 + * tree-if-conv.cc (factor_out_operators): Reject + BIT_FIELD_REF and BIT_INSERT_EXPR if operand other + than 0 is different. + +2025-11-11 Jakub Jelinek <jakub@redhat.com> + + PR lto/122620 + * gimplify-me.cc (gimple_regimplify_operands): Don't try to regimplify + TREE_CLOBBER on rhs of gimple_clobber_p if it has gimple_reg_type. + +2025-11-11 Hu, Lin1 <lin1.hu@intel.com> + + PR target/122446 + * config/i386/amxavx512intrin.h (_tile_cvtrowps2bf16hi_internal): + Input register name by inline asm %c[...], and remove %% before tmm + from intel side. + (_tile_cvtrowps2bf16li_internal): Ditto. + * config/i386/amxbf16intrin.h (_tile_dpbf16ps_internal): Ditto + * config/i386/amxcomplexintrin.h (_tile_cmmimfp16ps_internal): Ditto + (_tile_cmmrlfp16ps_internal): Ditto + (_tile_cmmimfp16ps): Ditto + (_tile_cmmrlfp16ps): Ditto + * config/i386/amxfp16intrin.h (_tile_dpfp16ps_internal): Ditto + (_tile_dpfp16ps): Ditto + * config/i386/amxfp8intrin.h (_tile_dpbf8ps_internal): Ditto + (_tile_dpbhf8ps_internal): Ditto + (_tile_dphbf8ps_internal): Ditto + (_tile_dphf8ps_internal): Ditto + (_tile_dpbf8ps): Ditto + (_tile_dpbhf8ps): Ditto + (_tile_dphbf8ps): Ditto + (_tile_dphf8ps): Ditto + * config/i386/amxint8intrin.h (_tile_int8_dp_internal): Ditto + * config/i386/amxmovrsintrin.h (_tile_loaddrs_internal): Ditto + (_tile_loaddrst1_internal): Ditto + (_tile_loaddrs): Ditto + (_tile_loaddrst1): Ditto + * config/i386/amxtf32intrin.h (_tile_mmultf32ps_internal): Ditto + * config/i386/amxtileintrin.h (_tile_loadd): Ditto + (_tile_loadd_internal): Ditto + (_tile_stream_loadd): Ditto + (_tile_stream_loadd_internal): Ditto + (_tile_stored): Ditto + (_tile_stored_internal): Ditto + (_tile_zero): Ditto + (_tile_zero_internal): Ditto + +2025-11-10 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/122243 + * common.opt.urls: Regenerated. + * config/dragonfly.opt.urls: Regenerated. + * config/freebsd.opt.urls: Regenerated. + * config/gcn/gcn.opt.urls: Regenerated. + * config/gnu-user.opt.urls: Regenerated. + +2025-11-10 Sam James <sam@gentoo.org> + + * acinclude.m4: Quote "$gcc_cv_nm" and friends. + * configure.ac: Ditto. + * configure: Regenerate. + +2025-11-10 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR middle-end/122605 + * builtins.cc (expand_ifn_atomic_bit_test_and): Split out the call to + build_call_nary into two different statements. + (expand_ifn_atomic_op_fetch_cmp_0): Likewise. + +2025-11-10 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/122243 + * common.opt: Clean up comments/documentation for -fident. + * doc/invoke.texi: Move -Qy/-Qn documentation from System V options + and combine with -fident/-fno-ident entry. + +2025-11-10 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/122243 + * common.opt: Add comments/documentation for -N, -Q, -S, -T, + -Tbss, -Tdata, -Ttext, -Z, -n, -Q, -s, -t, -z. + * doc/invoke.texi: Add documentation for -Tbss, -Tdata, -Ttext, + -N, -n, -t, -Z. + +2025-11-10 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/122243 + PR rtl-optimization/120064 + * doc/invoke.texi: Document -fconcepts-diagnostics-depth, + -Wdeprecated-copy-dtor, -Wformat-diag, -Wcannot-profile, + -fvar-tracking-uninit, -gno-pubnames, -finline-atomics, + -fext-dce, -fipa-icf-functions, -fipa-icf-variables, + -fprofile, -fdump-internal-locations, and -Wopenacc-dims. + Minor copy-editing and rearrangement of items in the option + summary lists. + +2025-11-10 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/122243 + * doc/cppdiropts.texi: Document --include-directory, + --include-directory-after, --include-barrier, --include-prefix, + --include-with-prefix, --include-with-prefix-after, + --include-with-prefix-before, --no-standard-includes. + --embed-directory. + * doc/cppopts.texi: Document --define-macro, --undefine-macro, + --include, --imacros, --dependencies, --user-dependencies, + --print-missing-file-dependencies, --write-dependencies, + --write-user-dependencies, --comments, --comments-in-macros, + --no-line-commands, --traditional, --traditional-cpp, + --trigraphs, --trace-includes, --dump. + * doc/invoke.texi: Add missing long options to Option Summary. + Document --language, --compile, --assemble, --preprocess, + --output, --dumpbase, --dumpbase-ext, --dumpdir, + --verbose, --pass-exit-codes, --pipe, --specs, --ansi, + --no-warnings, --pedantic, --pedantic-errors, --all-warnings, + --extra-warnings, --debug, --optimize, --profile, -coverage, + --no-integrated-cpp, --for-assembler, --no-standard-libraries, + --entries, --pie, --static-pie, --static, --shared, --symbolic, + --for-linker, --force-link, --library-directory, --prefix, + --no-canonical-prefixes, --dump, --save-temps, --print-file-name, + --print-multi-directory, --print-multi-lib, + --print-multi-os-directory, --print-multiarch, + --print-prog-name, --print-libgcc-file-name, --print-search-dirs, + --print-sysroot, --print-sysroot-headers-suffix. + +2025-11-10 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/122243 + * doc/cppopts.texi (-A): Restrict option documentation to the CPP + manual. Also document the --assert form. + * doc/invoke.texi (Option Summary): Don't list the -A option. + +2025-11-10 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/122243 + * doc/invoke.texi (Option Summary): Add missing entries, + also correct alphabetization and formatting of the C++ options. + (C++ Language Options): Fix some formatting issues. + +2025-11-10 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/122243 + * common.opt (fhelp, fhelp=, ftarget-help, fversion): Mark as + "Undocumented". + (fbounds-check): Update comments. + (flag-graphite, fsel-sched-reschedule-pipelined): Mark as + "Undocumented". + (fstack-limit): Add comment. + +2025-11-10 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/122243 + * common.opt (fhelp): Add RejectNegative. + (fhelp=): Likewise. + (ftarget-help): Likewise. + (fversion): Likewise. + (Wno-frame-larger-than): Likewise. + (Wno-larger-than): Likewise. + (Wno-stack-usage): Likewise. + (fdiagnostics-minimum-margin-width=): Likewise. + (flto-incremental=): Likewise. + (foffload=): Likewise. + (foffload-options=): Likewise. + (foffload-abi-host-opts=): Likewise. + (fpatchable-function-entry=): Likewise. + (gno-pubnames): Likewise. + (gpubnames): Likewise. + (ggnu-pubnames): Likewise. + +2025-11-10 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/122243 + * common.opt (ftree-lrs): Mark as "Ignore". + +2025-11-10 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/122243 + * doc/cppopts.texi (fcanonical-system-headers): Add @opindex. + * doc/invoke.texi (fdump-ada-spec-slim): Add @opindex. + (fcontract-semantic): Likewise. + (fdiagnostics-plain-output): Likewise. + (Wc11-c2x-compat): Likewise. + (Wvla-parameter): Likewise. + (fanalyzer-verbose-edges): Likewise. + (fanalyzer-verbose-state-changes): Likewise. + (fanalyzer-verbosity): Likewise. + (flimit-function-alignment): Likewise. + +2025-11-10 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/122243 + * doc/invoke.texi (fdump-analyzer-exploded-nodes): Correct + spelling of option in @opindex. + (fdump-analyzer-exploded-nodes-2): Likewise. + (fdump-analyzer-exploded-nodes-3): Likewise. + (fdump-analyzer-feasibility): Likewise. + (fdump-analyzer-infinite-loop): Likewise. + (fstack-reuse): Likewise. + +2025-11-10 Dimitar Dimitrov <dimitar@dinux.eu> + + * config/pru/pru.h (REG_CLASS_CONTENTS): Use unsigned integer + constants. + +2025-11-10 Dimitar Dimitrov <dimitar@dinux.eu> + + PR target/122415 + * config/pru/pru-protos.h (pru_fixup_jump_address_operand): + Declare. + * config/pru/pru.cc (pru_fixup_jump_address_operand): New + function. + (pru_addr_space_legitimize_address): New function. + (TARGET_ADDR_SPACE_LEGITIMIZE_ADDRESS): Declare. + * config/pru/pru.md (call): Fixup the address operand. + (call_value): Ditto. + (sibcall): Ditto. + (sibcall_value): Ditto. + +2025-11-10 Tejas Belagod <tejas.belagod@arm.com> + + * config/aarch64/aarch64-sve-builtins.cc (register_builtin_types): Make + SVE vector boolean type equivalent to GNU vectors. + * config/aarch64/aarch64-sve.md (extend<vpred><mode>2, + zero_extend<vpred><mode>2, trunc<mode><vpred>2, vec_cmp<mode><mode>): + New patterns to support additional operations on predicate modes. + * config/aarch64/aarch64.cc (aarch64_valid_vector_boolean_op): New. + (aarch64_invalid_unary_op): Consider vector bool types. + (aarch64_invalid_binary_op): Likewise. + (aarch64_convert_to_type): Define target hook and handle standard to + non-standard bool conversion. + +2025-11-10 Richard Earnshaw <rearnsha@arm.com> + + PR target/118460 + * config/arm/arm.md (movhfcc): Use expandable_comparison_operator. + (movsfcc, movdfcc): Likewise. + +2025-11-10 Robin Dapp <rdapp@ventanamicro.com> + + PR middle-end/121985 + * tree-vect-loop-manip.cc (vect_gen_vector_loop_niters): Only + set niter_vector's range if step == 1. + +2025-11-10 Robin Dapp <rdapp@ventanamicro.com> + + * optabs-query.cc (qimode_for_vec_perm): Check if QImode's + precision divides the inner mode's precision. + +2025-11-10 Robin Dapp <rdapp@ventanamicro.com> + + * tree-vect-data-refs.cc (vect_gather_scatter_fn_p): Bail if + offset_vectype is NULL. + +2025-11-10 Robin Dapp <rdapp@ventanamicro.com> + + * tree-vect-slp.cc (vect_load_perm_consecutive_p): New function. + (vect_lower_load_permutations): Use. + (vect_optimize_slp_pass::remove_redundant_permutations): Use. + * tree-vect-stmts.cc (has_consecutive_load_permutation): New + function that uses vect_load_perm_consecutive_p. + (get_load_store_type): Use. + (vectorizable_load): Reduce group size. + * tree-vectorizer.h (struct vect_load_store_data): Add + subchain_p. + (vect_load_perm_consecutive_p): Declare. + +2025-11-08 Avinash Jayakar <avinashd@linux.ibm.com> + + PR tree-optimization/122126 + * gimple-isel.cc (gimple_expand_vec_set_extract_expr): Add bound check. + +2025-11-08 Lulu Cheng <chenglulu@loongson.cn> + + PR target/122097 + * config/loongarch/loongarch.cc + (loongarch_const_vector_same_bytes_p): Add processing for + floating-point vector data. + +2025-11-08 Avinash Jayakar <avinashd@linux.ibm.com> + + PR tree-optimization/122065 + * tree-vect-generic.cc (target_supports_mult_synth_alg): Add helper to + check mult synth. + (expand_vector_mult): Optimize mult when const is uniform but not + power of 2. + +2025-11-08 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR tree-optimization/122599 + * tree-scalar-evolution.cc (final_value_replacement_loop): Move + the removal of the phi until after the gimplification of the final + value expression. + +2025-11-07 David Malcolm <dmalcolm@redhat.com> + + * gdbhooks.py (class AnaSupernodePrinter): New. + (class AnaExplodedNodePrinter): New. + (build_pretty_printer): Register the above. + +2025-11-07 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * tree.cc (build_call_nary): Remove decl. + Add template definition that uses std::initializer_list<tree> + and call build_call. + (build_call): New declaration. + * tree.h (build_call_nary): Remove. + (build_call): New function. + +2025-11-07 Robin Dapp <rdapp@ventanamicro.com> + + * config/riscv/autovec.md: Use const_1_operand for scale and + extend predicates. + * config/riscv/riscv-v.cc (expand_gather_scatter): Remove scale + and extension handling. + +2025-11-07 Robin Dapp <rdapp@ventanamicro.com> + + * tree-vect-stmts.cc (vect_use_strided_gather_scatters_p): + Do not convert offset type. + +2025-11-07 Robin Dapp <rdapp@ventanamicro.com> + + * tree-vect-data-refs.cc (struct gather_scatter_config): + Add scale. + (vect_gather_scatter_get_configs): Try various scales. + (vect_gather_scatter_fn_p): Add scale handling. + (vect_check_gather_scatter): Add scale parameter. + * tree-vect-stmts.cc (check_load_store_for_partial_vectors): + Ditto. + (vect_truncate_gather_scatter_offset): Ditto. + (vect_use_grouped_gather): Ditto. + (get_load_store_type): Ditto. + (vectorizable_store): Scale offset if necessary. + (vectorizable_load): Ditto. + * tree-vectorizer.h (struct vect_load_store_data): Add + supported_scale. + (vect_gather_scatter_fn_p): Add argument. + +2025-11-07 Robin Dapp <rdapp@ventanamicro.com> + + * tree-vect-data-refs.cc (struct gather_scatter_config): New + struct to hold gather/scatter configurations. + (vect_gather_scatter_which_ifn): New function to determine which + IFN to use. + (vect_gather_scatter_get_configs): New function to enumerate all + target-supported configs. + (vect_gather_scatter_fn_p): Rework to use + vect_gather_scatter_get_configs and try sign-swapped offset. + (vect_check_gather_scatter): Use new supported offset vectype + argument. + * tree-vect-stmts.cc (check_load_store_for_partial_vectors): + Ditto. + (vect_truncate_gather_scatter_offset): Ditto. + (vect_use_grouped_gather): Ditto. + (get_load_store_type): Ditto. + (vectorizable_store): Convert to sign-swapped offset type if + needed. + (vectorizable_load): Ditto. + * tree-vectorizer.h (struct vect_load_store_data): Add + supported_offset_vectype. + (vect_gather_scatter_fn_p): Add argument. + +2025-11-07 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR tree-optimization/122588 + * tree-ssa-forwprop.cc (optimize_unreachable): Don't touch + if the condition was already true or false. + +2025-11-07 David Faust <david.faust@oracle.com> + + PR target/122140 + * config/bpf/bpf.cc (bpf_expand_cpymem): Fix off-by-one offset + in backwards loop. Improve src and dest addrs used for the + branch condition. + (emit_move_loop): Improve emitted set insns and remove the + explict temporary register. + +2025-11-07 Richard Biener <rguenther@suse.de> + + PR tree-optimization/122577 + * tree-vect-stmts.cc (vectorizable_conversion): Allow conversions + from non-mode-precision types. + +2025-11-07 Pan Li <pan2.li@intel.com> + + * match.pd: Leverage usmul_widen_mult by bit_ior based + unsigned SAT_MUL pattern. + +2025-11-07 Pan Li <pan2.li@intel.com> + + * config/riscv/autovec-opt.md (*vwsll_sign_extend_<mode>): Add + pattern to combine vsext.vf2 and vslli.vi to vwsll.vi. + +2025-11-07 Richard Biener <rguenther@suse.de> + + PR tree-optimization/122589 + PR middle-end/122594 + * gimple-iterator.cc (gsi_replace_with_seq): Instead of + removing the last stmt from the sequence with gsi_remove, + split it using gsi_split_seq_before. + (gsi_split_seq_before): Fix bogus documentation. + +2025-11-07 Alfie Richards <alfie.richards@arm.com> + + PR target/118328 + * config/aarch64/aarch64.cc (handle_aarch64_vector_pcs_attribute): + Add handling for ARM_PCS_PRESERVE_NONE. + (aarch64_pcs_exclusions): New definition. + (aarch64_gnu_attributes): Add entry for preserve_none and add + aarch64_pcs_exclusions to aarch64_vector_pcs entry. + (aarch64_preserve_none_abi): New function. + (aarch64_fntype_abi): Add handling for preserve_none. + (aarch64_reg_save_mode): Add handling for ARM_PCS_PRESERVE_NONE. + (aarch64_hard_regno_call_part_clobbered): Add handling for + ARM_PCS_PRESERVE_NONE. + (num_pcs_arg_regs): New helper function. + (get_pcs_arg_reg): New helper function. + (aarch64_function_ok_for_sibcall): Add handling for ARM_PCS_PRESERVE_NONE. + (aarch64_layout_arg): Add preserve_none argument lauout.. + (function_arg_preserve_none_regno_p): New helper function. + (aarch64_function_arg): Update to handle preserve_none. + (function_arg_preserve_none_regno_p): Update logic for preserve_none. + (aarch64_expand_builtin_va_start): Add preserve_none layout. + (aarch64_setup_incoming_varargs): Add preserve_none layout. + (aarch64_is_variant_pcs): Update for case of ARM_PCS_PRESERVE_NONE. + (aarch64_comp_type_attributes): Add preserve_none. + * config/aarch64/aarch64.h (NUM_PRESERVE_NONE_ARG_REGS): New macro. + (PRESERVE_NONE_REGISTERS): New macro. + (enum arm_pcs): Add ARM_PCS_PRESERVE_NONE. + * doc/extend.texi (preserve_none): Add docs for new attribute. + +2025-11-07 Pan Li <pan2.li@intel.com> + + * config/riscv/autovec-opt.md (*widen_mul_plus_vx_<mode>): Add + new pattern to combine the vwmaccu.vx. + * config/riscv/vector.md (*pred_widen_mul_plus_u_vx<mode>_undef): + Add undef define_insn for vmwaccu.vx emiting. + (@pred_widen_mul_plus_u_vx<mode>): Ditto. + +2025-11-07 Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/loongarch.cc + (loongarch_sign_extend_if_subreg_prom_p): Determine if the + current operand is SUBREG and if the source of SUBREG is + the sign-extended value. + (loongarch_expand_conditional_move): Optimize. + +2025-11-07 Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/loongarch.cc + (loongarch_canonicalize_int_order_test): Support GT GTU LT + and LTU. + (loongarch_extend_comparands): Expand the scope of op1 from + 0 to all immediate values. + * config/loongarch/loongarch.md + (*sge<u>_<X:mode><GPR:mode>): New template. + +2025-11-07 Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/loongarch.cc + (loongarch_legitimize_move): Optimize. + +2025-11-06 Sandra Loosemore <sloosemore@baylibre.com> + + * doc/invoke.texi (AArch64 Options): Clean up description of + -mbranch-protection= argument. + (ARM Options): Likewise. + +2025-11-06 Alejandro Colomar <alx@kernel.org> + + * doc/extend.texi: Move _Countof under 'Syntax Extensions'. + +2025-11-06 Georg-Johann Lay <avr@gjlay.de> + + PR target/122516 + * config/avr/elf.h (SUPPORTS_SHF_GNU_RETAIN): Define if + HAVE_GAS_SHF_GNU_RETAIN. + +2025-11-06 Jeff Law <jlaw@ventanamicro.com> + + * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p): Ignore + assignments of (const_int 0) to a register. They will get propagated + away. + +2025-11-06 Georg-Johann Lay <avr@gjlay.de> + + * config/avr/avr.cc (avr_output_addr_vec): Output + a valid opcode prior to the first gs() label provided: + - The code is compiled for an arch that has AVR-SD mcus, and + - the function has a "section" attribute, and + - the function has a gs() label addresses switch/case table. + +2025-11-06 Your Name <jlaw@ventanamicro.com> + + PR rtl-optimization/121136 + * config/riscv/riscv.md: Add define_insn to test the + upper bits of a register against zero using sltiu when + the bits are extracted via zero_extract or logial right shift. + Add 3->2 define_splits for gtu/leu cases testing upper bits + against zero. + +2025-11-06 Richard Biener <rguenther@suse.de> + + * tree-core.h (tree_ssa_name::active_iterated_stmt): Mark + GTY((skip(""))). + +2025-11-06 Richard Biener <rguenther@suse.de> + + * ssa-iterators.h (imm_use_iterator::name): Add. + (delink_imm_use): When in a FOR_EACH_IMM_USE_STMT iteration + enforce we only remove uses from the current stmt. + (end_imm_use_stmt_traverse): Reset current stmt. + (first_imm_use_stmt): Assert no FOR_EACH_IMM_USE_STMT on + var is in progress. Set the current stmt. + (next_imm_use_stmt): Set the current stmt. + (auto_end_imm_use_fast_traverse): New, lower iteration + depth upon destruction. + (first_readonly_imm_use): Bump the iteration depth. + * tree-core.h (tree_ssa_name::active_iterated_stmt, + tree_ssa_name::fast_iteration_depth): New members when + ENABLE_GIMPLE_CHECKING. + * tree-ssanames.cc (make_ssa_name_fn): Initialize + immediate use verifier bookkeeping members. + +2025-11-06 Richard Biener <rguenther@suse.de> + + PR tree-optimization/122502 + * ssa-iterators.h (imm_use_iterator::iter_node): Remove. + (imm_use_iterator::next_stmt_use): New. + (next_readonly_imm_use): Adjust checking code. + (end_imm_use_stmt_traverse): Simplify. + (link_use_stmts_after): Likewise. Return the last use + with the same stmt. + (first_imm_use_stmt): Simplify. Set next_stmt_use. + (next_imm_use_stmt): Likewise. + (end_imm_use_on_stmt_p): Adjust. + +2025-11-06 Richard Biener <rguenther@suse.de> + + * doc/tree-ssa.texi: Update immediate use iterator + documentation. + * ssa-iterators.h: Likewise. + +2025-11-06 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/113632 + * range-op-mixed.h (operator_bitwise_xor): Relocate and adjust. + (operator_bitwise_xor::m_and, m_or, m_not): New. + * range-op.cc (operator_bitwise_xor::fold_range): New. + +2025-11-06 Xi Ruoyao <xry111@xry111.site> + + * config.gcc: Support --with-cmodel={medium,normal} and make + medium the default for LoongArch, define TARGET_DEFAULT_CMODEL + as the selected value. + * config/loongarch/loongarch-opts.cc: Use TARGET_DEFAULT_CMODEL + instead of hard coding CMODEL_NORMAL. + * doc/install.texi: Document that --with-cmodel= is supported + for LoongArch. + * doc/invoke.texi: Update the document about default code model + on LoongArch. + +2025-11-05 Nathaniel Shead <nathanieloshead@gmail.com> + + PR c++/121574 + * doc/invoke.texi: Document '-Wexpose-global-module-tu-local'. + +2025-11-05 Artemiy Volkov <artemiy.volkov@arm.com> + + * tree-ssa-forwprop.cc (simplify_vector_constructor): Support + vector constructor elements. + * tree-vect-generic.cc (ssa_uniform_vector_p): Make non-static and + move ... + * tree.cc (ssa_uniform_vector_p): ... here. + * tree.h (ssa_uniform_vector_p): Declare it. + +2025-11-05 Richard Biener <rguenther@suse.de> + + * tree-ssa-forwprop.cc (forward_propagate_addr_expr): + Use gather_imm_use_stmts instead of FOR_EACH_IMM_USE_STMT. + +2025-11-05 Richard Biener <rguenther@suse.de> + + * gimple.h (gimple::pad): Rename to ... + (gimple::ilf): ... this. + * ssa-iterators.h (gather_imm_use_stmts): Declare. + * tree-ssa-operands.cc (gather_imm_use_stmts): New function. + +2025-11-05 Richard Biener <rguenther@suse.de> + + * gimple-ssa-isolate-paths.cc (check_loadstore): Set + the volatile flag on the stmt manually. + (find_implicit_erroneous_behavior): Move code transform + outside of FOR_EACH_IMM_USE_STMT iteration. + +2025-11-05 Richard Biener <rguenther@suse.de> + + * tree-ssa-loop-niter.cc (dump_affine_iv): Use file, not + dump_file when printing. + (debug): New overload for affine_iv. + +2025-11-05 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/loongarch.md (cntmap): Change to uppercase. + (popcount<GPR:mode>2): Modify to a post reload split. + +2025-11-04 Uros Bizjak <ubizjak@gmail.com> + + PR target/122390 + * config/i386/i386.md (*add<mode>3_carry_2): New insn pattern. + (*add<mode>3_carry_0_cc): Ditto. + (*add<mode>3_carry_0r_cc): Ditto. + (*sub<mode>3_carry_2): Ditto. + (*sub<mode>3_carry_0_cc): Ditto. + (*sub<mode>3_carry_0r_cc): Ditt. + +2025-11-04 Kees Cook <kees@kernel.org> + + * config/arc/builtins.def: Add ATTRS parameter to DEF_BUILTIN + macro calls. Mark mathematical builtins (FFS, FLS, NORM, NORMW, + SWAP) with attr_const, leave others as NULL_TREE. + * config/arc/arc.cc: Add support for builtin function attributes. + Create attr_const using tree_cons. Update DEF_BUILTIN macro to + pass ATTRS parameter to add_builtin_function. + +2025-11-04 Pan Li <pan2.li@intel.com> + + * match.pd: Add usmul_widen_mult helper and referenced by + min based unsigned SAT_MUL pattern. + +2025-11-04 Siddhesh Poyarekar <siddhesh@gotplt.org> + + PR lto/122515 + * lto-wrapper.cc (debug_objcopy): Set type of INOFF to int64_t. + (run_gcc): Set type of FILE_OFFSET to int64_t. + +2025-11-04 Kishan Parmar <kishan@linux.ibm.com> + + PR rtl-optimization/93738 + * simplify-rtx.cc (simplify_binary_operation_1): Canonicalize + SUBREG(LSHIFTRT) into LSHIFTRT(SUBREG) when valid. + +2025-11-04 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/122544 + * diagnostics/paths.cc (event::meaning::maybe_get_verb_str): + Handle the new verbs. + * diagnostics/paths.h (event::meaning::verb): Add new values + for special control flow operations. + (event::meaning::meaning): Add ctor taking just a verb. + +2025-11-03 Uros Bizjak <ubizjak@gmail.com> + + PR target/122534 + * config/i386/i386.md (@test<mode>_ccno_1): + Use <general_szext_operand> as operand 1 predicate. + (testqi_ccz_1): Use general_operand as operand 1 predicate. + (*testdi_1): Use x86_64_szext_general_operand as operand 1 predicate. + (*testqi_1_maybe_si): Use general_operand as operand 1 predicate. + Add (n,*a) alternative to allow UV pairing for pentium processor. + (*test<mode>_1): Use <general_operand> as operand 1 predicate. + +2025-11-03 Sam James <sam@gentoo.org> + + * configure: Regenerate. + +2025-11-03 Jeff Law <jlaw@ventanamicro.com> + + PR rtl-optimization/122536 + * simplify-rtx.cc (simplify_context::simplify_binary_operation_1): Fix + guard against variable bit extracts in recent change. + +2025-11-03 Thomas Schwinge <tschwinge@baylibre.com> + + PR ipa/122512 + * symtab.cc: Fix 'static_assert'. + +2025-11-03 Loeka Rogge <loeka@synopsys.com> + + * config/arc/simdext.md(movv2hi_insn): Change order for movv2hi + for big-endian. + +2025-11-03 Tobias Burnus <tburnus@baylibre.com> + + PR libgomp/122281 + PR middle-end/105001 + * gimple.cc (gimple_copy): Add missing unshare_expr for + GIMPLE_OMP_ATOMIC_LOAD and GIMPLE_OMP_ATOMIC_STORE. + +2025-11-03 Alfie Richards <alfie.richards@arm.com> + + PR c/122202 + * doc/extend.texi (target function attribute): Update to describe FMV + behaviour. + (target_version function attribute): New section. + (target_clones attribute): Update to descrbe new behaviour with + target_version. + (Function Multiversioning): Update to discuss both target_version and + target based FMV. + +2025-11-03 Kito Cheng <kito.cheng@sifive.com> + + * config/riscv/riscv.cc (riscv_flatten_aggregate_field): Skip + empty unions and zero-length arrays when flattening aggregate + fields for ABI classification. + (riscv_pass_aggregate_in_fpr_pair_p): Refactor to use separate + field parsing and emit ABI change warning for affected types. + (riscv_pass_aggregate_in_fpr_and_gpr_p): Likewise. + +2025-11-03 Alfie Richards <alfie.richards@arm.com> + + * config/aarch64/aarch64-option-extensions.def (dit): New fmv feature. + (dpb): New fmv feature. + (dpb2): New fmv feature. + (memtag): Change to also define an FMV feature. + (ssbs): Change to also define an FMV feature. + (bti): New fmv feature. + * config/aarch64/aarch64.cc (FEAT_SSBS): Add macro. + (FEAT_MEMTAG): Ditto. + +2025-11-03 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.md (int_iterator ANY_ROUND): + Specify "flag_unsafe_math_optimizations" in the condition of the + UNSPEC_ROUND element. + (int_attr c_round): Remove. + (l<m_round>sfsi2, *l<m_round>sfsi2_2x, *l<m_round>sfsi2_scaled): + Remove " && <c_round>" from the conditions. + +2025-11-03 Guo Jie <guojie@loongson.cn> + + * config/loongarch/loongarch.cc (loongarch_modes_tieable_p): + Make MODE_FLOAT and MODE_INT tieable. + * config/loongarch/loongarch.md: Adjust constraints. + +2025-11-03 Guo Jie <guojie@loongson.cn> + + * config/loongarch/loongarch.md + (and_load_zero_extend<mode>): New combiner. + * config/loongarch/predicates.md + (mask_operand): New predicate. + +2025-11-03 Guo Jie <guojie@loongson.cn> + + * config/loongarch/lasx.md (lasx_xvpermi_q_<LASX:mode>): + Add new splitter for optimization. + +2025-11-03 Guo Jie <guojie@loongson.cn> + + * config/loongarch/loongarch-protos.h + (loongarch_use_bstrins_bstrpick_for_and): New proto. + * config/loongarch/loongarch.cc + (loongarch_use_bstrins_bstrpick_for_and): Decide whether + to optimize. + (loongarch_rtx_costs): Adjust the cost of AND operation. + * config/loongarch/loongarch.md + (bstrins_bstrpick_for_and_imm<mode>): New insn_and_split. + +2025-11-03 Guo Jie <guojie@loongson.cn> + + * config/loongarch/loongarch.cc + (loongarch_can_change_mode_class): Support for conversion + between scalar INT and scalar FP. + +2025-11-03 Guo Jie <guojie@loongson.cn> + + * config/loongarch/loongarch.cc (loongarch_rtx_costs): + Correct the cost of mulh.{w[u]|d[u]}. + +2025-11-03 Tamar Christina <tamar.christina@arm.com> + + PR tree-optimization/122475 + * tree-vect-loop.cc (vectorizable_reduction): Check for neutral_op. + +2025-11-03 H.J. Lu <hjl.tools@gmail.com> + + PR target/90262 + * config/i386/i386-expand.cc (ix86_expand_unroll_movmem): New. + (ix86_expand_n_move_movmem): Likewise. + (ix86_expand_load_movmem): Likewise. + (ix86_expand_store_movmem): Likewise. + (ix86_expand_n_overlapping_move_movmem): Likewise. + (ix86_expand_less_move_movmem): Likewise. + (ix86_expand_movmem): Likewise. + * config/i386/i386-protos.h (ix86_expand_movmem): Likewise. + * config/i386/i386.md (movmem<mode>): Likewise. + +2025-11-03 Shreya Munnangi <smunnangi1@ventanamicro.com> + + PR target/52345 + * simplify-rtx.cc (simplify_relational_operation_1): Optimize boolean + IOR equality tests. + +2025-11-03 chenxiaolong <chenxiaolong@loongson.cn> + + * config/loongarch/lasx.md (vec_cast<mode>): New template + implemention. + (vec_insert_lo_<mode>): Dito. + (vec_insert_hi_<mode>): Dito. + * config/loongarch/lasxintrin.h (defined): Test for adding + the builtin function. + (__lasx_cast_128_s): Dito. + (__lasx_cast_128_d): Dito. + (__lasx_cast_128): Dito. + (__lasx_concat_128_s): Dito. + (__lasx_concat_128_d): Dito. + (__lasx_concat_128): Dito. + (__lasx_extract_128_lo_s): Dito. + (__lasx_extract_128_hi_s): Dito. + (__lasx_extract_128_lo_d): Dito. + (__lasx_extract_128_hi_d): Dito. + (__lasx_extract_128_lo): Dito. + (__lasx_extract_128_hi): Dito. + (__lasx_insert_128_lo_s): Dito. + (__lasx_insert_128_hi_s): Dito. + (__lasx_insert_128_lo_d): Dito. + (__lasx_insert_128_hi_d): Dito. + (__lasx_insert_128_lo): Dito. + (__lasx_insert_128_hi): Dito. + * config/loongarch/loongarch-builtins.cc + (CODE_FOR_lasx_extract_128_lo_s): Add builtins and register + icode. + (CODE_FOR_lasx_extract_128_hi_s): Dito. + (CODE_FOR_lasx_extract_128_lo_d): Dito. + (CODE_FOR_lasx_extract_128_hi_d): Dito. + (CODE_FOR_lasx_extract_128_lo): Dito. + (CODE_FOR_lasx_extract_128_hi): Dito. + (CODE_FOR_lasx_insert_128_lo_s): Dito. + (CODE_FOR_lasx_insert_128_hi_s): Dito. + (CODE_FOR_lasx_insert_128_lo_d): Dito. + (CODE_FOR_lasx_insert_128_hi_d): Dito. + (CODE_FOR_lasx_insert_128_lo): Dito. + (CODE_FOR_lasx_insert_128_hi): Dito. + (CODE_FOR_lasx_concat_128_s): Dito. + (CODE_FOR_lasx_concat_128_d): Dito. + (CODE_FOR_lasx_concat_128): Dito. + (CODE_FOR_lasx_cast_128_s): Dito. + (CODE_FOR_lasx_cast_128_d): Dito. + (CODE_FOR_lasx_cast_128): Dito. + (loongarch_expand_builtin_direct): For the newly added + insertion or extraction, construct the parallel parameter + corresponding to the operand. + * config/loongarch/loongarch-c.cc + (loongarch_update_cpp_builtins): Define + __loongarch_asx_sx_conv. + * config/loongarch/loongarch-ftypes.def: Declare the type + of the builtin function. + * doc/extend.texi: Add document description. + +2025-11-03 Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/loongarch.cc (loongarch_move_integer): + No new virtual register is allocated during immediate load. + +2025-11-03 Lulu Cheng <chenglulu@loongson.cn> + + PR target/122477 + * config/loongarch/loongarch.cc + (loongarch_split_reduction): Added handling of scalar mode. + +2025-11-02 Jeff Law <jlaw@ventanamicro.com> + + * config/riscv/bitmanip.md (rotrsi3): Use the sign extended form + for 32 bit rotates on TARGET_64BIT, even for constant counts. + * config/riscv/thead.md (th_srrisi3_extended): New pattern. + (th_srri<mode>3): Adjust formatting. + +2025-11-02 Uros Bizjak <ubizjak@gmail.com> + + PR target/122518 + * config/i386/i386.cc (ix86_canonicalize_comparison): Convert + (compare (minus (a b)) a) to (compare (a b)) to + match *sub<mode>_3 pattern. + +2025-11-02 Georg-Johann Lay <avr@gjlay.de> + + PR target/122527 + * config/avr/avr.cc (avr_load_libgcc_p): Return false if + the address-space is not ADDR_SPACE_FLASH. + (avr_out_lpm_no_lpmx [addr=REG]): Handle sizes of 3 and 4 bytes. + +2025-11-02 Georg-Johann Lay <avr@gjlay.de> + + PR tree-optimization/118012 + PR tree-optimization/122505 + * config/avr/avr.md (mulpsi3): Also allow the insn condition + in the case where avropt_pr118012 && !AVR_TINY. + (*mulpsi3): Handle split for the !AVR_HAVE_MUL case. + (*mulpsi3-nomul.libgcc_split, *mulpsi3-nomul.libgcc): New insns. + +2025-11-02 Richard Biener <rguenther@suse.de> + + * doc/tree-ssa.texi: Remove outdated info on FOR_EACH_IMM_USE_STMT + iteration, clarify SSA operand parts. + * ssa-iterators.h: Update toplevel comment. + +2025-11-02 Sam James <sam@gentoo.org> + + * .simplify-rtx.cc.swo: Removed. + 2025-11-01 Shreya Munnangi <smunnangi1@ventanamicro.com> PR target/67731 @@ -19363,7 +23521,7 @@ original address with more adaptive operations 2025-05-06 Julian Waters <tanksherman27@gmail.com> - Eric Botcazou <botcazou@adacore.com> + Eric Botcazou <ebotcazou@adacore.com> Uroš Bizjak <ubizjak@gmail.com> Liu Hao <lh_mouse@126.com> |