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Diffstat (limited to 'gcc/ChangeLog')
| -rw-r--r-- | gcc/ChangeLog | 1104 |
1 files changed, 1104 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 86389dd..ee83e32 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,1107 @@ +2025-03-27 Uros Bizjak <ubizjak@gmail.com> + + * config/i386/i386.cc (ix86_redzone_clobber): Use integer, not rtx + as the third argument of plus_constant. + +2025-03-27 Richard Biener <rguenther@suse.de> + + PR target/119010 + * config/i386/zn4zn5.md (znver4_insn_both, znver5_insn_both): + New reservation for ALU ops with load and store. + +2025-03-27 Richard Biener <rguenther@suse.de> + + PR target/119010 + * config/i386/zn4zn5.md (znver4_sse_add, znver4_sse_add_load, + znver5_sse_add_load, znver4_sse_add1, znver4_sse_add1_load, + znver5_sse_add1_load, znver4_sse_mul, znver4_sse_mul_load, + znver5_sse_mul_load, znver4_sse_cvt, znver4_sse_cvt_load, + znver5_sse_cvt_load, znver4_sse_shuf, znver5_sse_shuf, + znver4_sse_shuf_load, znver5_sse_shuf_load, + znver4_sse_cmp_avx128, znver5_sse_cmp_avx128, + znver4_sse_cmp_avx128_load, znver5_sse_cmp_avx128_load): + Also handle DFmode. + (znver4_sse_muladd_load, znver5_sse_muladd_load): Use + ssemuladd type. + +2025-03-27 Tobias Burnus <tburnus@baylibre.com> + + * gimplify.cc (modify_call_for_omp_dispatch): Remove sorry. + +2025-03-27 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/neon.md (<fmaxmin><mode>3): Move pattern from here... + * config/arm/vec-common.md (<fmaxmin><mode>3): ... to here. Convert + to define_expand and disable the pattern when denormal values might + get truncated to zero. Iterate on VF to add V4HF and V8HF variants. + +2025-03-27 Hu, Lin1 <lin1.hu@intel.com> + + PR target/119425 + * config/i386/sse.md: + (vec_set<mode>_0): Set the alternative with constraint "jm"'s + attribute "addr" to "gpr16". + (<mask_codefor>avx512dq_shuf_<shuffletype>64x2_1<mask_name>): + Ditto. + (avx512vl_shuf_<shuffletype>32x4_1<mask_name>): Ditto. + (avx2_pblendd<mode>): Ditto. + (aesenc): Ditto. + (aesenclast): Ditto. + (aesdec): Ditto. + (aesdeclast): Ditto. + (vaesdec_<mode>): Ditto. + (vaesdeclast_<mode>): Ditto. + (vaesenc_<mode>):: Ditto. + (vaesenclast_<mode>):: Ditto. + (aes<aesklvariant>u8): Ditto. + (*aes<aeswideklvariant>u8): Ditto. + +2025-03-27 Lulu Cheng <chenglulu@loongson.cn> + + PR target/119408 + * config/loongarch/loongarch.cc + (loongarch_c_mode_for_suffix): New. + (TARGET_C_MODE_FOR_SUFFIX): Define. + +2025-03-26 Jørgen Kvalsvik <j@lambda.is> + + * builtins.cc (expand_builtin_fork_or_exec): Call + coverage_instrumentation_p. + * ipa-inline.cc (can_early_inline_edge_p): Likewise. + * passes.cc (finish_optimization_passes): Likewise. + * profile.cc (coverage_instrumentation_p): New function. + * profile.h (coverage_instrumentation_p): New declaration. + * tree-profile.cc (tree_profiling): Call + coverage_instrumentation_p. + (pass_ipa_tree_profile::gate): Likewise. + * value-prof.h (coverage_instrumentation_p): New declaration. + +2025-03-26 Jørgen Kvalsvik <j@lambda.is> + + * Makefile.in (OBJS): Add prime-paths.o, path-coverage.o. + (GTFILES): Add prime-paths.cc, path-coverage.cc + (GCOV_OBJS): Add graphds.o, prime-paths.o, bitmap.o + * builtins.cc (expand_builtin_fork_or_exec): Check + path_coverage_flag. + * collect2.cc (main): Add -fno-path-coverage to OBSTACK. + * common.opt: Add new options -fpath-coverage, + -fpath-coverage-limit, -Wcoverage-too-many-paths + * doc/gcov.texi: Add --prime-paths, --prime-paths-lines, + --prime-paths-source documentation. + * doc/invoke.texi: Add -fpath-coverage, -fpath-coverage-limit, + -Wcoverage-too-many-paths documentation. + * gcc.cc: Link gcov on -fpath-coverage. + * gcov-counter.def (GCOV_COUNTER_PATHS): New. + * gcov-io.h (GCOV_TAG_PATHS): New. + (GCOV_TAG_PATHS_LENGTH): New. + (GCOV_TAG_PATHS_NUM): New. + * gcov.cc (class path_info): New. + (struct coverage_info): Add paths, paths_covered. + (find_prime_paths): New. + (add_path_counts): New. + (find_arc): New. + (print_usage): Add -e, --prime-paths, --prime-paths-lines, + --prime-paths-source. + (process_args): Likewise. + (json_set_prime_path_coverage): New. + (output_json_intermediate_file): Call + json_set_prime_path_coverage. + (process_all_functions): Call find_prime_paths. + (generate_results): Call add_path_counts. + (read_graph_file): Read path counters. + (read_count_file): Likewise. + (function_summary): Print path counts. + (file_summary): Likewise. + (print_source_line): New. + (print_prime_path_lines): New. + (print_inlined_separator): New. + (print_prime_path_source): New. + (output_path_coverage): New. + (output_lines): Print path coverage. + * ipa-inline.cc (can_early_inline_edge_p): Check + path_coverage_flag. + * passes.cc (finish_optimization_passes): Likewise. + * profile.cc (branch_prob): Likewise. + * selftest-run-tests.cc (selftest::run_tests): Run path coverage + tests. + * selftest.h (path_coverage_cc_tests): New declaration. + * tree-profile.cc (tree_profiling): Check path_coverage_flag. + (pass_ipa_tree_profile::gate): Likewise. + * path-coverage.cc: New file. + * prime-paths.cc: New file. + +2025-03-26 Jørgen Kvalsvik <j@lambda.is> + + * gcov.cc (generate_results): Count branches, conditions. + (function_summary): Output branch, calls, condition count. + +2025-03-26 Thomas Schwinge <thomas@codesourcery.com> + + PR driver/101544 + * gcc.cc (driver_handle_option): Forward host '-lstdc++' to + offloading compilation. + * config/gcn/mkoffload.cc (main): Adjust. + * config/nvptx/mkoffload.cc (main): Likewise. + +2025-03-26 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/119417 + * tree-ssa-math-opts.cc (convert_mult_to_widen): Before changing + typeN because actual_precision/from_unsignedN differs cast rhsN + to typeN if it has a different type. + (convert_plusminus_to_widen): Before changing + typeN because actual_precision/from_unsignedN differs cast mult_rhsN + to typeN if it has a different type. + +2025-03-26 Jakub Jelinek <jakub@redhat.com> + Andi Kleen <ak@gcc.gnu.org> + + PR gcov-profile/118442 + * profile.cc (branch_prob): Ignore EDGE_FAKE edges from musttail calls + to EXIT. + +2025-03-26 Jakub Jelinek <jakub@redhat.com> + + PR target/119450 + * config/i386/i386.md (narrow test peephole2): Test for + offsettable_memref_p in condition. + +2025-03-26 Richard Biener <rguenther@suse.de> + + PR target/119010 + * config/i386/zn4zn5.md (znver4_sse_mov_fp, znver4_sse_mov_fp_load, + znver5_sse_mov_fp_load, znver4_sse_mov_fp_store, + znver5_sse_mov_fp_store): Also match V1SF and DF. + +2025-03-26 Richard Biener <rguenther@suse.de> + + PR target/119010 + * config/i386/zn4zn5.md (znver4_imov_double_store, + znver5_imov_double_store, znver4_imov_store, znver5_imov_store): + New reservations for integer stores. + +2025-03-26 Richard Biener <rguenther@suse.de> + + PR middle-end/118795 + * match.pd (vec_perm <vec_perm <a, b>> -> vec_perm <a, b>): + Use the appropriate check to see whether the original + outer permute was supported. + +2025-03-26 Hu, Lin1 <lin1.hu@intel.com> + + * config/i386/avx10_2-512convertintrin.h (_mm512_mask_cvtx2ps_ph): Formatting fixes + (_mm512_mask_cvtx_round2ps_ph): Ditto + (_mm512_maskz_cvtx_round2ps_ph): Ditto + (_mm512_cvtbiassph_bf8): Rename to _mm512_cvts_biasph_bf8. + (_mm512_mask_cvtbiassph_bf8): Rename to _mm512_mask_cvts_biasph_bf8. + (_mm512_maskz_cvtbiassph_bf8): Rename to _mm512_maskz_cvts_biasph_bf8. + (_mm512_cvtbiassph_hf8): Rename to _mm512_cvts_biasph_hf8. + (_mm512_mask_cvtbiassph_hf8): Rename to _mm512_mask_cvts_biasph_hf8. + (_mm512_maskz_cvtbiassph_hf8): Rename to _mm512_maskz_cvts_biasph_hf8. + (_mm512_cvts2ph_bf8): Rename to _mm512_cvts_2ph_bf8. + (_mm512_mask_cvts2ph_bf8): Rename to _mm512_mask_cvts_2ph_bf8. + (_mm512_maskz_cvts2ph_bf8): Rename to _mm512_maskz_cvts_2ph_bf8. + (_mm512_cvts2ph_hf8): Rename to _mm512_cvts_2ph_hf8. + (_mm512_mask_cvts2ph_hf8): Rename to _mm512_mask_cvts_2ph_hf8. + (_mm512_maskz_cvts2ph_hf8): Rename to _mm512_maskz_cvts_2ph_hf8. + (_mm512_cvtsph_bf8): Rename to _mm512_cvts_ph_bf8. + (_mm512_mask_cvtsph_bf8): Rename to _mm512_mask_cvts_ph_bf8. + (_mm512_maskz_cvtsph_bf8): Rename to _mm512_maskz_cvts_ph_bf8. + (_mm512_cvtsph_hf8): Rename to _mm512_cvts_ph_hf8. + (_mm512_mask_cvtsph_hf8): Rename to _mm512_mask_cvts_ph_hf8. + (_mm512_maskz_cvtsph_hf8): Rename to _mm512_maskz_cvts_ph_hf8. + * config/i386/avx10_2convertintrin.h + (_mm_cvtbiassph_bf8): Rename to _mm_cvts_biasph_bf8. + (_mm_mask_cvtbiassph_bf8): Rename to _mm_mask_cvts_biasph_bf8. + (_mm_maskz_cvtbiassph_bf8): Rename to _mm_maskz_cvts_biasph_bf8. + (_mm256_cvtbiassph_bf8): Rename to _mm256_cvts_biasph_bf8. + (_mm256_mask_cvtbiassph_bf8): Rename to _mm256_mask_cvts_biasph_bf8. + (_mm256_maskz_cvtbiassph_bf8): Rename to _mm256_maskz_cvts_biasph_bf8. + (_mm_cvtbiassph_hf8): Rename to _mm_cvts_biasph_hf8. + (_mm_mask_cvtbiassph_hf8): Rename to _mm_mask_cvts_biasph_hf8. + (_mm_maskz_cvtbiassph_hf8): Rename to _mm_maskz_cvts_biasph_hf8. + (_mm256_cvtbiassph_hf8): Rename to _mm256_cvts_biasph_hf8. + (_mm256_mask_cvtbiassph_hf8): Rename to _mm256_mask_cvts_biasph_hf8. + (_mm256_maskz_cvtbiassph_hf8): Rename to _mm256_maskz_cvts_biasph_hf8. + (_mm_cvts2ph_bf8): Rename to _mm_cvts_2ph_bf8. + (_mm_mask_cvts2ph_bf8): Rename to _mm_mask_cvts_2ph_bf8. + (_mm_maskz_cvts2ph_bf8): Rename to _mm_maskz_cvts_2ph_bf8. + (_mm256_cvts2ph_bf8): Rename to _mm256_cvts_2ph_bf8. + (_mm256_mask_cvts2ph_bf8): Rename to _mm256_mask_cvts_2ph_bf8. + (_mm256_maskz_cvts2ph_bf8): Rename to _mm256_maskz_cvts_2ph_bf8. + (_mm_cvts2ph_hf8): Rename to _mm_cvts_2ph_hf8. + (_mm_mask_cvts2ph_hf8): Rename to _mm_mask_cvts_2ph_hf8. + (_mm_maskz_cvts2ph_hf8): Rename to _mm_maskz_cvts_2ph_hf8. + (_mm256_cvts2ph_hf8): Rename to _mm256_cvts_2ph_hf8. + (_mm256_mask_cvts2ph_hf8): Rename to _mm256_mask_cvts_2ph_hf8. + (_mm256_maskz_cvts2ph_hf8): Rename to _mm256_maskz_cvts_2ph_hf8. + (_mm_cvtsph_bf8): Rename to _mm_cvts_ph_bf8. + (_mm_mask_cvtsph_bf8): Rename to _mm_mask_cvts_ph_bf8. + (_mm_maskz_cvtsph_bf8): Rename to _mm_maskz_cvts_ph_bf8. + (_mm256_cvtsph_bf8): Rename to _mm256_cvts_ph_bf8. + (_mm256_mask_cvtsph_bf8): Rename to _mm256_mask_cvts_ph_bf8. + (_mm256_maskz_cvtsph_bf8): Rename to _mm256_maskz_cvts_ph_bf8. + (_mm_cvtsph_hf8): Rename to _mm_cvts_ph_hf8. + (_mm_mask_cvtsph_hf8): Rename to _mm_mask_cvts_ph_hf8. + (_mm_maskz_cvtsph_hf8): Rename to _mm_maskz_cvts_ph_hf8. + (_mm256_cvtsph_hf8): Rename to _mm256_cvts_ph_hf8. + (_mm256_mask_cvtsph_hf8): Rename to _mm256_mask_cvts_ph_hf8. + (_mm256_maskz_cvtsph_hf8): Rename to _mm256_maskz_cvts_ph_hf8. + +2025-03-25 Iain Sandoe <iain@sandoe.co.uk> + + * gcov.cc (get_gcov_intermediate_filename): Use lbasename(). + +2025-03-25 Iain Sandoe <iain@sandoe.co.uk> + + PR other/119250 + * config.in: Regenerate. + * configure: Regenerate. + * configure.ac: Match the configure test in libiberty when checking + the basename decl. + +2025-03-25 Sandra Loosemore <sloosemore@baylibre.com> + Tobias Burnus <tburnus@baylibre.com> + + * gimplify.cc (modify_call_for_omp_dispatch): Adjust arguments. + Remove the "sorry" for the case where new interop objects must be + constructed, and add code to make it work instead. + (expand_variant_call_expr): Adjust arguments and call to + modify_call_for_omp_dispatch. + (gimplify_variant_call_expr): Simplify logic for calling + expand_variant_call_expr. + +2025-03-25 Jakub Jelinek <jakub@redhat.com> + + PR target/96226 + PR target/119428 + * config/i386/i386.md (splitter after *<rotate_insn><mode>3_mask, + splitter after *<rotate_insn><mode>3_mask_1): Revert 2020-12-05 + changes. + +2025-03-25 Vineet Gupta <vineetg@rivosinc.com> + + PR target/119224 + * config/riscv/autovec.md: Disable abd splitter. + +2025-03-25 Tobias Burnus <tburnus@baylibre.com> + + PR middle-end/119325 + * doc/install.texi (gcn): Change ROCm > 6.3.2 to >6.3.3 for generic + support; mention Newlib commit that fixes a SIMD math issue. + +2025-03-25 Tobias Burnus <tburnus@baylibre.com> + + PR middle-end/118627 + * omp-general.cc (omp_parse_access_method): Change to return void. + (omp_parse_access_methods): Return void; remove 'if' around a + function call. + (omp_parse_expr): Remove 'if' around a function call. + +2025-03-25 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/arm.md (<US>mull): Add alternatives that allow Rs + to be tied to either Rdlo or Rdhi. + +2025-03-25 Richard Earnshaw <rearnsha@arm.com> + + PR middle-end/117811 + * optabs.cc (expand_binop_directly): Remove LAST as an argument, + instead record the last insn on entry. Only delete insns if + we need to restart and restart by calling ourself, not expand_binop. + (expand_binop): Update callers to expand_binop_directly. If it + fails to expand the operation, delete back to LAST. + +2025-03-25 Jakub Jelinek <jakub@redhat.com> + + PR ipa/119376 + * tree-tailcall.cc (suitable_for_tail_opt_p): Add DIAG_MUSTTAIL + argument, propagate it down to maybe_error_musttail. + (suitable_for_tail_call_opt_p): Likewise. + (maybe_error_musttail): Add DIAG_MUSTTAIL argument. Don't emit error + for gimple_call_must_tail_p calls if it is false. + (find_tail_calls): Add DIAG_MUSTTAIL argument, propagate it down to + maybe_error_musttail, suitable_for_tail_opt_p, + suitable_for_tail_call_opt_p and find_tail_calls calls. + (tree_optimize_tail_calls_1): Add DIAG_MUSTTAIL argument, propagate + it down to find_tail_calls and if set, clear cfun->has_musttail flag + at the end. Rename OPT_MUSTCALL argument to OPT_MUSTTAIL. + (execute_tail_calls): Pass true to DIAG_MUSTTAIL + tree_optimize_tail_calls_1 argument. + (pass_tail_recursion::execute): Pass false to DIAG_MUSTTAIL + tree_optimize_tail_calls_1 argument. + (pass_musttail::gate): Don't test flag_optimize_sibling_calls. + (pass_musttail::execute): Pass true to DIAG_MUSTTAIL + tree_optimize_tail_calls_1 argument. + +2025-03-24 Andrew Pinski <quic_apinski@quicinc.com> + + PR tree-optimization/118616 + * tree-vect-generic.cc (expand_vector_conversion): Add + an assert that converts vect is non empty if + supportable_indirect_convert_operation returns true. + +2025-03-24 Thomas Schwinge <tschwinge@baylibre.com> + + PR target/101544 + * config/nvptx/nvptx.cc (nvptx_asm_output_def_from_decls) + [ACCEL_COMPILER]: Special-case certain host-setup symbol aliases. + * varasm.cc (do_assemble_alias) [ACCEL_COMPILER]: Adjust. + +2025-03-24 Thomas Schwinge <tschwinge@baylibre.com> + + * config/nvptx/nvptx.cc (default_ptx_version_option): Default at + least to '-mptx=6.3'. + * doc/invoke.texi (Nvidia PTX Options): Update '-mptx=[...]'. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + * common/config/i386/cpuinfo.h + (get_available_features): Change to FEATURE_AVX10_1. + * common/config/i386/i386-common.cc + (OPTION_MASK_ISA2_AVX10_1_512_SET): Renamed to ... + (OPTION_MASK_ISA2_AVX10_1_SET): ... this. + (OPTION_MASK_ISA2_AVX10_2_SET): Use renamed macro. + (OPTION_MASK_ISA2_AVX10_1_UNSET): Ditto. + (ix86_handle_option): Ditto. + (processor_alias_table): Use P_PROC_AVX10_1. + * common/config/i386/i386-cpuinfo.h + (enum feature_priority): Rename from AVX10_1_512 to AVX10_1. + (enum processor_features): Ditto. + * common/config/i386/i386-isas.h: Add avx10.1. + * config/i386/driver-i386.cc + (host_detect_local_cpu): Use renamed enum. + * config/i386/i386-c.cc + (ix86_target_macros_internal): Rename to avx10.1. + * config/i386/i386-isa.def (AVX10_1_512): Rename to ... + (AVX10_1): ... this. + * config/i386/i386-options.cc (isa2_opts): Rename to avx10.1. + (ix86_valid_target_attribute_inner_p): Add avx10.1. + (ix86_option_override_internal): Rename to AVX10_1. + Revise warnings to mention behavior change for option + combination in GCC 16. + * config/i386/i386.h (PTA_DIAMONDRAPIDS): Use AVX10_1. + * config/i386/i386.opt: Add avx10.1. + Add deprecate warnings for mevex512 and mavx10.1-256/512. + * config/i386/i386.opt.urls: Add avx10.1. + * doc/extend.texi: Ditto. + * doc/sourcebuild.texi: Ditto. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + * common/config/i386/cpuinfo.h + (get_available_features): Revise the logic AVX10 version. + * common/config/i386/i386-common.cc + (OPTION_MASK_ISA2_AVX10_2_256_SET): Removed. + (OPTION_MASK_ISA2_AVX10_2_512_SET): Ditto. + (OPTION_MASK_ISA2_AVX10_2_SET): New. + (OPTION_MASK_ISA2_AMX_AVX512_SET): Use AVX10.2 macro. + (OPTION_MASK_ISA2_AVX10_2_UNSET): Ditto. + (ix86_handle_option): Remove avx10.2-256 part. Adjust avx10.2. + * common/config/i386/i386-cpuinfo.h + (enum processor_features): Remove FEATURE_AVX10_2_256 and skip + the value for it. Change the name from FEATURE_AVX10_2_512 to + FEATURE_AVX10_2. + * common/config/i386/i386-isas.h: Remove avx10.2-256/512. + * config/i386/avx10_2-512bf16intrin.h: Use avx10.2 instead of + avx10.2-256/512. + * config/i386/avx10_2-512convertintrin.h: Ditto. + * config/i386/avx10_2-512mediaintrin.h: Ditto. + * config/i386/avx10_2-512minmaxintrin.h: Ditto. + * config/i386/avx10_2-512satcvtintrin.h: Ditto. + * config/i386/avx10_2bf16intrin.h: Ditto. + * config/i386/avx10_2convertintrin.h: Ditto. + * config/i386/avx10_2mediaintrin.h: Ditto. + * config/i386/avx10_2minmaxintrin.h: Ditto. + * config/i386/avx10_2satcvtintrin.h: Ditto. + * config/i386/movrsintrin.h: Ditto. + * config/i386/sm4intrin.h: Ditto. + * config/i386/cpuid.h (bit_AVX10_256): Removed. + (bit_AVX10_512): Ditto. + * config/i386/driver-i386.cc (host_detect_local_cpu): Adjust + Diamond Rapids and -march=native condition. + * config/i386/i386-builtin.def (BDESC): Use AVX10.2 macro + instead of AVX10.2-256/512. + * config/i386/i386-c.cc (ix86_target_macros_internal): Ditto. + * config/i386/i386-expand.cc + (ix86_expand_branch): Use TARGET_AVX10_2 instead of specifying + vector size. + (ix86_prepare_fp_compare_args): Ditto. + (ix86_expand_fp_compare): Ditto. + (ix86_ssecom_setcc): Ditto. + (ix86_expand_sse_comi): Ditto. + (ix86_expand_sse_comi_round): Ditto. + (ix86_check_builtin_isa_match): Ditto. + * config/i386/i386.cc (ix86_fp_compare_code_to_integer): Ditto. + (ix86_get_mask_mode): Ditto. + * config/i386/i386.h (SSE_FLOAT_MODE_SSEMATH_OR_HFBF_P): Ditto. + * config/i386/i386.md: Ditto. + * config/i386/mmx.md: Ditto. + * config/i386/sse.md: Ditto. + * config/i386/predicates.md: Ditto. + * config/i386/i386-isa.def (AVX10_2_256): Removed. + (AVX10_2_512): Removed. + (AVX10_2): New. + * config/i386/i386-options.cc + (isa2_opts): Remove avx10.2-256/512. + (ix86_valid_target_attribute_inner_p): Ditto. + (PTA_DIAMONDRAPIDS): Use PTA_AVX10_2. + * config/i386/i386.opt: Remove avx10.2-256/512. + * config/i386/i386.opt.urls: Ditto. + * doc/extend.texi: Ditto. + * doc/invoke.texi: Ditto. + * doc/sourcebuild.texi: Ditto. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2024-08-19 Hu, Lin1 <lin1.hu@intel.com> + + * config.gcc: Add avx10_2roundingintrin.h. + * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. + * config/i386/i386-builtin.def (BDESC): Add new builtins. + * config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle + V4DF_FTYPE_V4DF_V4DF_V4DF_UQI_INT, V8SF_FTYPE_V8SF_V8SF_V8SF_UQI_INT, + V16HF_FTYPE_V16HF_V16HF_V16HF_UHI_INT, UQI_FTYPE_V4DF_V4DF_INT_UQI_INT, + UHI_FTYPE_V16HF_V16HF_INT_UHI_INT, UQI_FTYPE_V8SF_V8SF_INT_UQI_INT. + * config/i386/immintrin.h: Include avx10_2roundingintrin.h. + * config/i386/sse.md: Change subst_attr name due to renaming. + * config/i386/subst.md: + (<round_mode512bit_condition>): Add condition check for avx10.2 + rounding control 256bit intrins and renamed to ... + (<round_mode_condition>): ...this. + (round_saeonly_mode512bit_condition): Add condition check for + avx10.2 rounding control 256 bit intris and renamed to ... + (round_saeonly_mode_condition): ...this. + * config/i386/avx10_2roundingintrin.h: New file. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2024-08-19 Hu, Lin1 <lin1.hu@intel.com> + + * config/i386/avx10_2roundingintrin.h: Add new intrins. + * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. + * config/i386/i386-builtin.def (BDESC): Add new builtins. + * config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle + V8SF_FTYPE_V8SI_V8SF_UQI_INT, V4SF_FTYPE_V4DF_V4SF_UQI_INT, + V8HF_FTYPE_V8SI_V8HF_UQI_INT, V8HF_FTYPE_V4DF_V8HF_UQI_INT. + * config/i386/sse.md: + (avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode><mask_name><round_name>): + Add condition check. + (avx512fp16_vcvtpd2ph_v4df_mask_round): New expand. + (*avx512fp16_vcvt<castmode>2ph_<mode>_mask): Change name to + avx512fp16_vcvt<castmode>2ph_<mode>_mask<round_name>_1 + and extend pattern to generate 256bit insns. + (avx_cvtpd2ps256<mask_name>): Change name to + avx_cvtpd2ps256<mask_name><round_name> and extend pattern to + generate 256bit insns. + * config/i386/subst.md (round_applied): New condition. + (round_suff): New iterator. + (round_mode_condition): Add V32HI check for 512bit. + (round_saeonly_mode_condition): Ditto. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2024-08-19 Hu, Lin1 <lin1.hu@intel.com> + + * config/i386/avx10_2roundingintrin.h: Add new intrins. + * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. + * config/i386/i386-builtin.def (BDESC): Add new builtins. + * config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle + V4DI_FTYPE_V4DF_V4DI_UQI_INT, V4SI_FTYPE_V4DF_V4SI_UQI_INT. + * config/i386/sse.md: + (avx_cvtpd2dq256<mask_name>): Change name to + avx_cvtpd2dq256<mask_name><round_name> and extend pattern to + generate 256bit insns. + (fixuns_notrunc<mode><si2dfmodelower>2<mask_name><round_name>): + Add round_mode_condition. + * config/i386/subst.md (round_pd2udqsuff): New iterator. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2024-08-19 Hu, Lin1 <lin1.hu@intel.com> + + * config/i386/avx10_2roundingintrin.h: New intrins. + * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. + * config/i386/i386-builtin.def (BDESC): Add new builtins. + * config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle + V8SF_FTYPE_V8HF_V8SF_UQI_INT, V8SI_FTYPE_V8HF_V8SI_UQI_INT, + V4DF_FTYPE_V8HF_V4DF_UQI_INT, V4DI_FTYPE_V8HF_V4DI_UQI_INT. + * config/i386/sse.md: + (avx512fp16_float_extend_ph<mode>2<mask_name><round_saeonly_name>): + Add condition check. + (avx512fp16_vcvtph2<sseintconvertsignprefix><sseintconvert>_<mode> + <mask_name><round_name>): + Ditto. + (avx512fp16_float_extend_ph<mode>2<mask_name>): Extend round saeonly. + (vcvtph2ps256<mask_name>): Ditto. + * config/i386/subst.md + (round_saeonly_applied): New condition. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2024-08-19 Hu, Lin1 <lin1.hu@intel.com> + + * config/i386/avx10_2roundingintrin.h: New intrins. + * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. + * config/i386/i386-builtin.def (BDESC): Add new builtins. + * config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle + V16HI_FTYPE_V16HF_V16HI_UHI_INT, V4DF_FTYPE_V4SF_V4DF_UQI_INT + V8HF_FTYPE_V8SF_V8HF_UQI_INT. + * config/i386/sse.md + (avx512fp16_vcvt<castmode>2ph_<mode><mask_name><round_name>): + Add round condition check. + * config/i386/subst.md (round_mode_condition): Add V16HI check for + 256bit. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2024-08-19 Hu, Lin1 <lin1.hu@intel.com> + + * config/i386/avx10_2roundingintrin.h: New intrins. + * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. + * config/i386/i386-builtin.def (BDESC): Add new builtins. + * config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle + V8SI_FTYPE_V8SF_V8SI_UQI_INT, V4DI_FTYPE_V4SF_V4DI_UQI_INT. + * config/i386/sse.md + (<sse2_avx_avx512f>_fix_notrunc<sf2simodelower><mode><mask_name>): + Extend to round. + (<mask_codefor><avx512>_fixuns_notrunc<sf2simodelower><mode><mask_name><round_name>): + Add round condition check. + * config/i386/subst.md (round_constraint4): New. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2024-08-19 Hu, Lin1 <lin1.hu@intel.com> + + * config/i386/avx10_2roundingintrin.h: New intrins. + * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. + * config/i386/i386-builtin.def (BDESC): Add new builtins. + * config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle + V4DF_FTYPE_V4DI_V4DF_UQI_INT, V4SF_FTYPE_V4DI_V4SF_UQI_INT, + V8HF_FTYPE_V4DI_V8HF_UQI_INT. + * config/i386/sse.md: + (avx512fp16_vcvt<floatsuffix>qq2ph_v4di_mask_round): New expand. + (*avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode>_mask): + Extend round control and add "_1" suffix. + (float<floatunssuffix><sseintvecmodelower><mode>2<mask_name><round_name>): + Add condition check. + (float<floatunssuffix><sselongvecmodelower><mode>2<mask_name><round_name>): + Ditto. + (float<floatunssuffix><mode><ssePSmode2lower>2<mask_name><round_name>): + Limit suffix output. + (unspec_fix_truncv4dfv4si2<mask_name>): Extend round control. + (unspec_fixuns_truncv4dfv4si2<mask_name>): Ditto. + * config/i386/subst.md (round_qq2pssuff): New iterator. + (round_saeonly_suff): Ditto. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2024-08-19 Hu, Lin1 <lin1.hu@intel.com> + + * config/i386/avx10_2roundingintrin.h: New intrins. + * config/i386/i386-builtin.def (BDESC): Add new builtins. + * config/i386/sse.md (avx512fp16_fix<fixunssuffix>_trunc<mode>2<mask_name>): + Extend round control for 256bit. + (unspec_avx512fp16_fix<vcvtt_uns_suffix>_trunc<mode>2<mask_name>): + Ditto. + (avx512fp16_fix<fixunssuffix>_trunc<mode>2<mask_name><round_saeonly_name>): + Add condition check. + * config/i386/subst.md + (round_saeonly_mode_condition): Add V16HI check for 256bit. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2024-08-19 Hu, Lin1 <lin1.hu@intel.com> + + * config/i386/avx10_2roundingintrin.h: New intrins. + * config/i386/i386-builtin.def (BDESC): Add new builtins. + * config/i386/sse.md + (unspec_fix_truncv8sfv8si2<mask_name>): Extend rounding control. + (<mask_codefor>fixuns_trunc<mode><sseintvecmodelower>2<mask_name>): + Ditto. + (<mask_codefor>floatuns<sseintvecmodelower><mode>2<mask_name><round_name>): + Add condition check. + (fix<fixunssuffix>_trunc<mode><sselongvecmodelower>2<mask_name><round_saeonly_name>): + Remove round_saeonly_name. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2024-08-19 Hu, Lin1 <lin1.hu@intel.com> + + * config/i386/avx10_2roundingintrin.h: New intrins. + * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. + * config/i386/i386-builtin.def (BDESC): Add new builtins. + * config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle + V16HF_FTYPE_V16HI_V16HF_UHI_INT. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2024-08-19 Hu, Lin1 <lin1.hu@intel.com> + + * config/i386/avx10_2roundingintrin.h: New intrins. + * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. + * config/i386/i386-builtin.def (BDESC): Add new builtins. + * config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle + V16HF_FTYPE_V16HF_V16HF_INT, V16HF_FTYPE_V16HF_V16HF_V16HF_INT, + V16HF_FTYPE_V16HF_V16HF_V16HF_UQI_INT, + V4DF_FTYPE_V4DF_V4DF_V4DI_INT_UQI_INT, + V8SF_FTYPE_V8SF_V8SF_V8SI_INT_UQI_INT. + * config/i386/sse.md: + (<avx512>_fixupimm<mode><sd_maskz_name><round_saeonly_name>): + Add condition check. + (<avx512>_fixupimm<mode>_mask<round_saeonly_name>): Ditto. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2024-08-19 Hu, Lin1 <lin1.hu@intel.com> + + * config/i386/avx10_2roundingintrin.h: New intrins. + * config/i386/i386-builtin.def (BDESC): Add new builtins. + * config/i386/sse.md: + (<avx512>_fmadd_<mode>_mask3<round_name>): Add condition check. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2024-08-19 Hu, Lin1 <lin1.hu@intel.com> + + * config/i386/avx10_2roundingintrin.h: New intrins. + * config/i386/i386-builtin.def (BDESC): Add new builtins. + * config/i386/sse.md: + (<avx512>_fmaddsub_<mode>_mask<round_name>): Add condition check. + (<avx512>_fmaddsub_<mode>_mask3<round_name>): Ditto. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2024-08-19 Hu, Lin1 <lin1.hu@intel.com> + + * config/i386/avx10_2roundingintrin.h: New intrins. + * config/i386/i386-builtin.def (BDESC): Add new builtins. + * config/i386/sse.md: + (<avx512>_fmsub_<mode>_mask<round_name>): Add condition check. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2024-08-19 Hu, Lin1 <lin1.hu@intel.com> + + * config/i386/avx10_2roundingintrin.h: New intrins. + * config/i386/i386-builtin.def (BDESC): Add new builtins. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2024-08-19 Hu, Lin1 <lin1.hu@intel.com> + + * config/i386/avx10_2roundingintrin.h: New intrins. + * config/i386/i386-builtin.def (BDESC): Add new builtins. + * config/i386/sse.md: + (<avx512>_fnmsub_<mode>_mask3<round_name>): Add condition check. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2024-08-19 Hu, Lin1 <lin1.hu@intel.com> + + * config/i386/avx10_2roundingintrin.h: New intrins. + * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. + * config/i386/i386-builtin.def (BDESC): Add new builtins. + * config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle + V8SF_FTYPE_V8SF_V8SF_UQI_INT, V4DF_FTYPE_V4DF_V4DF_UQI_INT, + V16HF_FTYPE_V16HF_V16HF_UHI_INT, V16HF_FTYPE_V16HF_INT_V16HF_UHI_INT, + V4DF_FTYPE_V4DF_INT_V4DF_UQI_INT, V8SF_FTYPE_V8SF_INT_V8SF_UQI_INT. + * config/i386/sse.md: + (<avx512>_getexp<mode><mask_name><round_saeonly_name>): + Add condition check. + (<avx512>_getmant<mode><mask_name><round_saeonly_name>): + Ditto. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2024-08-19 Hu, Lin1 <lin1.hu@intel.com> + + * config/i386/avx10_2roundingintrin.h: New intrins. + * config/i386/i386-builtin.def (BDESC): Add new builtins. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2024-08-19 Hu, Lin1 <lin1.hu@intel.com> + + * config/i386/avx10_2roundingintrin.h: New intrins. + * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. + * config/i386/i386-builtin.def (BDESC): Add new builtins. + * config/i386/i386-expand.cc (ix86_expand_round_builtin): + Handle V8SF_FTYPE_V8SF_V8SF_INT_V8SF_UQI_INT, + V4DF_FTYPE_V4DF_V4DF_INT_V4DF_UQI_INT. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2024-08-19 Hu, Lin1 <lin1.hu@intel.com> + + * config/i386/avx10_2roundingintrin.h: New intrins. + * config/i386/i386-builtin.def (BDESC): Add new builtins. + * config/i386/sse.md: + (<mask_codefor>reducep<mode><mask_name><round_saeonly_name>): + Add condition check. + (<avx512>_rndscale<mode><mask_name><round_saeonly_name>): Ditto. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2024-08-19 Hu, Lin1 <lin1.hu@intel.com> + + * config/i386/avx10_2roundingintrin.h: New intrins. + * config/i386/i386-builtin.def: Add new builtins. + * config/i386/sse.md: + (<avx512>_scalef<mode><mask_name><round_name>): Add condition check. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2024-08-19 Hu, Lin1 <lin1.hu@intel.com> + + * config/i386/avx10_2roundingintrin.h: New intrins. + * config/i386/i386-builtin.def (BDESC): Add new builtins. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + * config/i386/avx10_2satcvtintrin.h: Remove rounding intrins. + Use non-round intrins. + * config/i386/i386-builtin.def (BDESC): Ditto. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + * config/i386/avx10_2convertintrin.h: Remove rounding intrins. + Use non-round builtins. + * config/i386/avx10_2minmaxintrin.h: Ditto. + * config/i386/i386-builtin.def (BDESC): Ditto. + * config/i386/i386-builtin-types.def: Remove unused type. + * config/i386/i386-expand.cc + (ix86_expand_args_builtin): Ditto. + (ix86_expand_round_builtin): Ditto. + +2025-03-23 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/42270 + * doc/extend.texi (Nonlocal Gotos): Group with other built-ins + sections. + (Constructing Calls): Likewise. + (Pragmas): Move earlier in the section, before the built-ins docs. + (Thread-Local): Likewise. + (OpenMP): Likewise. + (OpenACC): Likewise. + +2025-03-23 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/42270 + * doc/extend.texi (Syntax Extensions): New section. + (Statement Exprs): Make it a subsection of the above. + (Local Labels): Likewise. + (Labels as Values): Likewise. + (Nested Functions): Likewise. + (Typeof): Likewise. + (Offsetof): Likewise. + (Alignment): Likewise. + (Incomplete Enums): Likewise. + (Variadic Macros): Likewise. + (Conditionals): Likewise. + (Case Ranges): Likewise. + (Mixed Labels and Declarations): Likewise. + (C++ Comments): Likewise. + (Escaped Newlines): Likewise. + (Hex Floats): Likewise. + (Binary constants): Likewise. + (Dollar Signs): Likewise. + (Character Escapes): Likewise. + (Alternate Keywords): Likewise. + (Function Names): Likewise. + (Semantic Extensions): New section. + (Function Prototypes): Make it a subsection of the above. + (Pointer Arith): Likewise. + (Variadic Pointer Args): Likewise. + (Pointers to Arrays): Likewise. + (Const and Volatile Functions): Likewise. + +2025-03-23 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/42270 + * doc/extend.texi (Aggregate Types): New section. + (Variable Length): Make it a subsection of the above. + (Zero Length): Likewise. + (Empty Structures): Likewise. + (Flexible Array Members in Unions): Likewise. + (Flexible Array Members alone in Structures): Likewise. + (Unnamed Fields): Likewise. + (Cast to Union): Likewise. + (Subscripting): Likewise. + (Initializers): Likewise. + (Compound Literals): Likewise. + (Designated Inits): Likewise. + +2025-03-23 Sandra Loosemore <sloosemore@baylibre.com> + + PR other/42270 + * doc/extend.texi (Additional Numeric Types): New section. + (__int128): Make it a subsection of the above. + (Long Long): Likewise. + (Complex): Likewise. + (Floating Types): Likewise. + (Half-Precision): Likewise. + (Decimal Float): Likewise. + (Fixed-Point): Likewise. + +2025-03-23 Georg-Johann Lay <avr@gjlay.de> + + * config/avr/avr-mcus.def: Add AVR32SD20, AVR32SD28, AVR32SD32, + AVR64SD28, AVR64SD32, AVR64SD48. + * doc/avr-mmcu.texi: Rebuild. + +2025-03-23 Georg-Johann Lay <avr@gjlay.de> + + * doc/invoke.texi (AVR Optimization Options) + <-maccumulate-args>: Refer to -fdefer-pop. + <-muse-nonzero-bits>: Re-formulate what the option does. + +2025-03-22 Georg-Johann Lay <avr@gjlay.de> + + * config/avr/avr.cc (avr_option_override): Use + "avr-peep2-after-fuse-move" as dump name instead of "peephole2". + +2025-03-22 Georg-Johann Lay <avr@gjlay.de> + + * config/avr/avr.opt.urls: Add -muse-nonzero-bits. + +2025-03-22 Georg-Johann Lay <avr@gjlay.de> + + PR target/119421 + * config/avr/avr.opt (-muse-nonzero-bits): New option. + * config/avr/avr-protos.h (avr_nonzero_bits_lsr_operands_p): New. + (make_avr_pass_split_nzb): New. + * config/avr/avr.cc (avr_nonzero_bits_lsr_operands_p): New function. + (avr_rtx_costs_1): Return costs for the new insns. + * config/avr/avr.md (nzb): New insn attribute. + (*nzb=1.<code>...): New insns to better support some bit + operations for <code> in AND, IOR, XOR. + * config/avr/avr-passes.def (avr_pass_split_nzb): Insert pass + atfer combine. + * config/avr/avr-passes.cc (avr_pass_data_split_nzb). New pass data. + (avr_pass_split_nzb): New pass. + (make_avr_pass_split_nzb): New function. + * common/config/avr/avr-common.cc (avr_option_optimization_table): + Enable -muse-nonzero-bits for -O2 and higher. + * doc/invoke.texi (AVR Options): Document -muse-nonzero-bits. + +2025-03-22 Georg-Johann Lay <avr@gjlay.de> + + * config/avr/avr.cc (avr_attrs_section_name): New function. + (avr_insert_attributes): Add "used" attribute to functions + in .initN and .finiN. + +2025-03-22 Iain Sandoe <iain@sandoe.co.uk> + + * config/darwin.h (DL_LIBRARY): New. + +2025-03-22 Jakub Jelinek <jakub@redhat.com> + + * gimplify.cc (warn_switch_unreachable_and_auto_init_r): Add missing + space in the middle of diagnostics. + * tree-vect-stmts.cc (vectorizable_load): Add missing space in the + middle of debug dump message. + * sym-exec/sym-exec-state.cc (state::check_args_compatibility): + Likewise. + +2025-03-21 Surya Kumari Jangala <jskumari@linux.ibm.com> + Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/116028 + PR rtl-optimization/118615 + * lra-constraints.cc (first_call_insn): New variable. + (split_reg): Spill register before first_call_insn if call_save_p + and the call is in a different bb in the ebb. + (split_if_necessary): Formatting fix. + (inherit_in_ebb): Set first_call_insn when handling a CALL_INSN. + For successful split_if_necessary with before_p, only change + use_insn if it emitted any new instructions before curr_insn. + Clear first_call_insn before returning. + +2025-03-21 Paul-Antoine Arras <parras@baylibre.com> + Tobias Burnus <tburnus@baylibre.com> + + * builtin-types.def + (BT_FN_VOID_INT_INT_PTR_PTR_PTR_INT_PTR_INT_PTR_UINT_PTR): New. + * gimple-low.cc (lower_stmt): Handle GIMPLE_OMP_INTEROP. + * gimple-pretty-print.cc (dump_gimple_omp_interop): New function. + (pp_gimple_stmt_1): Handle GIMPLE_OMP_INTEROP. + * gimple.cc (gimple_build_omp_interop): New function. + (gimple_copy): Handle GIMPLE_OMP_INTEROP. + * gimple.def (GIMPLE_OMP_INTEROP): Define. + * gimple.h (gimple_build_omp_interop): Declare. + (gimple_omp_interop_clauses): New function. + (gimple_omp_interop_clauses_ptr): Likewise. + (gimple_omp_interop_set_clauses): Likewise. + (gimple_return_set_retval): Handle GIMPLE_OMP_INTEROP. + * gimplify.cc (gimplify_scan_omp_clauses): Handle OMP_CLAUSE_INIT, + OMP_CLAUSE_USE and OMP_CLAUSE_DESTROY. + (gimplify_omp_interop): New function. + (gimplify_expr): Replace sorry with call to gimplify_omp_interop. + * omp-builtins.def (BUILT_IN_GOMP_INTEROP): Define. + * omp-low.cc (scan_sharing_clauses): Handle OMP_CLAUSE_INIT, + OMP_CLAUSE_USE and OMP_CLAUSE_DESTROY. + (scan_omp_1_stmt): Handle GIMPLE_OMP_INTEROP. + (lower_omp_interop_action_clauses): New function. + (lower_omp_interop): Likewise. + (lower_omp_1): Handle GIMPLE_OMP_INTEROP. + +2025-03-21 Jason Merrill <jason@redhat.com> + + PR c++/114992 + * multiple_target.cc (create_dispatcher_calls): + remove_from_same_comdat_group before add_to_same_comdat_group. + +2025-03-21 Dhruv Chawla <dhruvc@nvidia.com> + + * config/aarch64/aarch64-cores.def (olympus): New entry. + * config/aarch64/aarch64-tune.md: Regenerate. + * doc/invoke.texi (AArch64 Options): Document the above. + +2025-03-21 Antoni Boucher <bouanto@zoho.com> + + * config/i386/i386-rust-and-jit.inc: New file. + * config/i386/i386-rust.cc: Move code to i386-rust-and-jit.inc. + +2025-03-21 Jakub Jelinek <jakub@redhat.com> + + PR ipa/119376 + * ipa-icf-gimple.cc (func_checker::compare_gimple_call): Return false + for gimple_call_must_tail_p mismatches. + +2025-03-21 Jakub Jelinek <jakub@redhat.com> + + PR ipa/119376 + * ipa-split.cc (split_function): Call gimple_call_set_must_tail + on the call to outlined partition if has_musttail and + !add_tsan_func_exit. + +2025-03-21 Jakub Jelinek <jakub@redhat.com> + + PR ipa/119376 + * tree-inline.cc (remap_gimple_stmt): Silently clear + gimple_call_must_tail_p on inlined call stmts if id->call_stmt + is a call without that flag set. + +2025-03-21 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org> + + PR target/119235 + * config/s390/s390.cc (s390_hard_regno_mode_ok): Accept only + Pmode for registers AP/FP/RA. + +2025-03-21 Richard Biener <rguenther@suse.de> + + * cgraphunit.cc (symbol_table::finalize_compilation_unit): + Put early debug generation under TV_SYMOUT. + +2025-03-21 Andrew Pinski <quic_apinski@quicinc.com> + + PR rtl-optimization/118914 + * combine.cc (recog_for_combine): Add old_nregs and new_nregs + argument (defaulting to 0). Update call to recog_for_combine_1. + (combine_split_insns): Add old_nregs and new_nregs arguments, + store the old and new max registers to them. + (try_combine): Update calls to combine_split_insns and + pass old_nregs and new_nregs for the i3 call to recog_for_combine. + (find_split_point): Update call to combine_split_insns; ignoring + the values there. + (recog_for_combine_1): Add old_nregs and new_nregs arguments, + if the insn was recognized (and not to no-op move), add the + REG_DEAD notes to pnotes argument. + +2025-03-20 Richard Biener <rguenther@suse.de> + + PR tree-optimization/119389 + * tree-ssa-sccvn.cc (dominated_by_p_w_unex): Limit the number + of predecessors of a CFG merge we try to skip. + +2025-03-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org> + + Revert: + 2025-03-11 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org> + + * config.gcc: Fail in case of option --with-mode=esa. + * config/s390/s390.cc (s390_option_override_internal): Default + to z/Architecture mode. + * config/s390/s390.h (DRIVER_SELF_SPECS): Ditto. + * config/s390/s390.opt: Emit a warning for option -mesa. + * doc/invoke.texi: Document the change. + +2025-03-20 Filip Kastl <fkastl@suse.cz> + + * gimple-ssa-sccopy.cc (scc_copy_prop::propagate): Don't + increment after vec::unordered_remove(). + +2025-03-20 Richard Biener <rguenther@suse.de> + + * tree-core.h (function_decl_type): Make a scoped enum. + * tree.h (set_function_decl_type): Adjust. + (DECL_IS_OPERATOR_NEW_P): Likewise. + (DECL_SET_IS_OPERATOR_NEW): Likewise. + (DECL_IS_OPERATOR_DELETE_P): Likewise. + (DECL_SET_IS_OPERATOR_DELETE): Likewise. + (DECL_LAMBDA_FUNCTION_P): Likewise. + (DECL_SET_LAMBDA_FUNCTION): Likewise. + * lto-streamer-out.cc (hash_tree): Hash all of + FUNCTION_DECL_DECL_TYPE. + * tree-streamer-out.cc (pack_ts_function_decl_value_fields): + Adjust. + * config/aarch64/aarch64-simd-pragma-builtins.def (vcombine_mf8): + Use literal zero instead of NONE. + +2025-03-20 liuhongt <hongtao.liu@intel.com> + + PR target/117452 + * config/i386/i386.md (cbranchbf4): Use + ix86_fp_comparison_operator instead of comparison_operator. + +2025-03-20 Hu, Lin1 <lin1.hu@intel.com> + + * config/i386/avx10_2-512satcvtintrin.h: Add "s_" before + intrinsics' core name. + * config/i386/avx10_2satcvtintrin.h: Ditto. + +2025-03-20 Hu, Lin1 <lin1.hu@intel.com> + + * config/i386/avx10_2-512satcvtintrin.h: Add new intrinsics. + * config/i386/avx10_2satcvtintrin.h: Ditto. + * config/i386/i386-builtin-types.def: + Add DEF_FUNCTION_TYPE (V32HI, V32HF, V32HI, USI), + (V16SI, V16SF, V16SI, UHI), (V8DI, V8SF, V8DI, UQI), + (V8DI, V8DF, V8DI, UQI), (V8SI, V8DF, V8SI, UQI). + * config/i386/i386-builtin.def: Add new builtins. + * config/i386/i386-expand.cc: Handle V16SI_FTYPE_V16SF_V16SI_UHI, + V32HI_FTYPE_V32HF_V32HI_USI, V8DI_FTYPE_V8SF_V8DI_UQI, + V8DI_FTYPE_V8DF_V8DI_UQI, V8SI_FTYPE_V8DF_V8SI_UQI. + +2025-03-20 Hu, Lin1 <lin1.hu@intel.com> + + * config/i386/avx10_2-512satcvtintrin.h: Change *i[u]bs's type suffix + of intrin name. + * config/i386/avx10_2satcvtintrin.h: Ditto. + 2025-03-19 Vladimir N. Makarov <vmakarov@redhat.com> PR target/119270 |