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Diffstat (limited to 'gcc/ChangeLog')
| -rw-r--r-- | gcc/ChangeLog | 332 |
1 files changed, 332 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1eb1ada..d4ef4f9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,335 @@ +2025-12-09 John Ericson <git@JohnEricson.me> + + * Makefile.in: No longer include TARGET_SYSTEM_ROOT in + libgcc.mvars. + +2025-12-09 John Ericson <git@JohnEricson.me> + + * Makefile.in:: Remove NO_PIE_CFLAGS logic, since it is now in + libgcc. + * configure: Regenerate. + * configure.ac: Remove the enable_default_pie substitution, since + libgcc now has its own logic. + +2025-12-09 Robin Dapp <rdapp@ventanamicro.com> + + PR tree-optimization/123074 + * tree-vect-loop.cc: Reset LOOP_VINFO_USING_SELECT_VL_P. + +2025-12-09 Pan Li <pan2.li@intel.com> + + * config/riscv/predicates.md: Append operator lt to + the comparison_swappable_operator. + * config/riscv/riscv-v.cc (get_swapped_cmp_rtx_code): Add + swappable operator lt handing. + +2025-12-09 Richard Biener <rguenther@suse.de> + + PR target/121230 + * config/i386/i386.cc (ix86_vector_costs::add_stmt_cost): + With FP mode and 387 math cost spill/reload. + +2025-12-09 Robin Dapp <rdapp@ventanamicro.com> + + * config/riscv/riscv.opt.urls: Regenerate. + +2025-12-09 Andrew Stubbs <ams@baylibre.com> + + * config/gcn/gcn.cc (gcn_init_cumulative_args): Only warn once. + Use "required" instead of "enabled" in the warning. + * config/gcn/mkoffload.cc (process_asm): Warn, don't error. + Use "required" instead of "on" in the warning. + +2025-12-09 Robin Dapp <rdapp@ventanamicro.com> + + PR tree-optimization/122635 + * gimple-fold.cc (enum mask_load_store_state): New enum. + (gimple_fold_partial_load_store_mem_ref): Only fold + "all active" loads/stores. + (partial_load_store_mask_state): New function to compute mask + state. + (gimple_fold_partial_load): Remove. + (gimple_fold_partial_load_store): New function. + (gimple_fold_partial_store): Remove. + (gimple_fold_call): Use new function. + +2025-12-09 Robin Dapp <rdapp@ventanamicro.com> + + * config/rs6000/predicates.md (lxvl_else_operand): New + predicate. + * config/rs6000/vsx.md: Add else operand. + * config/s390/predicates.md (vll_else_operand): New predicate. + * config/s390/vector.md: Add else operand. + * doc/md.texi: Document else operand. + * internal-fn.cc (internal_fn_len_index): Adjust IFN_LEN_LOAD. + (internal_fn_else_index): Add IFN_LEN_LOAD. + * optabs-tree.cc (target_supports_len_load_store_p): Get else + value for len_load. + * tree-vect-stmts.cc (vectorizable_load): Pun the else value + type. + +2025-12-09 Robin Dapp <rdapp@ventanamicro.com> + + * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::handle_max_vect): + New parser entry. + (riscv_target_attr_parser::update_settings): Set max-vect + option. + (riscv_process_one_target_attr): Change null-arg handling. + * config/riscv/riscv.cc (riscv_override_options_internal): Set + max-vect option. + * config/riscv/riscv.opt: Add -mmax-vectorization option. + * doc/extend.texi: Document new option. + * doc/invoke.texi: Ditto. + +2025-12-09 Robin Dapp <rdapp@ventanamicro.com> + + PR target/123022 + * config/riscv/vector.md: Add mode_idx attribute. + +2025-12-09 Robin Dapp <rdapp@ventanamicro.com> + + PR target/115325 + * config/riscv/riscv-c.cc (riscv_pragma_target_parse): New + function. + (riscv_register_pragmas): Register riscv_pragma_target_parse. + * config/riscv/riscv-protos.h (riscv_process_target_attr_for_pragma): + Declare. + (riscv_reset_previous_fndecl): Ditto. + * config/riscv/riscv-target-attr.cc (riscv_process_target_attr_for_pragma): + New function. + * config/riscv/riscv.cc (riscv_reset_previous_fndecl): Reset. + (riscv_option_save): New function. + (riscv_option_print): Ditto. + (riscv_get_interrupt_type): Adjust docs. + (TARGET_OPTION_SAVE): Implement. + (TARGET_OPTION_PRINT): Ditto. + * doc/extend.texi: Document that riscv can do target pragams. + +2025-12-09 Robin Dapp <rdapp@ventanamicro.com> + + * config/riscv/autovec.md (reduc_sbool_and_scal_<mode>): New + expander. + (reduc_sbool_ior_scal_<mode>): Ditto. + (reduc_sbool_xor_scal_<mode>): Ditto. + * config/riscv/riscv-protos.h (expand_mask_reduction): Declare. + * config/riscv/riscv-v.cc (expand_mask_reduction): New function. + +2025-12-09 Richard Biener <rguenther@suse.de> + + PR target/123027 + * config/i386/i386-expand.cc (ix86_expand_sse_fp_minmax): + With !HONOR_NANS we can handle LE by swapping and inverting. + +2025-12-08 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR tree-optimization/46555 + * tree-cfgcleanup.cc (execute_cleanup_cfg_post_optimizing): + Don't set todo to include cleanupcfg; do it manually. + Call make_forwarders_with_degenerate_phis if optimizing. + +2025-12-08 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * tree-cfg.cc (make_forwarders_with_degenerate_phis): Add debug + dump. + +2025-12-08 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * tree-ssa-dce.cc (sort_phi_args): Move to tree-cfg.cc. + (make_forwarders_with_degenerate_phis): Move to tree-cfg.cc. + (perform_tree_ssa_dce): Update for the updated return type + of make_forwarders_with_degenerate_phis. + * tree-cfg.cc (sort_phi_args): Moved from tree-ssa-dce.cc. + (make_forwarders_with_degenerate_phis): Moved from tree-ssa-dce.cc. + Update return type to bool and return true if an edge was split. + * tree-cfg.h (make_forwarders_with_degenerate_phis): New decl. + +2025-12-08 Eric Botcazou <ebotcazou@adacore.com> + + PR target/80881 + * config/mingw/winnt.cc (mingw_pe_unique_section): Put two dollar + signs for TLS sections after the prefix. + (mingw_pe_asm_named_section): Deal with all TLS sections uniformly. + +2025-12-08 Ezra Sitorus <Ezra.Sitorus@arm.com> + + * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add C1-Nano, + C1-Pro, C1-Premium and C1-Ultra. + * config/aarch64/aarch64-tune.md: Regenerate. + * doc/invoke.texi: Document C1 cores. + +2025-12-08 Richard Biener <rguenther@suse.de> + + PR tree-optimization/123040 + * tree-ssa-sccvn.cc (vn_nary_build_or_lookup_1): Only insert + nary results. + +2025-12-08 Josef Melcr <josef.melcr@suse.com> + + PR ipa/122798 + * cgraph.cc (cgraph_edge::redirect_callee): Use + iterate_referring instead of referred_to_p. + * cgraphclones.cc (set_new_clone_decl_and_node_flags): Set local + to true iff the node does not have its address taken. + +2025-12-08 Richard Biener <rguenther@suse.de> + + PR tree-optimization/123038 + * tree-vect-patterns.cc (vect_recog_ctz_ffs_pattern): Reject + pattern for reductions when the call argument is used multiple + times. + +2025-12-08 Tamar Christina <tamar.christina@arm.com> + + PR target/123026 + * config/aarch64/aarch64-simd.md (reduc_sbool_ior_scal_<mode>, + reduc_sbool_and_scal_<mode>): Fix tmp operands[1] override. + +2025-12-08 Tamar Christina <tamar.christina@arm.com> + + PR tree-optimization/122868 + * tree-vect-stmts.cc (vectorizable_load): Move check for invariant loads + down into the loop. + +2025-12-08 H.J. Lu <hjl.tools@gmail.com> + + PR target/122343 + * config/i386/sse.md (*<avx512>_cmp<mode>3_dup_op): Don't allow + 2 volatile memory references. + +2025-12-07 Jason Merrill <jason@redhat.com> + + * config/darwin-c.cc (find_subframework_header): Use + _cpp_get_file_*. + +2025-12-07 H.J. Lu <hjl.tools@gmail.com> + + PR target/122343 + * common.opt: Add -ffuse-ops-with-volatile-access. + * common.opt.urls: Regenerated. + * recog.cc (general_operand): Allow volatile memory reference if + -ffuse-ops-with-volatile-access is enabled. + * simplify-rtx.cc (simplify_binary_operation_1): Keep PLUS for 2 + volatile memory references. + * doc/invoke.texi: Document -ffuse-ops-with-volatile-access. + +2025-12-07 Alexandre Oliva <oliva@adacore.com> + + * cselib.cc (dump_cselib_val): Split out of and rename to... + (dump_cselib_val_ptr): ... this. + (dump_cselib_table): Adjust. Skip cselib_preserved_hash_table + when not allocated. + +2025-12-06 Alexandre Oliva <oliva@adacore.com> + + PR rtl-optimization/122947 + * calls.cc (expand_call): Add stack function usage in + non-ACCUMULATE_OUTGOING_ARGS configurations. + +2025-12-06 Alexandre Oliva <oliva@adacore.com> + + PR target/91420 + * config/riscv/riscv.cc (riscv_symbolic_constant_p): Require + offsets smaller than +/- 1GiB for PCREL symbols. + +2025-12-06 Jakub Jelinek <jakub@redhat.com> + + * attribs.cc (decl_attributes): Use attribute_value_equal to + compare attribute values instead of simple_cst_equal. + +2025-12-06 Dimitar Dimitrov <dimitar@dinux.eu> + + PR rtl-optimization/122675 + * bb-reorder.cc (edge_order): Fix BB edge ordering to be + descending. + +2025-12-05 Vladimir N. Makarov <vmakarov@redhat.com> + + PR rtl-optimization/122215 + * ira-color.cc (improve_allocation): Use register filter for all + loop on hard regs. + +2025-12-05 Richard Earnshaw <rearnsha@arm.com> + + PR target/122999 + * config/arm/arm.cc (arm_canonicalize_comparison): Defer + initializing maxval until we know we are dealing with an + integer mode. + +2025-12-05 Richard Biener <rguenther@suse.de> + + * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p): + When peeling for gaps we always need an epilog. + +2025-12-05 Richard Biener <rguenther@suse.de> + + PR tree-optimization/120939 + * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p): + Remove eliding an epilogue based on not computed + LOOP_VINFO_COST_MODEL_THRESHOLD and estimated max stmt executions. + +2025-12-05 Richard Biener <rguenther@suse.de> + + PR tree-optimization/123002 + * tree-vectorizer.h (supportable_widening_operation): Remove + vinfo and stmt_info parameters, add flag to indicate whether + the context would allow OP_{EVEN,ODD}. + * tree-vect-patterns.cc (vect_recog_abd_pattern): Adjust + and pass false. + (vect_recog_widen_op_pattern): Likewise. + (vect_recog_widen_abd_pattern): Likewise. + * tree-vect-stmts.cc (vectorizable_conversion): Move + even/odd validity check here, from supportable_widening_operation. + Adjust it to be conservative. + (supportable_widening_operation): Get flag whether even/odd + is OK to use and remove then unused parameters and code. + +2025-12-05 Richard Biener <rguenther@suse.de> + + * tree-pretty-print.cc (dump_mem_ref): Dump clique : base + specifier for MEM_REF and TARGET_MEM_REF when dumping + GIMPLE format. + +2025-12-05 Tobias Burnus <tburnus@baylibre.com> + + * gimplify.cc (gimplify_scan_omp_clauses): Handle + OMP_CLAUSE_DYN_GROUPPRIVATE by printing 'sorry, unimplemented'. + * tree-core.h (enum omp_clause_code): Add OMP_CLAUSE_DYN_GROUPPRIVATE. + (enum omp_clause_fallback_kind): New. + (struct tree_omp_clause): Add fallback_kind union member. + * tree-nested.cc (convert_nonlocal_omp_clauses, + convert_local_omp_clauses): Handle OMP_CLAUSE_DYN_GROUPPRIVATE. + * tree.cc (omp_clause_num_ops, omp_clause_code_name): Add + OMP_CLAUSE_DYN_GROUPPRIVATE. + * tree-pretty-print.cc (dump_omp_clause): Handle + OMP_CLAUSE_DYN_GROUPPRIVATE. + * tree.h (OMP_CLAUSE_DYN_GROUPPRIVATE_EXPR, + OMP_CLAUSE_DYN_GROUPPRIVATE_KIND): New #define. + +2025-12-05 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR middle-end/99782 + * config/i386/i386-expand.cc (ix86_gen_ccmp_next): Move the check + for mode earlier before expand_operands. + * config/aarch64/aarch64.cc (aarch64_gen_ccmp_next): Likewise. + +2025-12-05 Daniel Barboza <dbarboza@ventanamicro.com> + Jeff Law <jlaw@ventanamicro.com> + + * match.pd (`x & c ? (x - c) | (x | c)`): New pattern. + (`x & c ? (x & ~c) | (x | c)`): Likewise. + +2025-12-05 Pan Li <pan2.li@intel.com> + + * config/riscv/autovec-opt.md (*pred_cmp_swapped<mode>_scalar): + Add new pattern to match vec_dup > vec for vmsltu. + * config/riscv/predicates.md (comparison_swappable_operator): + Add new iterator for above pattern + * config/riscv/riscv-protos.h (expand_vx_cmp_vec_dup_vec): Add + new func to emit vmsltu.vx. + * config/riscv/riscv-v.cc (get_swapped_cmp_rtx_code): Add new + func to convert cmp code to swapped, like gtu to ltu. + (expand_vx_cmp_vec_dup_vec): Add new func decl. + 2025-12-04 Jakub Jelinek <jakub@redhat.com> PR target/122991 |