diff options
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/common/config/arc/arc-common.c | 3 | ||||
| -rw-r--r-- | gcc/config/arc/arc-opts.h | 1 | ||||
| -rw-r--r-- | gcc/config/arc/arc.c | 14 | ||||
| -rw-r--r-- | gcc/config/arc/arc.h | 7 | ||||
| -rw-r--r-- | gcc/config/arc/arc.md | 6 | ||||
| -rw-r--r-- | gcc/config/arc/arc.opt | 9 | ||||
| -rw-r--r-- | gcc/config/arc/constraints.md | 2 | ||||
| -rw-r--r-- | gcc/config/arc/t-arc-newlib | 3 |
9 files changed, 19 insertions, 34 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 17b46e7..9266593 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2015-09-10 Claudiu Zissulescu <claziss@synopsys.com> + + * common/config/arc/arc-common.c: Remove references to A5. + * config/arc/arc-opts.h: Likewise. + * config/arc/arc.c, config/arc/arc.h, config/arc/arc.md: Likewise. + * config/arc/arc.opt, config/arc/constraints.md: Likewise. + * config/arc/t-arc-newlib: Likewise. + 2015-09-10 Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.md (length): Fix attribute length for conditional diff --git a/gcc/common/config/arc/arc-common.c b/gcc/common/config/arc/arc-common.c index 95993df..489bdb2 100644 --- a/gcc/common/config/arc/arc-common.c +++ b/gcc/common/config/arc/arc-common.c @@ -33,7 +33,7 @@ arc_option_init_struct (struct gcc_options *opts) { opts->x_flag_no_common = 255; /* Mark as not user-initialized. */ - /* Which cpu we're compiling for (A5, ARC600, ARC601, ARC700). */ + /* Which cpu we're compiling for (ARC600, ARC601, ARC700). */ arc_cpu = PROCESSOR_NONE; } @@ -82,7 +82,6 @@ arc_handle_option (struct gcc_options *opts, struct gcc_options *opts_set, switch (value) { - case PROCESSOR_A5: case PROCESSOR_ARC600: case PROCESSOR_ARC700: if (! (opts_set->x_target_flags & MASK_BARREL_SHIFTER) ) diff --git a/gcc/config/arc/arc-opts.h b/gcc/config/arc/arc-opts.h index f259a47..cca1f03 100644 --- a/gcc/config/arc/arc-opts.h +++ b/gcc/config/arc/arc-opts.h @@ -21,7 +21,6 @@ enum processor_type { PROCESSOR_NONE, - PROCESSOR_A5, PROCESSOR_ARC600, PROCESSOR_ARC601, PROCESSOR_ARC700 diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index b5b644c..e9ecc90 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -77,7 +77,7 @@ along with GCC; see the file COPYING3. If not see #include "builtins.h" #include "rtl-iter.h" -/* Which cpu we're compiling for (A5, ARC600, ARC601, ARC700). */ +/* Which cpu we're compiling for (ARC600, ARC601, ARC700). */ static const char *arc_cpu_string = ""; /* ??? Loads can handle any constant, stores can only handle small ones. */ @@ -702,11 +702,7 @@ arc_init (void) { enum attr_tune tune_dflt = TUNE_NONE; - if (TARGET_A5) - { - arc_cpu_string = "A5"; - } - else if (TARGET_ARC600) + if (TARGET_ARC600) { arc_cpu_string = "ARC600"; tune_dflt = TUNE_ARC600; @@ -755,7 +751,7 @@ arc_init (void) break; } - /* Support mul64 generation only for A5 and ARC600. */ + /* Support mul64 generation only for ARC600. */ if (TARGET_MUL64_SET && TARGET_ARC700) error ("-mmul64 not supported for ARC700"); @@ -1280,7 +1276,7 @@ arc_conditional_register_usage (void) i <= ARC_LAST_SIMD_DMA_CONFIG_REG; i++) reg_alloc_order [i] = i; } - /* For Arctangent-A5 / ARC600, lp_count may not be read in an instruction + /* For ARC600, lp_count may not be read in an instruction following immediately after another one setting it to a new value. There was some discussion on how to enforce scheduling constraints for processors with missing interlocks on the gcc mailing list: @@ -2093,7 +2089,7 @@ arc_compute_frame_size (int size) /* size = # of var. bytes allocated. */ total_size = ARC_STACK_ALIGN (total_size); /* Compute offset of register save area from stack pointer: - A5 Frame: pretend_size <blink> reg_size <fp> var_size args_size <--sp + Frame: pretend_size <blink> reg_size <fp> var_size args_size <--sp */ reg_offset = (total_size - (pretend_size + reg_size + extra_size) + (frame_pointer_needed ? 4 : 0)); diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h index d98cce1..874b118 100644 --- a/gcc/config/arc/arc.h +++ b/gcc/config/arc/arc.h @@ -66,9 +66,7 @@ along with GCC; see the file COPYING3. If not see #define TARGET_CPU_CPP_BUILTINS() \ do { \ builtin_define ("__arc__"); \ - if (TARGET_A5) \ - builtin_define ("__A5__"); \ - else if (TARGET_ARC600) \ + if (TARGET_ARC600) \ { \ builtin_define ("__A6__"); \ builtin_define ("__ARC600__"); \ @@ -133,7 +131,6 @@ along with GCC; see the file COPYING3. If not see #define ASM_SPEC "\ %{mbig-endian|EB:-EB} %{EL} \ -%{mcpu=A5|mcpu=a5|mA5:-mA5} \ %{mcpu=ARC600:-mARC600} \ %{mcpu=ARC601:-mARC601} \ %{mcpu=ARC700:-mARC700} \ @@ -224,7 +221,6 @@ along with GCC; see the file COPYING3. If not see #endif #define DRIVER_SELF_SPECS DRIVER_ENDIAN_SELF_SPECS \ - "%{mARC5|mA5: -mcpu=A5 %<mARC5 %<mA5}" \ "%{mARC600|mA6: -mcpu=ARC600 %<mARC600 %<mA6}" \ "%{mARC601: -mcpu=ARC601 %<mARC601}" \ "%{mARC700|mA7: -mcpu=ARC700 %<mARC700 %<mA7}" \ @@ -277,7 +273,6 @@ along with GCC; see the file COPYING3. If not see use conditional execution? */ #define TARGET_AT_DBR_CONDEXEC (!TARGET_ARC700) -#define TARGET_A5 (arc_cpu == PROCESSOR_A5) #define TARGET_ARC600 (arc_cpu == PROCESSOR_ARC600) #define TARGET_ARC601 (arc_cpu == PROCESSOR_ARC601) #define TARGET_ARC700 (arc_cpu == PROCESSOR_ARC700) diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index cfc4d32..e1da4d7 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -188,7 +188,7 @@ ;; Attribute describing the processor -(define_attr "cpu" "none,A5,ARC600,ARC700" +(define_attr "cpu" "none,ARC600,ARC700" (const (symbol_ref "arc_cpu_attr"))) ;; true for compact instructions (those with _s suffix) @@ -4903,9 +4903,7 @@ ; operand 0 is the loop count pseudo register ; operand 1 is the label to jump to at the top of the loop -; Use this for the ARC600 and ARC700. For ARCtangent-A5, this is unsafe -; without further checking for nearby branches etc., and without proper -; annotation of shift patterns that clobber lp_count +; Use this for the ARC600 and ARC700. ; ??? ARC600 might want to check if the loop has few iteration and only a ; single insn - loop setup is expensive then. (define_expand "doloop_end" diff --git a/gcc/config/arc/arc.opt b/gcc/config/arc/arc.opt index 6352a2e..7c859e4 100644 --- a/gcc/config/arc/arc.opt +++ b/gcc/config/arc/arc.opt @@ -33,10 +33,6 @@ mno-cond-exec Target Report RejectNegative Mask(NO_COND_EXEC) Disable ARCompact specific pass to generate conditional execution instructions -mA5 -Target Report -Generate ARCompact 32-bit code for ARCtangent-A5 processor - mA6 Target Report Generate ARCompact 32-bit code for ARC600 processor @@ -61,7 +57,7 @@ mmixed-code Target Report Mask(MIXED_CODE_SET) Tweak register allocation to help 16-bit instruction generation ; originally this was: -;Generate ARCompact 16-bit instructions intermixed with 32-bit instructions for ARCtangent-A5 and higher processors +;Generate ARCompact 16-bit instructions intermixed with 32-bit instructions ; but we do that without -mmixed-code, too, it's just a different instruction ; count / size tradeoff. @@ -163,9 +159,6 @@ Enum Name(processor_type) Type(enum processor_type) EnumValue -Enum(processor_type) String(A5) Value(PROCESSOR_A5) - -EnumValue Enum(processor_type) String(ARC600) Value(PROCESSOR_ARC600) EnumValue diff --git a/gcc/config/arc/constraints.md b/gcc/config/arc/constraints.md index 9540075..8902246 100644 --- a/gcc/config/arc/constraints.md +++ b/gcc/config/arc/constraints.md @@ -21,7 +21,7 @@ ; Most instructions accept arbitrary core registers for their inputs, even ; if the core register in question cannot be written to, like the multiply -; result registers of the ARCtangent-A5 and ARC600 . +; result registers of ARC600. ; First, define a class for core registers that can be read cheaply. This ; is most or all core registers for ARC600, but only r0-r31 for ARC700 (define_register_constraint "c" "CHEAP_CORE_REGS" diff --git a/gcc/config/arc/t-arc-newlib b/gcc/config/arc/t-arc-newlib index 135bef6..8823805 100644 --- a/gcc/config/arc/t-arc-newlib +++ b/gcc/config/arc/t-arc-newlib @@ -17,8 +17,6 @@ # with GCC; see the file COPYING3. If not see # <http://www.gnu.org/licenses/>. -# Selecting -mA5 uses the same functional multilib files/libraries -# as get used for -mARC600 aka -mA6. MULTILIB_OPTIONS=mcpu=ARC600/mcpu=ARC601 mmul64/mmul32x16 mnorm MULTILIB_DIRNAMES=arc600 arc601 mul64 mul32x16 norm # @@ -26,7 +24,6 @@ MULTILIB_DIRNAMES=arc600 arc601 mul64 mul32x16 norm MULTILIB_MATCHES = mcpu?ARC600=mcpu?arc600 MULTILIB_MATCHES += mcpu?ARC600=mARC600 MULTILIB_MATCHES += mcpu?ARC600=mA6 -MULTILIB_MATCHES += mcpu?ARC600=mA5 MULTILIB_MATCHES += mcpu?ARC600=mno-mpy MULTILIB_MATCHES += mcpu?ARC601=mcpu?arc601 MULTILIB_MATCHES += EL=mlittle-endian |