diff options
-rw-r--r-- | gcc/ChangeLog | 13 | ||||
-rw-r--r-- | gcc/config/i386/i386-protos.h | 1 | ||||
-rw-r--r-- | gcc/config/i386/i386.c | 2 | ||||
-rw-r--r-- | gcc/config/i386/sse.md | 81 |
4 files changed, 96 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7b740a7..ade9a3b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,18 @@ 2015-11-10 Ilya Enkovich <enkovich.gnu@gmail.com> + * config/i386/i386-protos.h (ix86_expand_sse_movcc): New. + * config/i386/i386.c (ix86_expand_sse_movcc): Make public. + Cast mask to FP mode if required. + * config/i386/sse.md (vcond_mask_<mode><avx512fmaskmodelower>): New. + (vcond_mask_<mode><avx512fmaskmodelower>): New. + (vcond_mask_<mode><sseintvecmodelower>): New. + (vcond_mask_<mode><sseintvecmodelower>): New. + (vcond_mask_v2div2di): New. + (vcond_mask_<mode><sseintvecmodelower>): New. + (vcond_mask_<mode><sseintvecmodelower>): New. + +2015-11-10 Ilya Enkovich <enkovich.gnu@gmail.com> + * optabs-query.h (get_vcond_mask_icode): New. * optabs-tree.c (expand_vec_cond_expr_p): Use get_vcond_mask_icode for VEC_COND_EXPR with mask. diff --git a/gcc/config/i386/i386-protos.h b/gcc/config/i386/i386-protos.h index 9e20714..bd084dc 100644 --- a/gcc/config/i386/i386-protos.h +++ b/gcc/config/i386/i386-protos.h @@ -132,6 +132,7 @@ extern bool ix86_expand_vec_perm_const (rtx[]); extern bool ix86_expand_mask_vec_cmp (rtx[]); extern bool ix86_expand_int_vec_cmp (rtx[]); extern bool ix86_expand_fp_vec_cmp (rtx[]); +extern void ix86_expand_sse_movcc (rtx, rtx, rtx, rtx); extern void ix86_expand_sse_unpack (rtx, rtx, bool, bool); extern bool ix86_expand_int_addcc (rtx[]); extern rtx ix86_expand_call (rtx, rtx, rtx, rtx, rtx, bool); diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index f6c17df..b84a11d 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -22633,7 +22633,7 @@ ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1, /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical operations. This is used for both scalar and vector conditional moves. */ -static void +void ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false) { machine_mode mode = GET_MODE (dest); diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index f804255..452629f 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -3015,6 +3015,87 @@ DONE; }) +(define_expand "vcond_mask_<mode><avx512fmaskmodelower>" + [(set (match_operand:V48_AVX512VL 0 "register_operand") + (vec_merge:V48_AVX512VL + (match_operand:V48_AVX512VL 1 "nonimmediate_operand") + (match_operand:V48_AVX512VL 2 "vector_move_operand") + (match_operand:<avx512fmaskmode> 3 "register_operand")))] + "TARGET_AVX512F") + +(define_expand "vcond_mask_<mode><avx512fmaskmodelower>" + [(set (match_operand:VI12_AVX512VL 0 "register_operand") + (vec_merge:VI12_AVX512VL + (match_operand:VI12_AVX512VL 1 "nonimmediate_operand") + (match_operand:VI12_AVX512VL 2 "vector_move_operand") + (match_operand:<avx512fmaskmode> 3 "register_operand")))] + "TARGET_AVX512BW") + +(define_expand "vcond_mask_<mode><sseintvecmodelower>" + [(set (match_operand:VI_256 0 "register_operand") + (vec_merge:VI_256 + (match_operand:VI_256 1 "nonimmediate_operand") + (match_operand:VI_256 2 "vector_move_operand") + (match_operand:<sseintvecmode> 3 "register_operand")))] + "TARGET_AVX2" +{ + ix86_expand_sse_movcc (operands[0], operands[3], + operands[1], operands[2]); + DONE; +}) + +(define_expand "vcond_mask_<mode><sseintvecmodelower>" + [(set (match_operand:VI124_128 0 "register_operand") + (vec_merge:VI124_128 + (match_operand:VI124_128 1 "nonimmediate_operand") + (match_operand:VI124_128 2 "vector_move_operand") + (match_operand:<sseintvecmode> 3 "register_operand")))] + "TARGET_SSE2" +{ + ix86_expand_sse_movcc (operands[0], operands[3], + operands[1], operands[2]); + DONE; +}) + +(define_expand "vcond_mask_v2div2di" + [(set (match_operand:V2DI 0 "register_operand") + (vec_merge:V2DI + (match_operand:V2DI 1 "nonimmediate_operand") + (match_operand:V2DI 2 "vector_move_operand") + (match_operand:V2DI 3 "register_operand")))] + "TARGET_SSE4_2" +{ + ix86_expand_sse_movcc (operands[0], operands[3], + operands[1], operands[2]); + DONE; +}) + +(define_expand "vcond_mask_<mode><sseintvecmodelower>" + [(set (match_operand:VF_256 0 "register_operand") + (vec_merge:VF_256 + (match_operand:VF_256 1 "nonimmediate_operand") + (match_operand:VF_256 2 "vector_move_operand") + (match_operand:<sseintvecmode> 3 "register_operand")))] + "TARGET_AVX" +{ + ix86_expand_sse_movcc (operands[0], operands[3], + operands[1], operands[2]); + DONE; +}) + +(define_expand "vcond_mask_<mode><sseintvecmodelower>" + [(set (match_operand:VF_128 0 "register_operand") + (vec_merge:VF_128 + (match_operand:VF_128 1 "nonimmediate_operand") + (match_operand:VF_128 2 "vector_move_operand") + (match_operand:<sseintvecmode> 3 "register_operand")))] + "TARGET_SSE" +{ + ix86_expand_sse_movcc (operands[0], operands[3], + operands[1], operands[2]); + DONE; +}) + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Parallel floating point logical operations |