diff options
45 files changed, 102 insertions, 88 deletions
diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index f8f288d..e7e575c 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -1043,11 +1043,11 @@ get_available_features (struct __processor_model *cpu_model, set_feature (FEATURE_AVX10_2); /* Fall through. */ case 1: - set_feature (FEATURE_AVX10_1_512); + set_feature (FEATURE_AVX10_1); set_feature (FEATURE_AVX10_1_256); break; default: - set_feature (FEATURE_AVX10_1_512); + set_feature (FEATURE_AVX10_1); set_feature (FEATURE_AVX10_1_256); break; } diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index df87bb4..80aec32 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -120,10 +120,10 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_EVEX512_SET OPTION_MASK_ISA2_EVEX512 #define OPTION_MASK_ISA2_USER_MSR_SET OPTION_MASK_ISA2_USER_MSR #define OPTION_MASK_ISA2_AVX10_1_256_SET OPTION_MASK_ISA2_AVX10_1_256 -#define OPTION_MASK_ISA2_AVX10_1_512_SET \ - (OPTION_MASK_ISA2_AVX10_1_256_SET | OPTION_MASK_ISA2_AVX10_1_512) +#define OPTION_MASK_ISA2_AVX10_1_SET \ + (OPTION_MASK_ISA2_AVX10_1_256_SET | OPTION_MASK_ISA2_AVX10_1) #define OPTION_MASK_ISA2_AVX10_2_SET \ - (OPTION_MASK_ISA2_AVX10_1_512_SET | OPTION_MASK_ISA2_AVX10_2) + (OPTION_MASK_ISA2_AVX10_1_SET | OPTION_MASK_ISA2_AVX10_2) #define OPTION_MASK_ISA2_AMX_AVX512_SET \ (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AVX10_2_SET \ | OPTION_MASK_ISA2_AMX_AVX512) @@ -323,7 +323,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_EVEX512_UNSET OPTION_MASK_ISA2_EVEX512 #define OPTION_MASK_ISA2_USER_MSR_UNSET OPTION_MASK_ISA2_USER_MSR #define OPTION_MASK_ISA2_AVX10_1_UNSET \ - (OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1_512 \ + (OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1 \ | OPTION_MASK_ISA2_AVX10_2_UNSET) #define OPTION_MASK_ISA2_AVX10_2_UNSET \ (OPTION_MASK_ISA2_AVX10_2 | OPTION_MASK_ISA2_AMX_AVX512_UNSET) @@ -1378,11 +1378,11 @@ ix86_handle_option (struct gcc_options *opts, } return true; - case OPT_mavx10_1_512: + case OPT_mavx10_1: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_1_512_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_512_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_1_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_SET; opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET; } @@ -2311,10 +2311,10 @@ const pta processor_alias_table[] = {"meteorlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE, M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2}, {"graniterapids", PROCESSOR_GRANITERAPIDS, CPU_HASWELL, PTA_GRANITERAPIDS, - M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS), P_PROC_AVX10_1_512}, + M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS), P_PROC_AVX10_1}, {"graniterapids-d", PROCESSOR_GRANITERAPIDS_D, CPU_HASWELL, PTA_GRANITERAPIDS_D, M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS_D), - P_PROC_AVX10_1_512}, + P_PROC_AVX10_1}, {"arrowlake", PROCESSOR_ARROWLAKE, CPU_HASWELL, PTA_ARROWLAKE, M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE), P_PROC_AVX2}, {"arrowlake-s", PROCESSOR_ARROWLAKE_S, CPU_HASWELL, PTA_ARROWLAKE_S, @@ -2324,7 +2324,7 @@ const pta processor_alias_table[] = {"pantherlake", PROCESSOR_PANTHERLAKE, CPU_HASWELL, PTA_PANTHERLAKE, M_CPU_SUBTYPE (INTEL_COREI7_PANTHERLAKE), P_PROC_AVX2}, {"diamondrapids", PROCESSOR_DIAMONDRAPIDS, CPU_HASWELL, PTA_DIAMONDRAPIDS, - M_CPU_SUBTYPE (INTEL_COREI7_DIAMONDRAPIDS), P_PROC_AVX512F}, + M_CPU_SUBTYPE (INTEL_COREI7_DIAMONDRAPIDS), P_PROC_AVX10_1}, {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL, M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3}, {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL, diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h index 9a3d644..6b2ab0a 100644 --- a/gcc/common/config/i386/i386-cpuinfo.h +++ b/gcc/common/config/i386/i386-cpuinfo.h @@ -149,8 +149,8 @@ enum feature_priority P_PROC_AVX512F, P_X86_64_V4, P_AVX10_1_256, - P_AVX10_1_512, - P_PROC_AVX10_1_512, + P_AVX10_1, + P_PROC_AVX10_1, P_PROC_DYNAMIC }; @@ -267,7 +267,7 @@ enum processor_features FEATURE_APX_F, FEATURE_USER_MSR, FEATURE_AVX10_1_256, - FEATURE_AVX10_1_512, + FEATURE_AVX10_1, FEATURE_AVX10_2 = 116, FEATURE_AMX_AVX512, FEATURE_AMX_TF32, diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h index e6a1d36..55af985 100644 --- a/gcc/common/config/i386/i386-isas.h +++ b/gcc/common/config/i386/i386-isas.h @@ -184,7 +184,8 @@ ISA_NAMES_TABLE_START ISA_NAMES_TABLE_ENTRY("apxf", FEATURE_APX_F, P_NONE, "-mapxf") ISA_NAMES_TABLE_ENTRY("usermsr", FEATURE_USER_MSR, P_NONE, "-musermsr") ISA_NAMES_TABLE_ENTRY("avx10.1-256", FEATURE_AVX10_1_256, P_AVX10_1_256, "-mavx10.1-256") - ISA_NAMES_TABLE_ENTRY("avx10.1-512", FEATURE_AVX10_1_512, P_AVX10_1_512, "-mavx10.1-512") + ISA_NAMES_TABLE_ENTRY("avx10.1", FEATURE_AVX10_1, P_AVX10_1, "-mavx10.1") + ISA_NAMES_TABLE_ENTRY("avx10.1-512", FEATURE_AVX10_1, P_AVX10_1, "-mavx10.1-512") ISA_NAMES_TABLE_ENTRY("avx10.2", FEATURE_AVX10_2, P_NONE, "-mavx10.2") ISA_NAMES_TABLE_ENTRY("amx-avx512", FEATURE_AMX_AVX512, P_NONE, "-mamx-avx512") diff --git a/gcc/config/i386/driver-i386.cc b/gcc/config/i386/driver-i386.cc index 82bdbaf..1ff05e5 100644 --- a/gcc/config/i386/driver-i386.cc +++ b/gcc/config/i386/driver-i386.cc @@ -912,7 +912,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) /* Never push -mno-avx10.1-{256,512} under -march=native to avoid unnecessary warnings when building libraries. */ else if (isa_names_table[i].feature != FEATURE_AVX10_1_256 - && isa_names_table[i].feature != FEATURE_AVX10_1_512 + && isa_names_table[i].feature != FEATURE_AVX10_1 && check_avx512_features (cpu_model, cpu_features2, isa_names_table[i].feature)) options = concat (options, neg_option, diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc index e6daba9..0a320ca 100644 --- a/gcc/config/i386/i386-c.cc +++ b/gcc/config/i386/i386-c.cc @@ -734,12 +734,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, if (isa_flag2 & OPTION_MASK_ISA2_USER_MSR) def_or_undef (parse_in, "__USER_MSR__"); if (isa_flag2 & OPTION_MASK_ISA2_AVX10_1_256) - { - def_or_undef (parse_in, "__AVX10_1_256__"); - def_or_undef (parse_in, "__AVX10_1__"); - } - if (isa_flag2 & OPTION_MASK_ISA2_AVX10_1_512) - def_or_undef (parse_in, "__AVX10_1_512__"); + def_or_undef (parse_in, "__AVX10_1_256__"); + if (isa_flag2 & OPTION_MASK_ISA2_AVX10_1) + def_or_undef (parse_in, "__AVX10_1__"); if (isa_flag2 & OPTION_MASK_ISA2_APX_F) def_or_undef (parse_in, "__APX_F__"); if (ix86_apx_inline_asm_use_gpr32) diff --git a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def index 13cb49a..19d78d7 100644 --- a/gcc/config/i386/i386-isa.def +++ b/gcc/config/i386/i386-isa.def @@ -120,7 +120,7 @@ DEF_PTA(APX_F) DEF_PTA(USER_MSR) DEF_PTA(EVEX512) DEF_PTA(AVX10_1_256) -DEF_PTA(AVX10_1_512) +DEF_PTA(AVX10_1) DEF_PTA(AVX10_2) DEF_PTA(AMX_AVX512) DEF_PTA(AMX_TF32) diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index a48a939..91f59e1 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -262,7 +262,7 @@ static struct ix86_target_opts isa2_opts[] = { "-mevex512", OPTION_MASK_ISA2_EVEX512 }, { "-musermsr", OPTION_MASK_ISA2_USER_MSR }, { "-mavx10.1-256", OPTION_MASK_ISA2_AVX10_1_256 }, - { "-mavx10.1-512", OPTION_MASK_ISA2_AVX10_1_512 }, + { "-mavx10.1", OPTION_MASK_ISA2_AVX10_1 }, { "-mavx10.2", OPTION_MASK_ISA2_AVX10_2 }, { "-mamx-avx512", OPTION_MASK_ISA2_AMX_AVX512 }, { "-mamx-tf32", OPTION_MASK_ISA2_AMX_TF32 }, @@ -1134,7 +1134,8 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[], IX86_ATTR_ISA ("evex512", OPT_mevex512), IX86_ATTR_ISA ("usermsr", OPT_musermsr), IX86_ATTR_ISA ("avx10.1-256", OPT_mavx10_1_256), - IX86_ATTR_ISA ("avx10.1-512", OPT_mavx10_1_512), + IX86_ATTR_ISA ("avx10.1", OPT_mavx10_1), + IX86_ATTR_ISA ("avx10.1-512", OPT_mavx10_1), IX86_ATTR_ISA ("avx10.2", OPT_mavx10_2), IX86_ATTR_ISA ("amx-avx512", OPT_mamx_avx512), IX86_ATTR_ISA ("amx-tf32", OPT_mamx_tf32), @@ -2673,7 +2674,7 @@ ix86_option_override_internal (bool main_args_p, 2. Both AVX10.1-256 and AVX512 w/o 512 bit vector width are enabled with no explicit disable on other AVX512 features. 3. Both AVX10.1 and AVX512 are disabled. */ - if (TARGET_AVX10_1_512_P (opts->x_ix86_isa_flags2)) + if (TARGET_AVX10_1_P (opts->x_ix86_isa_flags2)) { if (opts->x_ix86_no_avx512_explicit && (((~(avx512_isa_flags & opts->x_ix86_isa_flags) @@ -2683,7 +2684,9 @@ ix86_option_override_internal (bool main_args_p, & ((avx512_isa_flags2 | OPTION_MASK_ISA2_EVEX512) & opts->x_ix86_isa_flags2_explicit))))) warning (0, "%<-mno-evex512%> or %<-mno-avx512XXX%> cannot disable " - "AVX10 instructions when AVX10.1-512 is available"); + "AVX10 instructions when AVX10.1-512 is available in GCC 15, " + "behavior will change to it will disable that part of " + "AVX512 instructions since GCC 16"); } else if (TARGET_AVX10_1_256_P (opts->x_ix86_isa_flags2)) { @@ -2719,18 +2722,21 @@ ix86_option_override_internal (bool main_args_p, & (avx512_isa_flags2 & opts->x_ix86_isa_flags2_explicit))))) warning (0, "%<-mno-avx512XXX%> cannot disable AVX10 instructions " - "when AVX10 is available"); + "when AVX10 is available in GCC 15, behavior will change " + "to it will disable that part of AVX512 instructions since " + "GCC 16"); } else if (TARGET_AVX512F_P (opts->x_ix86_isa_flags) && (OPTION_MASK_ISA_AVX512F & opts->x_ix86_isa_flags_explicit)) { if (opts->x_ix86_no_avx10_1_explicit - && ((OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1_512) + && ((OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1) & opts->x_ix86_isa_flags2_explicit)) { - warning (0, "%<-mno-avx10.1-256, -mno-avx10.1-512%> " - "cannot disable AVX512 instructions when " - "%<-mavx512XXX%>"); + warning (0, "%<-mno-avx10.1-256, -mno-avx10.1-512%> cannot disable " + "AVX512 instructions when %<-mavx512XXX%> in GCC 15, " + "behavior will change to it will disable all the " + "instructions in GCC 16"); /* Reset those unset AVX512 flags set by AVX10 options when AVX10 is disabled. */ if (OPTION_MASK_ISA2_AVX10_1_256 & opts->x_ix86_isa_flags2_explicit) @@ -2750,7 +2756,7 @@ ix86_option_override_internal (bool main_args_p, /* Set EVEX512 if one of the following conditions meets: 1. AVX512 is enabled while EVEX512 is not explicitly set/unset. 2. AVX10.1-512 is enabled. */ - if (TARGET_AVX10_1_512_P (opts->x_ix86_isa_flags2) + if (TARGET_AVX10_1_P (opts->x_ix86_isa_flags2) || (TARGET_AVX512F_P (opts->x_ix86_isa_flags) && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512))) opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_EVEX512; diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index c797ac1..13da3d8 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -2449,7 +2449,7 @@ constexpr wide_int_bitmask PTA_DIAMONDRAPIDS = PTA_SKYLAKE | PTA_PKU | PTA_SHA | PTA_WBNOINVD | PTA_CLWB | PTA_MOVDIRI | PTA_MOVDIR64B | PTA_ENQCMD | PTA_CLDEMOTE | PTA_PTWRITE | PTA_WAITPKG | PTA_SERIALIZE | PTA_TSXLDTRK | PTA_AMX_TILE | PTA_AMX_INT8 | PTA_AMX_BF16 | PTA_UINTR | PTA_AVXVNNI - | PTA_AMX_FP16 | PTA_PREFETCHI | PTA_AMX_COMPLEX | PTA_AVX10_1_512 + | PTA_AMX_FP16 | PTA_PREFETCHI | PTA_AMX_COMPLEX | PTA_AVX10_1 | PTA_AVXIFMA | PTA_AVXNECONVERT | PTA_AVXVNNIINT16 | PTA_AVXVNNIINT8 | PTA_CMPCCXADD | PTA_SHA512 | PTA_SM3 | PTA_SM4 | PTA_AVX10_2 | PTA_APX_F | PTA_AMX_AVX512 | PTA_AMX_FP8 | PTA_AMX_TF32 | PTA_AMX_TRANSPOSE diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index ff864b6..27d34bd 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -1356,7 +1356,7 @@ Target Var(ix86_apx_inline_asm_use_gpr32) Init(0) Enable GPR32 in inline asm when APX_F enabled. mevex512 -Target Mask(ISA2_EVEX512) Var(ix86_isa_flags2) Save +Target Mask(ISA2_EVEX512) Var(ix86_isa_flags2) Save Warn(%<-mevex512%> will be deprecated in GCC 16 due to all machines 512 bit vector size supported) Support 512 bit vector built-in functions and code generation. musermsr @@ -1364,12 +1364,17 @@ Target Mask(ISA2_USER_MSR) Var(ix86_isa_flags2) Save Support USER_MSR built-in functions and code generation. mavx10.1-256 -Target Mask(ISA2_AVX10_1_256) Var(ix86_isa_flags2) Save +Target Mask(ISA2_AVX10_1_256) Var(ix86_isa_flags2) Save Warn(%<-mavx10.1%> is aliased to 512 bit since GCC14.3 and GCC15.1 while %<-mavx10.1-256%> and %<-mavx10.1-512%> will be deprecated in GCC 16 due to all machines 512 bit vector size supported) Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, and AVX10.1-256 built-in functions and code generation. +mavx10.1 +Target Mask(ISA2_AVX10_1) Var(ix86_isa_flags2) Save Warn(%<-mavx10.1%> is aliased to 512 bit since GCC14.3 and GCC15.1 while %<-mavx10.1-256%> and %<-mavx10.1-512%> will be deprecated in GCC 16 due to all machines 512 bit vector size supported) +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, +and AVX10.1-512 built-in functions and code generation. + mavx10.1-512 -Target Mask(ISA2_AVX10_1_512) Var(ix86_isa_flags2) Save +Target Alias(mavx10.1) Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, and AVX10.1-512 built-in functions and code generation. diff --git a/gcc/config/i386/i386.opt.urls b/gcc/config/i386/i386.opt.urls index abfb973..0d5a5a1 100644 --- a/gcc/config/i386/i386.opt.urls +++ b/gcc/config/i386/i386.opt.urls @@ -599,6 +599,9 @@ UrlSuffix(gcc/x86-Options.html#index-musermsr) mavx10.1-256 UrlSuffix(gcc/x86-Options.html#index-mavx10_002e1-256) +mavx10.1 +UrlSuffix(gcc/x86-Options.html#index-mavx10_002e1) + mavx10.1-512 UrlSuffix(gcc/x86-Options.html#index-mavx10_002e1-512) diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 522d51a..ed766e5 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -6639,6 +6639,12 @@ EGPR, PUSH2POP2, NDD and PPX. Enable the generation of the AVX10.1 instructions with 256 bit support. Disable the generation of the AVX10.1 instructions. +@cindex @code{target("avx10.1")} function attribute, x86 +@item avx10.1 +@itemx no-avx10.1 +Enable the generation of the AVX10.1 instructions with 512 bit support. +Disable the generation of the AVX10.1 instructions. + @cindex @code{target("avx10.1-512")} function attribute, x86 @item avx10.1-512 @itemx no-avx10.1-512 diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index f0912cf..c29cd3f 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2626,6 +2626,9 @@ Target supports the execution of @code{avx} instructions. @item avx10.1-256 Target supports the execution of @code{avx10.1-256} instructions. +@item avx10.1 +Target supports the execution of @code{avx10.1} instructions. + @item avx10.1-512 Target supports the execution of @code{avx10.1-512} instructions. diff --git a/gcc/testsuite/gcc.target/i386/avx10-check.h b/gcc/testsuite/gcc.target/i386/avx10-check.h index 18e0e78..7d4326d 100644 --- a/gcc/testsuite/gcc.target/i386/avx10-check.h +++ b/gcc/testsuite/gcc.target/i386/avx10-check.h @@ -38,7 +38,7 @@ int main () { /* Run AVX10 test only if host has ISA support. */ - if (__builtin_cpu_supports ("avx10.1-256") + if (__builtin_cpu_supports ("avx10.1") #ifdef AVX10_2 && __builtin_cpu_supports ("avx10.2") #endif diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-1.c b/gcc/testsuite/gcc.target/i386/avx10_1-1.c index 33ce99e..bd3249e 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-1.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-1.c @@ -1,5 +1,6 @@ /* { dg-do compile { target { ! ia32 } } } */ -/* { dg-options "-O2 -march=x86-64 -mavx10.1-256" } */ +/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */ +/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ #include <immintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-10.c b/gcc/testsuite/gcc.target/i386/avx10_1-10.c index 0db5240..dba2a4e 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-10.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-10.c @@ -1,6 +1,8 @@ /* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx10.1-512 -mavx512f -mno-evex512" } */ +/* { dg-options "-march=x86-64 -mavx10.1 -mavx512f -mno-evex512" } */ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" "" { target *-*-* } 0 } */ +/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ +/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ /* { dg-final { scan-assembler "%zmm" } } */ #include "avx10_1-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-11.c b/gcc/testsuite/gcc.target/i386/avx10_1-11.c index c0ad4fc..608817a 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-11.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-11.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx10.1-512 -mno-avx512f" } */ +/* { dg-options "-march=x86-64 -mavx10.1 -mno-avx512f" } */ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" "" { target *-*-* } 0 } */ +/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ /* { dg-final { scan-assembler "%zmm" } } */ #include "avx10_1-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-12.c b/gcc/testsuite/gcc.target/i386/avx10_1-12.c index ae1c77b..1650f26 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-12.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-12.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=x86-64 -mno-avx10.1-512 -mavx512f" } */ /* { dg-warning "'-mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" "" { target *-*-* } 0 } */ +/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ /* { dg-final { scan-assembler "%zmm" } } */ #include "avx10_1-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-13.c b/gcc/testsuite/gcc.target/i386/avx10_1-13.c index e94ac8e..a864e96 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-13.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-13.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-march=x86-64 -mavx10.1-256" } */ +/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ /* { dg-final { scan-assembler "%zmm" } } */ typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-15.c b/gcc/testsuite/gcc.target/i386/avx10_1-15.c index d1731f0..b227cf3 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-15.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-15.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx10.1-512" } */ +/* { dg-options "-march=x86-64 -mavx10.1" } */ +/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ /* { dg-final { scan-assembler "%zmm" } } */ typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-16.c b/gcc/testsuite/gcc.target/i386/avx10_1-16.c index f5f3ff8..b3fdb3f 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-16.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-16.c @@ -1,10 +1,11 @@ /* { dg-do compile } */ /* { dg-options "-march=x86-64 -mavx512f -mno-evex512" } */ +/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ /* { dg-final { scan-assembler "%zmm" } } */ typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); -__attribute__ ((target ("avx10.1-512"))) __m512d +__attribute__ ((target ("avx10.1"))) __m512d foo () { /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" } */ __m512d a, b; diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-18.c b/gcc/testsuite/gcc.target/i386/avx10_1-18.c index c50fd2b..c1edce8 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-18.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-18.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx10.1-512" } */ +/* { dg-options "-march=x86-64 -mavx10.1" } */ +/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ /* { dg-final { scan-assembler "%zmm" } } */ typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-19.c b/gcc/testsuite/gcc.target/i386/avx10_1-19.c index 7445ecf..25b5887 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-19.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-19.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-march=x86-64 -mno-avx10.1-512" } */ +/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ /* { dg-final { scan-assembler "%zmm" } } */ typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-2.c b/gcc/testsuite/gcc.target/i386/avx10_1-2.c index 0b3991d..19962bc 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-2.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx10.1-512" } */ +/* { dg-options "-march=x86-64 -mavx10.1" } */ +/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ /* { dg-final { scan-assembler "%zmm" } } */ typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-20.c b/gcc/testsuite/gcc.target/i386/avx10_1-20.c index d63c6b4..a223065 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-20.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-20.c @@ -4,7 +4,7 @@ typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); -__attribute__ ((target ("avx10.1-512"))) __m512d +__attribute__ ((target ("avx10.1"))) __m512d foo () { /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" } */ __m512d a, b; diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-21.c b/gcc/testsuite/gcc.target/i386/avx10_1-21.c index 0a1fcc9..2ae437e 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-21.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-21.c @@ -1,6 +1,8 @@ /* { dg-do compile } */ /* { dg-options "-march=x86-64 -mavx10.1-256 -mevex512 -Wno-psabi" } */ /* { dg-warning "Using '-mevex512' without any AVX512 features enabled together with AVX10.1 only will not enable any AVX512 or AVX10.1-512 features, using 256 as max vector size" "" { target *-*-* } 0 } */ +/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ +/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ /* { dg-final { scan-assembler-not "%zmm" } } */ #include "avx10_1-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-22.c b/gcc/testsuite/gcc.target/i386/avx10_1-22.c index cb649dc..df7bffb 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-22.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-22.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-march=x86-64 -mavx10.1-256 -Wno-psabi" } */ +/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ /* { dg-final { scan-assembler-not "%zmm" } } */ typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-23.c b/gcc/testsuite/gcc.target/i386/avx10_1-23.c index f31c636..1f84584 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-23.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-23.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-march=x86-64 -mevex512 -Wno-psabi" } */ +/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ /* { dg-final { scan-assembler-not "%zmm" } } */ typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-24.c b/gcc/testsuite/gcc.target/i386/avx10_1-24.c deleted file mode 100644 index 1bba0fb..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-24.c +++ /dev/null @@ -1,7 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64 -mavx10.1-256" } */ -/* { dg-final { scan-assembler-not "%zmm" } } */ - -typedef float __m512 __attribute__ ((__vector_size__ (64), __may_alias__)); - -void __attribute__((target("avx10.1-256"))) callee256(__m512 *a, __m512 *b) { *a = *b; } diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-25.c b/gcc/testsuite/gcc.target/i386/avx10_1-25.c deleted file mode 100644 index fb378b9..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-25.c +++ /dev/null @@ -1,10 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64-v2 -mavx" } */ -/* { dg-require-ifunc "" } */ - -#include <immintrin.h> -__attribute__((target_clones ("default","avx10.1-256"))) -__m256d foo(__m256d a, __m256d b) -{ - return a + b; -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-26.c b/gcc/testsuite/gcc.target/i386/avx10_1-26.c index e54e2f5..d887404 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-26.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-26.c @@ -3,7 +3,7 @@ /* { dg-require-ifunc "" } */ #include <immintrin.h> -__attribute__((target_clones ("default","avx10.1-512"))) +__attribute__((target_clones ("default","avx10.1"))) __m512d foo(__m512d a, __m512d b) { return a + b; diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-3.c b/gcc/testsuite/gcc.target/i386/avx10_1-3.c index a176f27..992364a 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-3.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-3.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64 -mavx10.1-256" } */ +/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */ +/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ #include <immintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-4.c b/gcc/testsuite/gcc.target/i386/avx10_1-4.c index 68cbf19..b3d2603 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-4.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-4.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64 -mavx10.1-512" } */ +/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */ +/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ #include <immintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-5.c b/gcc/testsuite/gcc.target/i386/avx10_1-5.c deleted file mode 100644 index 3079cf1..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-5.c +++ /dev/null @@ -1,5 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O0 -march=x86-64 -mavx10.1-256 -Wno-psabi" } */ -/* { dg-final { scan-assembler-not ".%zmm" } } */ - -#include "avx10_1-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-6.c b/gcc/testsuite/gcc.target/i386/avx10_1-6.c deleted file mode 100644 index 60dbd05..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-6.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64 -mavx10.1-256" } */ - -#include <immintrin.h> - -long long -foo (long long c) -{ - register long long a __asm ("k7") = c; - long long b = foo (a); - asm volatile ("" : "+k" (b)); - return b; -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-7.c b/gcc/testsuite/gcc.target/i386/avx10_1-7.c index afce290..fb74ffb 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-7.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-7.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx10.1-512 -mavx512f" } */ +/* { dg-options "-march=x86-64 -mavx10.1 -mavx512f" } */ +/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ /* { dg-final { scan-assembler "%zmm" } } */ #include "avx10_1-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-8.c b/gcc/testsuite/gcc.target/i386/avx10_1-8.c index ec930f7..dbb7d64 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-8.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-8.c @@ -1,4 +1,6 @@ /* { dg-do compile { target { ! ia32 } } } */ /* { dg-options "-march=x86-64 -mavx10.1-256 -mavx512f -mno-evex512" } */ +/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ +/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ #include "avx10_1-1.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-9.c b/gcc/testsuite/gcc.target/i386/avx10_1-9.c index 8e83827..b951738 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-9.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-9.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=x86-64 -mavx10.1-256 -mavx512f" } */ /* { dg-warning "Vector size conflicts between AVX10.1 and AVX512, using 512 as max vector size" "" { target *-*-* } 0 } */ +/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ /* { dg-final { scan-assembler "%zmm" } } */ #include "avx10_1-2.c" diff --git a/gcc/testsuite/gcc.target/i386/noevex512-1.c b/gcc/testsuite/gcc.target/i386/noevex512-1.c index 7fd45f1..89eb528 100644 --- a/gcc/testsuite/gcc.target/i386/noevex512-1.c +++ b/gcc/testsuite/gcc.target/i386/noevex512-1.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O0 -march=x86-64 -mavx512f -mno-evex512 -Wno-psabi" } */ +/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ /* { dg-final { scan-assembler-not ".%zmm" } } */ typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); diff --git a/gcc/testsuite/gcc.target/i386/noevex512-2.c b/gcc/testsuite/gcc.target/i386/noevex512-2.c index b7915d8..34740ff 100644 --- a/gcc/testsuite/gcc.target/i386/noevex512-2.c +++ b/gcc/testsuite/gcc.target/i386/noevex512-2.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -march=x86-64 -mavx512bw -mno-evex512" } */ +/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ #include <immintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/pr111068.c b/gcc/testsuite/gcc.target/i386/pr111068.c index 4ff2ea0..70c1e9a 100644 --- a/gcc/testsuite/gcc.target/i386/pr111068.c +++ b/gcc/testsuite/gcc.target/i386/pr111068.c @@ -1,6 +1,7 @@ /* PR target/111068 */ /* { dg-do compile } */ -/* { dg-options "-ffloat-store -mavx10.1-512" } */ +/* { dg-options "-ffloat-store -mavx10.1" } */ +/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ typedef _Float16 __attribute__((__vector_size__ (8))) V; V u, v, w; diff --git a/gcc/testsuite/gcc.target/i386/pr111907.c b/gcc/testsuite/gcc.target/i386/pr111907.c index 5275e94..cadc9e4 100644 --- a/gcc/testsuite/gcc.target/i386/pr111907.c +++ b/gcc/testsuite/gcc.target/i386/pr111907.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-mavx512f -mno-evex512" } */ +/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ _Float128 foo (_Float128 d, _Float128 e) diff --git a/gcc/testsuite/gcc.target/i386/pr117240_avx512f.c b/gcc/testsuite/gcc.target/i386/pr117240_avx512f.c index c2d616a..d34ebb7 100644 --- a/gcc/testsuite/gcc.target/i386/pr117240_avx512f.c +++ b/gcc/testsuite/gcc.target/i386/pr117240_avx512f.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -mvaes -mevex512 -mno-xsave -Wno-psabi" } */ +/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ typedef __attribute__((__vector_size__(64))) char V; diff --git a/gcc/testsuite/gcc.target/i386/pr117304-1.c b/gcc/testsuite/gcc.target/i386/pr117304-1.c index ec75f27..58fb53c 100644 --- a/gcc/testsuite/gcc.target/i386/pr117304-1.c +++ b/gcc/testsuite/gcc.target/i386/pr117304-1.c @@ -1,6 +1,7 @@ /* PR target/117304 */ /* { dg-do compile } */ /* { dg-options "-O2 -mavx512f -mno-evex512" } */ +/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ typedef __attribute__((__vector_size__(32))) int __v8si; typedef __attribute__((__vector_size__(32))) unsigned int __v8su; diff --git a/gcc/testsuite/gcc.target/i386/pr117946.c b/gcc/testsuite/gcc.target/i386/pr117946.c index e7b660b..c4bf825 100644 --- a/gcc/testsuite/gcc.target/i386/pr117946.c +++ b/gcc/testsuite/gcc.target/i386/pr117946.c @@ -1,5 +1,6 @@ /* { dg-do compile { target { ! ia32 } } } */ -/* { dg-options "-O -favoid-store-forwarding -mavx10.1-256 -mprefer-avx128 --param=store-forwarding-max-distance=128 -Wno-psabi" } */ +/* { dg-options "-O -favoid-store-forwarding -mavx10.1 -mprefer-avx128 --param=store-forwarding-max-distance=128 -Wno-psabi" } */ +/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ typedef __attribute__((__vector_size__ (64))) _Decimal32 V; void |