diff options
29 files changed, 46 insertions, 34 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d811f92..e524ace 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,17 @@ 2001-10-28 Joseph S. Myers <jsm28@cam.ac.uk> + * config/alpha/alpha.md, config/arm/arm.c, config/arm/arm.h, + config/d30v/d30v.h, config/fr30/fr30.c, config/i370/x-oe, + config/i386/i386.c, config/i386/i386-interix.h, + config/i386/i386.md, config/i386/i386.h, config/i386/sco5.h, + config/i860/i860.h, config/i860/i860.md, config/m68k/aux-exit.c, + config/m68k/m68k.c, config/mcore/mcore.c, config/mips/mips.md, + config/ns32k/ns32k.h, config/pa/pa.c, config/rs6000/rs6000.c, + config/sparc/sparc.c, config/m68hc11/m68hc11.c, + config/cris/cris.c, config/cris/cris.h, config/s390/s390.c, + config/s390/s390.h, config/stormy16/stormy16.h, doc/tm.texi: Fix + spelling errors. + * ChangeLog.0, ChangeLog.1, ChangeLog.2, ChangeLog.3, ChangeLog.4, ChangeLog.5, ChangeLog, ChangeLog.lib, FSFChangeLog.10, ONEWS, c-common.c, caller-save.c, cfg.c, cfgcleanup.c, cfgrtl.c, diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 0dfece8..25eb09e 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -297,7 +297,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" ;; EV6 has two symmetric pairs ("clusters") of two asymetric integer units ;; ("upper" and "lower"), yielding pipe names U0, U1, L0, L1. -;; Conditional moves decompose into two independant primitives, each +;; Conditional moves decompose into two independent primitives, each ;; taking one cycle. Since ev6 is out-of-order, we can't see anything ;; but two cycles. (define_function_unit "ev6_ebox" 4 0 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 0c505bc..b3f8af2 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -3057,7 +3057,7 @@ arm_reload_memory_operand (op, mode) /* Return 1 if OP is a valid memory address, but not valid for a signed byte memory access (architecture V4). - MODE is QImode if called when computing contraints, or VOIDmode when + MODE is QImode if called when computing constraints, or VOIDmode when emitting patterns. In this latter case we cannot use memory_operand() because it will fail on badly formed MEMs, which is precisly what we are trying to catch. */ diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 4c076ff..4c3bbd1 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -731,7 +731,7 @@ extern int arm_is_6_or_7; /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the value set in previous versions of this toolchain was 8, which produces more compact structures. The command line option -mstructure_size_boundary=<n> - can be used to change this value. For compatability with the ARM SDK + can be used to change this value. For compatibility with the ARM SDK however the value should be left at 32. ARM SDT Reference Manual (ARM DUI 0020D) page 2-20 says "Structures are aligned on word boundaries". */ #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary diff --git a/gcc/config/cris/cris.c b/gcc/config/cris/cris.c index 668811e..3be8870a 100644 --- a/gcc/config/cris/cris.c +++ b/gcc/config/cris/cris.c @@ -1608,7 +1608,7 @@ cris_initial_frame_pointer_offset () { int regno; - /* Initial offset is 0 if we dont have a frame pointer. */ + /* Initial offset is 0 if we don't have a frame pointer. */ int offs = 0; /* And 4 for each register pushed. */ diff --git a/gcc/config/cris/cris.h b/gcc/config/cris/cris.h index 081af38..383a46f 100644 --- a/gcc/config/cris/cris.h +++ b/gcc/config/cris/cris.h @@ -608,7 +608,7 @@ extern int target_flags; /* Node: Allocation Order */ /* We need this on CRIS, because call-used regs should be used first, - (so we dont need to push). Else start using registers from r0 and up. + (so we don't need to push). Else start using registers from r0 and up. This preference is mainly because if we put call-used-regs from r0 and up, then we can't use movem to push the rest, (which have to be saved if we use them, and movem has to start with r0). diff --git a/gcc/config/d30v/d30v.h b/gcc/config/d30v/d30v.h index f7e743e..46e89cd 100644 --- a/gcc/config/d30v/d30v.h +++ b/gcc/config/d30v/d30v.h @@ -5100,7 +5100,7 @@ fprintf (STREAM, "\t.word .L%d\n", VALUE) /* Some stabs encapsulation formats (in particular ECOFF), cannot handle the `.stabs "",N_FUN,,0,0,Lscope-function-1' gdb dbx - extention construct. On those machines, define this macro to turn + extension construct. On those machines, define this macro to turn this feature off without disturbing the rest of the gdb extensions. */ /* #define NO_DBX_FUNCTION_END */ diff --git a/gcc/config/fr30/fr30.c b/gcc/config/fr30/fr30.c index 3adcb09..5fca233 100644 --- a/gcc/config/fr30/fr30.c +++ b/gcc/config/fr30/fr30.c @@ -1085,7 +1085,7 @@ fr30_move_double (operands) } } else - /* This should have been prevented by the contraints on movdi_insn. */ + /* This should have been prevented by the constraints on movdi_insn. */ abort (); val = gen_sequence (); diff --git a/gcc/config/i370/x-oe b/gcc/config/i370/x-oe index 8007ba8..045778b 100644 --- a/gcc/config/i370/x-oe +++ b/gcc/config/i370/x-oe @@ -2,5 +2,5 @@ # Host is an i370 running OpenEdition # -# Don't bother fixing up header files, they're wierd +# Don't bother fixing up header files, they're weird STMP_FIXPROTO = diff --git a/gcc/config/i386/i386-interix.h b/gcc/config/i386/i386-interix.h index 3da0807..0325b68 100644 --- a/gcc/config/i386/i386-interix.h +++ b/gcc/config/i386/i386-interix.h @@ -39,7 +39,7 @@ Boston, MA 02111-1307, USA. */ /* By default, target has a 80387, uses IEEE compatible arithmetic, and returns float values in the 387 and needs stack probes - We also align doubles to 64-bits for MSVC default compatability */ + We also align doubles to 64-bits for MSVC default compatibility */ #undef TARGET_SUBTARGET_DEFAULT #define TARGET_SUBTARGET_DEFAULT \ (MASK_80387 | MASK_IEEE_FP | MASK_FLOAT_RETURNS | MASK_STACK_PROBE | \ diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 52e2414..79aceb6 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -1418,7 +1418,7 @@ init_cumulative_args (cum, fntype, libname) } /* x86-64 register passing impleemntation. See x86-64 ABI for details. Goal - of this code is to classify each 8bytes of incomming argument by the register + of this code is to classify each 8bytes of incoming argument by the register class and assign registers accordingly. */ /* Return the union class of CLASS1 and CLASS2. @@ -3801,7 +3801,7 @@ ix86_compute_frame_layout (frame) /* Do some sanity checking of stack_alignment_needed and preferred_alignment, since i386 port is the only using those features - that may break easilly. */ + that may break easily. */ if (size && !stack_alignment_needed) abort (); @@ -4696,7 +4696,7 @@ legitimate_address_p (mode, addr, strict) This code is nonsensical, but results in addressing GOT table with pic_offset_table_rtx base. We can't - just refuse it easilly, since it gets matched by + just refuse it easily, since it gets matched by "addsi3" pattern, that later gets split to lea in the case output register differs from input. While this can be handled by separate addsi pattern for this case @@ -12133,7 +12133,7 @@ ix86_expand_builtin (exp, target, subtarget, mode, ignore) } /* Store OPERAND to the memory after reload is completed. This means - that we can't easilly use assign_stack_local. */ + that we can't easily use assign_stack_local. */ rtx ix86_force_to_memory (mode, operand) enum machine_mode mode; diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index f3e855c..85e1c35 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -2394,7 +2394,7 @@ while (0) stored in a register. This macro is only called when TYPE is a scalar type. - On i386 it is sometimes usefull to promote HImode and QImode + On i386 it is sometimes useful to promote HImode and QImode quantities to SImode. The choice depends on target type. */ #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index a8a01b4..7c12269 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -993,7 +993,7 @@ (eq_attr "athlon_fpunits" "store")) 1 1) -;; We don't need to model the Adress Generation Unit, since we don't model +;; We don't need to model the Address Generation Unit, since we don't model ;; the re-order buffer yet and thus we never schedule more than three operations ;; at time. Later we may want to experiment with MD_SCHED macros modeling the ;; decoders independently on the functional units. diff --git a/gcc/config/i386/sco5.h b/gcc/config/i386/sco5.h index ca7d6c8..cdc811b 100644 --- a/gcc/config/i386/sco5.h +++ b/gcc/config/i386/sco5.h @@ -102,7 +102,7 @@ Boston, MA 02111-1307, USA. */ #undef INIT_SECTION_ASM_OP #define INIT_SECTION_ASM_OP_ELF "\t.section\t.init" -/* Rename these for COFF becuase crt1.o will try to run them. */ +/* Rename these for COFF because crt1.o will try to run them. */ #define INIT_SECTION_ASM_OP_COFF "\t.section\t.ctor ,\"x\"" #define INIT_SECTION_ASM_OP \ ((TARGET_ELF) ? INIT_SECTION_ASM_OP_ELF : INIT_SECTION_ASM_OP_COFF) @@ -658,7 +658,7 @@ init_section () \ #if USE_GAS /* Leave ASM_SPEC undefined so we pick up the master copy from gcc.c - * Undef MD_EXEC_PREFIX becuase we don't know where GAS is, but it's not + * Undef MD_EXEC_PREFIX because we don't know where GAS is, but it's not * likely in /usr/ccs/bin/ */ #undef MD_EXEC_PREFIX diff --git a/gcc/config/i860/i860.h b/gcc/config/i860/i860.h index 60485f8..a176f23 100644 --- a/gcc/config/i860/i860.h +++ b/gcc/config/i860/i860.h @@ -126,7 +126,7 @@ extern int target_flags; when given unaligned data. */ #define STRICT_ALIGNMENT 1 -/* If bit field type is int, dont let it cross an int, +/* If bit field type is int, don't let it cross an int, and give entire struct the alignment of an int. */ #define PCC_BITFIELD_TYPE_MATTERS 1 diff --git a/gcc/config/i860/i860.md b/gcc/config/i860/i860.md index eda051c..b866c91 100644 --- a/gcc/config/i860/i860.md +++ b/gcc/config/i860/i860.md @@ -1617,7 +1617,7 @@ ;; Recognize the first insn generated above. ;; This RTL looks like a fix_truncdfdi2 insn, -;; but we dont call it that, because only 32 bits +;; but we don't call it that, because only 32 bits ;; of the result are valid. ;; This pattern will work for the intended purposes ;; as long as we do not have any fixdfdi2 or fix_truncdfdi2. @@ -1642,7 +1642,7 @@ ;; Recognize the first insn generated above. ;; This RTL looks like a fix_truncsfdi2 insn, -;; but we dont call it that, because only 32 bits +;; but we don't call it that, because only 32 bits ;; of the result are valid. ;; This pattern will work for the intended purposes ;; as long as we do not have any fixsfdi2 or fix_truncsfdi2. diff --git a/gcc/config/m68hc11/m68hc11.c b/gcc/config/m68hc11/m68hc11.c index fa0179a..247ce86 100644 --- a/gcc/config/m68hc11/m68hc11.c +++ b/gcc/config/m68hc11/m68hc11.c @@ -5060,7 +5060,7 @@ m68hc11_shift_cost (mode, x, shift) total *= GET_MODE_SIZE (mode) / 2; /* When optimizing for size, make shift more costly so that - multiplications are prefered. */ + multiplications are preferred. */ if (optimize_size && (shift % 8) != 0) total *= 2; diff --git a/gcc/config/m68k/aux-exit.c b/gcc/config/m68k/aux-exit.c index 47a5809..1d7d6c0 100644 --- a/gcc/config/m68k/aux-exit.c +++ b/gcc/config/m68k/aux-exit.c @@ -47,7 +47,7 @@ struct atexit_fn_block }; -/* staticly allocate the first block */ +/* statically allocate the first block */ static struct atexit_fn_block atexit_fns; static struct atexit_fn_block *current_block = &atexit_fns; diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c index a83168a..0bb1e85 100644 --- a/gcc/config/m68k/m68k.c +++ b/gcc/config/m68k/m68k.c @@ -1664,7 +1664,7 @@ output_scc_di(op, operand1, operand2, dest) rtx loperands[7]; enum rtx_code op_code = GET_CODE (op); - /* This does not produce a usefull cc. */ + /* This does not produce a useful cc. */ CC_STATUS_INIT; /* The m68k cmp.l instruction requires operand1 to be a reg as used diff --git a/gcc/config/mcore/mcore.c b/gcc/config/mcore/mcore.c index 412e7c4..5560030 100644 --- a/gcc/config/mcore/mcore.c +++ b/gcc/config/mcore/mcore.c @@ -3520,7 +3520,7 @@ mcore_unique_section (decl, reloc) (everything from the $ on is stripped). */ if (TREE_CODE (decl) == FUNCTION_DECL) prefix = ".text$"; - /* For compatability with EPOC, we ignore the fact that the + /* For compatibility with EPOC, we ignore the fact that the section might have relocs against it. */ else if (DECL_READONLY_SECTION (decl, 0)) prefix = ".rdata$"; diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index d22e157..36e83e1 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -4230,10 +4230,10 @@ move\\t%0,%z4\\n\\ ;; operand zero, because then the address in the move instruction will be ;; clobbered. We mark the scratch register as early clobbered to prevent this. -;; We need the ?X in alternative 1 so that it will be choosen only if the +;; We need the ?X in alternative 1 so that it will be chosen only if the ;; destination is a floating point register. Otherwise, alternative 1 can ;; have lower cost than alternative 0 (because there is one less loser), and -;; can be choosen when it won't work (because integral reloads into FP +;; can be chosen when it won't work (because integral reloads into FP ;; registers are not supported). (define_insn "fix_truncdfsi2" diff --git a/gcc/config/ns32k/ns32k.h b/gcc/config/ns32k/ns32k.h index 0037920..373f78f 100644 --- a/gcc/config/ns32k/ns32k.h +++ b/gcc/config/ns32k/ns32k.h @@ -236,7 +236,7 @@ while (0) crossing a page boundary cause unpredictable results. */ #define STRICT_ALIGNMENT 1 -/* If bit field type is int, dont let it cross an int, +/* If bit field type is int, don't let it cross an int, and give entire struct the alignment of an int. */ /* Required on the 386 since it doesn't have a full set of bitfield insns. (There is no signed extv insn.) */ diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c index 593f085..1449fca 100644 --- a/gcc/config/pa/pa.c +++ b/gcc/config/pa/pa.c @@ -4855,7 +4855,7 @@ hppa_builtin_saveregs () gen_rtx_REG (word_mode, i)); /* The incoming args pointer points just beyond the flushback area; - normally this is not a serious concern. Howver, when we are doing + normally this is not a serious concern. However, when we are doing varargs/stdargs we want to make the arg pointer point to the start of the incoming argument area. */ emit_move_insn (virtual_incoming_args_rtx, diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 6e6f428..803d4e0 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -6926,7 +6926,7 @@ rs6000_output_function_epilogue (file, size) is 0. C++ is 9. No number defined for Obj-C, so use the value for C for now. There is no official value for Java, although IBM appears to be using 13. There is no official value - for Chill, so we've choosen 44 pseudo-randomly. */ + for Chill, so we've chosen 44 pseudo-randomly. */ if (! strcmp (language_string, "GNU C") || ! strcmp (language_string, "GNU Objective-C")) i = 0; diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index 3c326d3..594f068 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -3074,7 +3074,7 @@ s390_build_va_list () false if implementing __builtin_varargs_va_start. NEXTARG points to the first anonymous stack argument. - The following global variables are used to initalize + The following global variables are used to initialize the va_list structure: current_function_args_info: diff --git a/gcc/config/s390/s390.h b/gcc/config/s390/s390.h index 4ecf2de..c4fd6fb 100644 --- a/gcc/config/s390/s390.h +++ b/gcc/config/s390/s390.h @@ -184,7 +184,7 @@ if (INTEGRAL_MODE_P (MODE) && \ #define EMPTY_FIELD_BOUNDARY 32 -/* Alignment on even adresses for LARL instruction. */ +/* Alignment on even addresses for LARL instruction. */ #define CONSTANT_ALIGNMENT(EXP, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 1b64987..1cb61c7 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -7509,7 +7509,7 @@ ultra_fpmode_conflict_exists (fpmode) continue; /* If it is not FMOV, FABS, FNEG, FDIV, or FSQRT then - we will get a stall. Loads and stores are independant + we will get a stall. Loads and stores are independent of these rules. */ if (GET_CODE (SET_SRC (pat)) != ABS && GET_CODE (SET_SRC (pat)) != NEG diff --git a/gcc/config/stormy16/stormy16.h b/gcc/config/stormy16/stormy16.h index f625ae8..7ca09e1 100644 --- a/gcc/config/stormy16/stormy16.h +++ b/gcc/config/stormy16/stormy16.h @@ -4795,7 +4795,7 @@ do { \ /* Some stabs encapsulation formats (in particular ECOFF), cannot handle the `.stabs "",N_FUN,,0,0,Lscope-function-1' gdb dbx - extention construct. On those machines, define this macro to turn + extension construct. On those machines, define this macro to turn this feature off without disturbing the rest of the gdb extensions. */ /* #define NO_DBX_FUNCTION_END */ diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index 96c04d9..8fc6b9c 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -7251,7 +7251,7 @@ This describes commands for alignment. @findex JUMP_ALIGN @item JUMP_ALIGN (@var{label}) The alignment (log base 2) to put in front of @var{label}, which is -a common destination of jumps and has no fallthru incomming edge. +a common destination of jumps and has no fallthru incoming edge. This macro need not be defined if you don't want any special alignment to be done at such a time. Most machine descriptions do not currently |