diff options
-rw-r--r-- | gcc/ChangeLog | 4 | ||||
-rw-r--r-- | gcc/config/aarch64/aarch64.md | 12 | ||||
-rw-r--r-- | gcc/testsuite/ChangeLog | 8 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/inline-lrint_1.c | 20 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/inline-lrint_2.c | 22 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/lrint-matherr.h | 5 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/no-inline-lrint_1.c | 20 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/no-inline-lrint_2.c | 20 |
8 files changed, 111 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9706455..6e1960f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -5,6 +5,10 @@ 2017-06-09 Tamar Christina <tamar.christina@arm.com> + * config/aarch64/aarch64.md (lrint<GPF:mode><GPI:mode>2): New. + +2017-06-09 Tamar Christina <tamar.christina@arm.com> + * config/arm/arm.c (arm_rtx_costs_internal): Make sdiv more expensive than udiv. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 2e9331f..1a721bf 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -4940,6 +4940,18 @@ [(set_attr "type" "f_minmax<stype>")] ) +(define_expand "lrint<GPF:mode><GPI:mode>2" + [(match_operand:GPI 0 "register_operand") + (match_operand:GPF 1 "register_operand")] + "TARGET_FLOAT" +{ + rtx cvt = gen_reg_rtx (<GPF:MODE>mode); + emit_insn (gen_rint<GPF:mode>2 (cvt, operands[1])); + emit_insn (gen_lbtrunc<GPF:mode><GPI:mode>2 (operands[0], cvt)); + DONE; +} +) + ;; For copysign (x, y), we want to generate: ;; ;; LDR d2, #(1 << 63) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 01f2d18..382805c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,13 @@ 2017-06-09 Tamar Christina <tamar.christina@arm.com> + * gcc.target/aarch64/lrint-matherr.h: New. + * gcc.target/aarch64/inline-lrint_1.c: New. + * gcc.target/aarch64/inline-lrint_2.c: New. + * gcc.target/aarch64/no-inline-lrint_1.c: New. + * gcc.target/aarch64/no-inline-lrint_2.c: New. + +2017-06-09 Tamar Christina <tamar.christina@arm.com> + * gcc.target/arm/sdiv_costs_1.c: New. 2017-06-09 Tom de Vries <tom@codesourcery.com> diff --git a/gcc/testsuite/gcc.target/aarch64/inline-lrint_1.c b/gcc/testsuite/gcc.target/aarch64/inline-lrint_1.c new file mode 100644 index 0000000..876cecd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/inline-lrint_1.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O3 -fno-math-errno" } */ + +#include "lrint-matherr.h" + +TEST (dld, double, long, ) +TEST (flf, float , long, ) + +TEST (did, double, int, ) +TEST (fif, float , int, ) + +TEST (dlld, double, long long, l) +TEST (fllf, float , long long, l) + +/* { dg-final { scan-assembler-times "frintx\td\[0-9\]+, d\[0-9\]+" 3 } } */ +/* { dg-final { scan-assembler-times "frintx\ts\[0-9\]+, s\[0-9\]+" 3 } } */ +/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, d\[0-9\]+" 3 } } */ +/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, s\[0-9\]+" 3 } } */ +/* { dg-final { scan-assembler-not "bl" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/inline-lrint_2.c b/gcc/testsuite/gcc.target/aarch64/inline-lrint_2.c new file mode 100644 index 0000000..baa5aee --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/inline-lrint_2.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O3 -fno-math-errno" } */ + +#include "lrint-matherr.h" + +TEST (dld, double, long, ) +TEST (flf, float , long, ) + +TEST (did, double, int, ) +TEST (fif, float , int, ) + +TEST (dlld, double, long long, l) +TEST (fllf, float , long long, l) + +/* { dg-final { scan-assembler-times "frintx\td\[0-9\]+, d\[0-9\]+" 3 } } */ +/* { dg-final { scan-assembler-times "frintx\ts\[0-9\]+, s\[0-9\]+" 3 } } */ +/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, d\[0-9\]+" 1 } } */ +/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, s\[0-9\]+" 1 } } */ +/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, d\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, s\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler-not "bl" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/lrint-matherr.h b/gcc/testsuite/gcc.target/aarch64/lrint-matherr.h new file mode 100644 index 0000000..cc6e3d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/lrint-matherr.h @@ -0,0 +1,5 @@ +#define TEST(name, float_type, int_type, pref) void f_##name (float_type x) \ +{ \ + volatile float_type a = __builtin_rint (x); \ + volatile int_type b = __builtin_l##pref##rint (x); \ +} diff --git a/gcc/testsuite/gcc.target/aarch64/no-inline-lrint_1.c b/gcc/testsuite/gcc.target/aarch64/no-inline-lrint_1.c new file mode 100644 index 0000000..fb7f065 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/no-inline-lrint_1.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O3" } */ + +#include "lrint-matherr.h" + +TEST (dld, double, long, ) +TEST (flf, float , long, ) + +TEST (did, double, int, ) +TEST (fif, float , int, ) + +TEST (dlld, double, long long, l) +TEST (fllf, float , long long, l) + +/* { dg-final { scan-assembler-times "frintx\td\[0-9\]+, d\[0-9\]+" 3 } } */ +/* { dg-final { scan-assembler-times "frintx\ts\[0-9\]+, s\[0-9\]+" 3 } } */ +/* { dg-final { scan-assembler-times "bl\tlrint" 4 } } */ +/* { dg-final { scan-assembler-times "bl\tllrint" 2 } } */ +/* { dg-final { scan-assembler-not "fcvtzs" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/no-inline-lrint_2.c b/gcc/testsuite/gcc.target/aarch64/no-inline-lrint_2.c new file mode 100644 index 0000000..c99843c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/no-inline-lrint_2.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O3" } */ + +#include "lrint-matherr.h" + +TEST (dld, double, long, ) +TEST (flf, float , long, ) + +TEST (did, double, int, ) +TEST (fif, float , int, ) + +TEST (dlld, double, long long, l) +TEST (fllf, float , long long, l) + +/* { dg-final { scan-assembler-times "frintx\td\[0-9\]+, d\[0-9\]+" 3 } } */ +/* { dg-final { scan-assembler-times "frintx\ts\[0-9\]+, s\[0-9\]+" 3 } } */ +/* { dg-final { scan-assembler-times "bl\tlrint" 4 } } */ +/* { dg-final { scan-assembler-times "bl\tllrint" 2 } } */ +/* { dg-final { scan-assembler-not "fcvtzs" } } */ |