diff options
17 files changed, 777 insertions, 2 deletions
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-helper.h b/gcc/testsuite/gcc.target/i386/avx512fp16-helper.h index ce3cfdc..69948f8 100644 --- a/gcc/testsuite/gcc.target/i386/avx512fp16-helper.h +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-helper.h @@ -172,9 +172,9 @@ init_src() for (i = 0; i < AVX512F_MAX_ELEM; i++) { v1.f32[i] = i + 1; - v2.f32[i] = i * 0.5f; + v2.f32[i] = (i + 2) * 0.5f; v3.f32[i] = i * 1.5f; - v4.f32[i] = i - 0.5f; + v4.f32[i] = i - 1.5f; src3.u32[i] = (i + 1) * 10; } @@ -234,10 +234,12 @@ init_dest(V512 * res, V512 * exp) #undef DF #undef H_HF #undef NET_MASK +#undef NET_CMASK #undef MASK_VALUE #undef HALF_MASK #undef ZMASK_VALUE #define NET_MASK 0xffff +#define NET_CMASK 0xff #define MASK_VALUE 0xcccc #define ZMASK_VALUE 0xfcc1 #define HALF_MASK 0xcc @@ -253,10 +255,12 @@ init_dest(V512 * res, V512 * exp) #undef SI #undef H_HF #undef NET_MASK +#undef NET_CMASK #undef MASK_VALUE #undef ZMASK_VALUE #undef HALF_MASK #define NET_MASK 0xff +#define NET_CMASK 0xff #define MASK_VALUE 0xcc #define HALF_MASK MASK_VALUE #define ZMASK_VALUE 0xc1 @@ -267,6 +271,7 @@ init_dest(V512 * res, V512 * exp) #define H_HF(x) x.xmmh[0] #else #define NET_MASK 0xffffffff +#define NET_CMASK 0xffff #define MASK_VALUE 0xcccccccc #define ZMASK_VALUE 0xfcc1fcc1 #define HALF_MASK 0xcccc diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vfcmaddcph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vfcmaddcph-1a.c new file mode 100644 index 0000000..6c2c34c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vfcmaddcph-1a.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vfcmaddcph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfcmaddcph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vfcmaddcph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfcmaddcph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfcmaddcph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vfcmaddcph\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m512h res, res1, res2; +volatile __m512h x1, x2, x3; +volatile __mmask16 m16; + +void extern +avx512f_test (void) +{ + res = _mm512_fcmadd_pch (x1, x2, x3); + res1 = _mm512_mask_fcmadd_pch (res1, m16, x1, x2); + res1 = _mm512_mask3_fcmadd_pch (res1, x1, x2, m16); + res2 = _mm512_maskz_fcmadd_pch (m16, x1, x2, x3); + res = _mm512_fcmadd_round_pch (x1, x2, x3, 8); + res1 = _mm512_mask_fcmadd_round_pch (res1, m16, x1, x2, 8); + res1 = _mm512_mask3_fcmadd_round_pch (res1, x1, x2, m16, 8); + res2 = _mm512_maskz_fcmadd_round_pch (m16, x1, x2, x3, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vfcmaddcph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vfcmaddcph-1b.c new file mode 100644 index 0000000..835699b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vfcmaddcph-1b.c @@ -0,0 +1,133 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(c_fmadd_pch) (V512 * dest, V512 op1, V512 op2, + __mmask16 k, int zero_mask, int c_flag, + int is_mask3) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + int invert = 1; + if (c_flag == 1) + invert = -1; + + unpack_ph_2twops(op1, &v1, &v2); + unpack_ph_2twops(op2, &v3, &v4); + unpack_ph_2twops(*dest, &v7, &v8); + + for (i = 0; i < 16; i++) { + if (((1 << (i / 2)) & k) == 0) { + if (zero_mask) { + v5.f32[i] = 0; + } + else { + v5.u32[i] = is_mask3 ? v3.u32[i] : v7.u32[i]; + } + } + else { + if ((i % 2) == 0) { + v5.f32[i] = v1.f32[i] * v7.f32[i] + - invert * (v1.f32[i+1] * v7.f32[i+1]) + v3.f32[i]; + } + else { + v5.f32[i] = v1.f32[i-1] * v7.f32[i] + + invert * (v1.f32[i] * v7.f32[i-1]) + v3.f32[i]; + + } + } + if (((1 << (i / 2 + 8)) & k) == 0) { + if (zero_mask) { + v6.f32[i] = 0; + } + else { + v6.u32[i] = is_mask3 ? v4.u32[i] : v8.u32[i]; + } + } + else { + if ((i % 2) == 0) { + v6.f32[i] = v2.f32[i] * v8.f32[i] + - invert * (v2.f32[i+1] * v8.f32[i+1]) + v4.f32[i]; + } + else { + v6.f32[i] = v2.f32[i-1] * v8.f32[i] + + invert * (v2.f32[i] * v8.f32[i-1]) + v4.f32[i]; + } + + } + } + + *dest = pack_twops_2ph(v5, v6); +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + init_dest(&res, &exp); + EMULATE(c_fmadd_pch)(&exp, src1, src2, NET_CMASK, 0, 1, 0); + HF(res) = INTRINSIC (_fcmadd_pch) (HF(res), HF(src1), + HF(src2)); + CHECK_RESULT (&res, &exp, N_ELEMS, _fcmadd_pch); + + init_dest(&res, &exp); + EMULATE(c_fmadd_pch)(&exp, src1, src2, HALF_MASK, 0, 1, 0); + HF(res) = INTRINSIC (_mask_fcmadd_pch) (HF(res) ,HALF_MASK, HF(src1), + HF(src2)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_fcmadd_pch); + + init_dest(&res, &exp); + EMULATE(c_fmadd_pch)(&exp, src1, src2, HALF_MASK, 0, 1, 1); + HF(res) = INTRINSIC (_mask3_fcmadd_pch) (HF(res), HF(src1), + HF(src2), HALF_MASK); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask3_fcmadd_pch); + + + init_dest(&res, &exp); + EMULATE(c_fmadd_pch)(&exp, src1, src2, HALF_MASK, 1, 1, 0); + HF(res) = INTRINSIC (_maskz_fcmadd_pch) (HALF_MASK, HF(res), + HF(src1), HF(src2)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_fcmadd_pch); + +#if AVX512F_LEN == 512 + init_dest(&res, &exp); + EMULATE(c_fmadd_pch)(&exp, src1, src2, NET_CMASK, 0, 1, 0); + HF(res) = INTRINSIC (_fcmadd_round_pch) (HF(res), HF(src1), + HF(src2), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _fcmadd_pch); + + init_dest(&res, &exp); + EMULATE(c_fmadd_pch)(&exp, src1, src2, HALF_MASK, 0, 1, 0); + HF(res) = INTRINSIC (_mask_fcmadd_round_pch) (HF(res) ,HALF_MASK, HF(src1), + HF(src2), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_fcmadd_pch); + + init_dest(&res, &exp); + EMULATE(c_fmadd_pch)(&exp, src1, src2, HALF_MASK, 0, 1, 1); + HF(res) = INTRINSIC (_mask3_fcmadd_round_pch) (HF(res), HF(src1), + HF(src2), HALF_MASK, _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask3_fcmadd_pch); + + + init_dest(&res, &exp); + EMULATE(c_fmadd_pch)(&exp, src1, src2, HALF_MASK, 1, 1, 0); + HF(res) = INTRINSIC (_maskz_fcmadd_round_pch) (HALF_MASK, HF(res), + HF(src1), HF(src2), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_fcmadd_pch); +#endif + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vfcmulcph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vfcmulcph-1a.c new file mode 100644 index 0000000..ca2f140 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vfcmulcph-1a.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vfcmulcph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfcmulcph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfcmulcph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfcmulcph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfcmulcph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfcmulcph\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m512h res, res1, res2; +volatile __m512h x1, x2, x3; +volatile __mmask16 m16; + +void extern +avx512f_test (void) +{ + res = _mm512_fcmul_pch (x1, x2); + res1 = _mm512_mask_fcmul_pch (res1, m16, x1, x2); + res2 = _mm512_maskz_fcmul_pch (m16, x1, x2); + res = _mm512_fcmul_round_pch (x1, x2, 8); + res1 = _mm512_mask_fcmul_round_pch (res1, m16, x1, x2, 8); + res2 = _mm512_maskz_fcmul_round_pch (m16, x1, x2, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vfcmulcph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vfcmulcph-1b.c new file mode 100644 index 0000000..ee41f6c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vfcmulcph-1b.c @@ -0,0 +1,111 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(c_fmul_pch) (V512 * dest, V512 op1, V512 op2, + __mmask16 k, int zero_mask, int c_flag) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + int invert = 1; + if (c_flag == 1) + invert = -1; + + unpack_ph_2twops(op1, &v1, &v2); + unpack_ph_2twops(op2, &v3, &v4); + unpack_ph_2twops(*dest, &v7, &v8); + + for (i = 0; i < 16; i++) { + if (((1 << (i / 2)) & k) == 0) { + if (zero_mask) { + v5.f32[i] = 0; + } + else { + v5.u32[i] = v7.u32[i]; + } + } + else { + if ((i % 2) == 0) { + v5.f32[i] = v1.f32[i] * v3.f32[i] + - invert * (v1.f32[i+1] * v3.f32[i+1]); + } + else { + v5.f32[i] = v1.f32[i] * v3.f32[i-1] + + invert * (v1.f32[i-1] * v3.f32[i]); + + } + } + if (((1 << (i / 2 + 8)) & k) == 0) { + if (zero_mask) { + v6.f32[i] = 0; + } + else { + v6.u32[i] = v8.u32[i]; + } + } + else { + if ((i % 2) == 0) { + v6.f32[i] = v2.f32[i] * v4.f32[i] + - invert * (v2.f32[i+1] * v4.f32[i+1]); + } + else { + v6.f32[i] = v2.f32[i] * v4.f32[i-1] + + invert * (v2.f32[i-1] * v4.f32[i]); + } + + } + } + + *dest = pack_twops_2ph(v5, v6); +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(c_fmul_pch)(&exp, src1, src2, NET_CMASK, 0, 1); + HF(res) = INTRINSIC (_fcmul_pch) (HF(src1), HF(src2)); + CHECK_RESULT (&res, &exp, N_ELEMS, _fcmul_pch); + + init_dest(&res, &exp); + EMULATE(c_fmul_pch)(&exp, src1, src2, HALF_MASK, 0, 1); + HF(res) = INTRINSIC (_mask_fcmul_pch) (HF(res) ,HALF_MASK, HF(src1), + HF(src2)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_fcmul_pch); + + EMULATE(c_fmul_pch)(&exp, src1, src2, HALF_MASK, 1, 1); + HF(res) = INTRINSIC (_maskz_fcmul_pch) ( HALF_MASK, HF(src1), + HF(src2)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_fcmul_pch); + +#if AVX512F_LEN == 512 + EMULATE(c_fmul_pch)(&exp, src1, src2, NET_CMASK, 0, 1); + HF(res) = INTRINSIC (_fcmul_round_pch) (HF(src1), HF(src2), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _fcmul_round_pch); + + init_dest(&res, &exp); + EMULATE(c_fmul_pch)(&exp, src1, src2, HALF_MASK, 0, 1); + HF(res) = INTRINSIC (_mask_fcmul_round_pch) (HF(res) ,HALF_MASK, HF(src1), + HF(src2), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_fcmul_round_pch); + + EMULATE(c_fmul_pch)(&exp, src1, src2, HALF_MASK, 1, 1); + HF(res) = INTRINSIC (_maskz_fcmul_round_pch) ( HALF_MASK, HF(src1), + HF(src2), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_fcmul_round_pch); +#endif + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vfmaddcph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vfmaddcph-1a.c new file mode 100644 index 0000000..4dae5f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vfmaddcph-1a.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vfmaddcph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmaddcph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vfmaddcph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmaddcph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmaddcph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vfmaddcph\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m512h res, res1, res2; +volatile __m512h x1, x2, x3; +volatile __mmask16 m16; + +void extern +avx512f_test (void) +{ + res = _mm512_fmadd_pch (x1, x2, x3); + res1 = _mm512_mask_fmadd_pch (res1, m16, x1, x2); + res1 = _mm512_mask3_fmadd_pch (res1, x1, x2, m16); + res2 = _mm512_maskz_fmadd_pch (m16, x1, x2, x3); + res = _mm512_fmadd_round_pch (x1, x2, x3, 8); + res1 = _mm512_mask_fmadd_round_pch (res1, m16, x1, x2, 8); + res1 = _mm512_mask3_fmadd_round_pch (res1, x1, x2, m16, 8); + res2 = _mm512_maskz_fmadd_round_pch (m16, x1, x2, x3, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vfmaddcph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vfmaddcph-1b.c new file mode 100644 index 0000000..1da6f01 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vfmaddcph-1b.c @@ -0,0 +1,131 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(c_fmadd_pch) (V512 * dest, V512 op1, V512 op2, + __mmask16 k, int zero_mask, int c_flag, + int is_mask3) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + int invert = 1; + if (c_flag == 1) + invert = -1; + + unpack_ph_2twops(op1, &v1, &v2); + unpack_ph_2twops(op2, &v3, &v4); + unpack_ph_2twops(*dest, &v7, &v8); + + for (i = 0; i < 16; i++) { + if (((1 << (i / 2)) & k) == 0) { + if (zero_mask) { + v5.f32[i] = 0; + } + else { + v5.u32[i] = is_mask3 ? v3.u32[i] : v7.u32[i]; + } + } + else { + if ((i % 2) == 0) { + v5.f32[i] = v1.f32[i] * v7.f32[i] + - invert * (v1.f32[i+1] * v7.f32[i+1]) + v3.f32[i]; + } + else { + v5.f32[i] = v1.f32[i-1] * v7.f32[i] + + invert * (v1.f32[i] * v7.f32[i-1]) + v3.f32[i]; + + } + } + if (((1 << (i / 2 + 8)) & k) == 0) { + if (zero_mask) { + v6.f32[i] = 0; + } + else { + v6.u32[i] = is_mask3 ? v4.u32[i] : v8.u32[i]; + } + } + else { + if ((i % 2) == 0) { + v6.f32[i] = v2.f32[i] * v8.f32[i] + - invert * (v2.f32[i+1] * v8.f32[i+1]) + v4.f32[i]; + } + else { + v6.f32[i] = v2.f32[i-1] * v8.f32[i] + + invert * (v2.f32[i] * v8.f32[i-1]) + v4.f32[i]; + } + + } + } + + *dest = pack_twops_2ph(v5, v6); +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + init_dest(&res, &exp); + EMULATE(c_fmadd_pch)(&exp, src1, src2, NET_CMASK, 0, 0, 0); + HF(res) = INTRINSIC (_fmadd_pch) (HF(res), HF(src1), + HF(src2)); + CHECK_RESULT (&res, &exp, N_ELEMS, _fmadd_pch); + + init_dest(&res, &exp); + EMULATE(c_fmadd_pch)(&exp, src1, src2, HALF_MASK, 0, 0, 0); + HF(res) = INTRINSIC (_mask_fmadd_pch) (HF(res), HALF_MASK, HF(src1), + HF(src2)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_fmadd_pch); + + init_dest(&res, &exp); + EMULATE(c_fmadd_pch)(&exp, src1, src2, HALF_MASK, 0, 0, 1); + HF(res) = INTRINSIC (_mask3_fmadd_pch) (HF(res), HF(src1), HF(src2), + HALF_MASK); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask3_fmadd_pch); + + init_dest(&res, &exp); + EMULATE(c_fmadd_pch)(&exp, src1, src2, HALF_MASK, 1, 0, 0); + HF(res) = INTRINSIC (_maskz_fmadd_pch) (HALF_MASK, HF(res), HF(src1), + HF(src2)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_fmadd_pch); + +#if AVX512F_LEN == 512 + init_dest(&res, &exp); + EMULATE(c_fmadd_pch)(&exp, src1, src2, NET_CMASK, 0, 0, 0); + HF(res) = INTRINSIC (_fmadd_round_pch) (HF(res), HF(src1), + HF(src2), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _fmadd_pch); + + init_dest(&res, &exp); + EMULATE(c_fmadd_pch)(&exp, src1, src2, HALF_MASK, 0, 0, 0); + HF(res) = INTRINSIC (_mask_fmadd_round_pch) (HF(res), HALF_MASK, HF(src1), + HF(src2), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_fmadd_pch); + + init_dest(&res, &exp); + EMULATE(c_fmadd_pch)(&exp, src1, src2, HALF_MASK, 0, 0, 1); + HF(res) = INTRINSIC (_mask3_fmadd_round_pch) (HF(res), HF(src1), HF(src2), + HALF_MASK, _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask3_fmadd_pch); + + init_dest(&res, &exp); + EMULATE(c_fmadd_pch)(&exp, src1, src2, HALF_MASK, 1, 0, 0); + HF(res) = INTRINSIC (_maskz_fmadd_round_pch) (HALF_MASK, HF(res), HF(src1), + HF(src2), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_fmadd_pch); +#endif + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vfmulcph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vfmulcph-1a.c new file mode 100644 index 0000000..f31cbca --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vfmulcph-1a.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vfmulcph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmulcph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmulcph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmulcph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmulcph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmulcph\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m512h res, res1, res2; +volatile __m512h x1, x2, x3; +volatile __mmask16 m16; + +void extern +avx512f_test (void) +{ + res = _mm512_fmul_pch (x1, x2); + res1 = _mm512_mask_fmul_pch (res1, m16, x1, x2); + res2 = _mm512_maskz_fmul_pch (m16, x1, x2); + res = _mm512_fmul_round_pch (x1, x2, 8); + res1 = _mm512_mask_fmul_round_pch (res1, m16, x1, x2, 8); + res2 = _mm512_maskz_fmul_round_pch (m16, x1, x2, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vfmulcph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vfmulcph-1b.c new file mode 100644 index 0000000..d9bb1b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vfmulcph-1b.c @@ -0,0 +1,115 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(c_fmul_pch) (V512 * dest, V512 op1, V512 op2, + __mmask16 k, int zero_mask, int c_flag) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + int invert = 1; + if (c_flag == 1) + invert = -1; + + unpack_ph_2twops(op1, &v1, &v2); + unpack_ph_2twops(op2, &v3, &v4); + unpack_ph_2twops(*dest, &v7, &v8); + + for (i = 0; i < 16; i++) { + if (((1 << (i / 2)) & k) == 0) { + if (zero_mask) { + v5.f32[i] = 0; + } + else { + v5.u32[i] = v7.u32[i]; + } + } + else { + if ((i % 2) == 0) { + v5.f32[i] = v1.f32[i] * v3.f32[i] + - invert * (v1.f32[i+1] * v3.f32[i+1]); + } + else { + v5.f32[i] = v1.f32[i-1] * v3.f32[i] + + invert * (v1.f32[i] * v3.f32[i-1]); + + } + } + if (((1 << (i / 2 + 8)) & k) == 0) { + if (zero_mask) { + v6.f32[i] = 0; + } + else { + v6.u32[i] = v8.u32[i]; + } + } + else { + if ((i % 2) == 0) { + v6.f32[i] = v2.f32[i] * v4.f32[i] + - invert * (v2.f32[i+1] * v4.f32[i+1]); + } + else { + v6.f32[i] = v2.f32[i-1] * v4.f32[i] + + invert * (v2.f32[i] * v4.f32[i-1]); + } + + } + } + + *dest = pack_twops_2ph(v5, v6); +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(c_fmul_pch)(&exp, src1, src2, NET_CMASK, 0, 0); + HF(res) = INTRINSIC (_fmul_pch) (HF(src1), HF(src2)); + CHECK_RESULT (&res, &exp, N_ELEMS, _fmul_pch); + + init_dest(&res, &exp); + EMULATE(c_fmul_pch)(&exp, src1, src2, HALF_MASK, 0, 0); + HF(res) = INTRINSIC (_mask_fmul_pch) (HF(res),HALF_MASK, HF(src1), + HF(src2)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_fmul_pch); + + init_dest(&res, &exp); + EMULATE(c_fmul_pch)(&exp, src1, src2, HALF_MASK, 1, 0); + HF(res) = INTRINSIC (_maskz_fmul_pch) (HALF_MASK, HF(src1), + HF(src2)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_fmul_pch); + +#if AVX512F_LEN == 512 + init_dest(&res, &exp); + EMULATE(c_fmul_pch)(&exp, src1, src2, NET_CMASK, 0, 0); + HF(res) = INTRINSIC (_fmul_round_pch) (HF(src1), HF(src2), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _fmul_pch); + + init_dest(&res, &exp); + EMULATE(c_fmul_pch)(&exp, src1, src2, HALF_MASK, 0, 0); + HF(res) = INTRINSIC (_mask_fmul_round_pch) (HF(res),HALF_MASK, HF(src1), + HF(src2), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_fmul_pch); + + init_dest(&res, &exp); + EMULATE(c_fmul_pch)(&exp, src1, src2, HALF_MASK, 1, 0); + HF(res) = INTRINSIC (_maskz_fmul_round_pch) (HALF_MASK, HF(src1), + HF(src2), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_fmul_pch); +#endif + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfcmaddcph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfcmaddcph-1a.c new file mode 100644 index 0000000..eff1381 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfcmaddcph-1a.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vfcmaddcph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfcmaddcph\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vfcmaddcph\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfcmaddcph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfcmaddcph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vfcmaddcph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m256h res1; +volatile __m128h res2; +volatile __m256h x1, x2, x3; +volatile __m128h x4, x5, x6; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_fcmadd_pch (x1, x2, x3); + res1 = _mm256_mask_fcmadd_pch (res1, m8, x1, x2); + res1 = _mm256_mask3_fcmadd_pch (res1, x1, x2, m8); + res1 = _mm256_maskz_fcmadd_pch (m8, x1, x2, x3); + + res2 = _mm_fcmadd_pch (x4, x5, x6); + res2 = _mm_mask_fcmadd_pch (res2, m8, x4, x5); + res2 = _mm_mask3_fcmadd_pch (res2, x4, x5, m8); + res2 = _mm_maskz_fcmadd_pch (m8, x4, x5, x6); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfcmaddcph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfcmaddcph-1b.c new file mode 100644 index 0000000..5e3a54e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfcmaddcph-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vfcmaddcph-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vfcmaddcph-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfcmulcph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfcmulcph-1a.c new file mode 100644 index 0000000..4e48e9c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfcmulcph-1a.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512f -mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vfcmulcph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfcmulcph\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfcmulcph\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfcmulcph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfcmulcph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfcmulcph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m256h res1; +volatile __m128h res2; +volatile __m256h x1, x2, x3; +volatile __m128h x4, x5, x6; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_fcmul_pch (x1, x2); + res1 = _mm256_mask_fcmul_pch (res1, m8, x1, x2); + res1 = _mm256_maskz_fcmul_pch (m8, x1, x2); + + res2 = _mm_fcmul_pch (x4, x5); + res2 = _mm_mask_fcmul_pch (res2, m8, x4, x5); + res2 = _mm_maskz_fcmul_pch (m8, x4, x5); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfcmulcph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfcmulcph-1b.c new file mode 100644 index 0000000..19564a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfcmulcph-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vfcmulcph-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vfcmulcph-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfmaddcph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfmaddcph-1a.c new file mode 100644 index 0000000..b9a24d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfmaddcph-1a.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vfmaddcph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmaddcph\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vfmaddcph\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmaddcph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmaddcph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vfmaddcph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m256h res1; +volatile __m128h res2; +volatile __m256h x1, x2, x3; +volatile __m128h x4, x5, x6; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_fmadd_pch (x1, x2, x3); + res1 = _mm256_mask_fmadd_pch (res1, m8, x1, x2); + res1 = _mm256_mask3_fmadd_pch (res1, x1, x2, m8); + res1 = _mm256_maskz_fmadd_pch (m8, x1, x2, x3); + + res2 = _mm_fmadd_pch (x4, x5, x6); + res2 = _mm_mask_fmadd_pch (res2, m8, x4, x5); + res2 = _mm_mask3_fmadd_pch (res2, x4, x5, m8); + res2 = _mm_maskz_fmadd_pch (m8, x4, x5, x6); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfmaddcph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfmaddcph-1b.c new file mode 100644 index 0000000..bf85fea --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfmaddcph-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vfmaddcph-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vfmaddcph-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfmulcph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfmulcph-1a.c new file mode 100644 index 0000000..54e58c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfmulcph-1a.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512f -mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vfmulcph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmulcph\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmulcph\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmulcph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmulcph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmulcph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m256h res1; +volatile __m128h res2; +volatile __m256h x1, x2, x3; +volatile __m128h x4, x5, x6; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_fmul_pch (x1, x2); + res1 = _mm256_mask_fmul_pch (res1, m8, x1, x2); + res1 = _mm256_maskz_fmul_pch (m8, x1, x2); + + res2 = _mm_fmul_pch (x4, x5); + res2 = _mm_mask_fmul_pch (res2, m8, x4, x5); + res2 = _mm_maskz_fmul_pch (m8, x4, x5); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfmulcph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfmulcph-1b.c new file mode 100644 index 0000000..f88d842 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfmulcph-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vfmulcph-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vfmulcph-1b.c" + |