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| -rw-r--r-- | gcc/ChangeLog | 519 | ||||
| -rw-r--r-- | gcc/DATESTAMP | 2 | ||||
| -rw-r--r-- | gcc/analyzer/ChangeLog | 22 | ||||
| -rw-r--r-- | gcc/cp/ChangeLog | 37 | ||||
| -rw-r--r-- | gcc/fortran/ChangeLog | 42 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 378 | ||||
| -rw-r--r-- | libgcc/ChangeLog | 38 | ||||
| -rw-r--r-- | libgomp/ChangeLog | 22 |
8 files changed, 1059 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6a402c8..2ff57b8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,522 @@ +2023-12-08 Vladimir N. Makarov <vmakarov@redhat.com> + + PR rtl-optimization/112875 + * lra-eliminations.cc (lra_eliminate_regs_1): Change an assert. + Add ASM_OPERANDS case. + +2023-12-08 Robin Dapp <rdapp@ventanamicro.com> + + PR target/112109 + * config/riscv/riscv-protos.h (expand_strcmp): Declare. + * config/riscv/riscv-string.cc (riscv_expand_strcmp): Add + strategy handling and delegation to scalar and vector expanders. + (expand_strcmp): Vectorized implementation. + * config/riscv/riscv.md: Add TARGET_VECTOR to strcmp and strncmp + expander. + +2023-12-08 Robin Dapp <rdapp@ventanamicro.com> + + PR target/112109 + * config/riscv/riscv-protos.h (expand_rawmemchr): Add strlen + parameter. + * config/riscv/riscv-string.cc (riscv_expand_strlen): Call + rawmemchr. + (expand_rawmemchr): Add strlen handling. + * config/riscv/riscv.md: Add TARGET_VECTOR to strlen expander. + +2023-12-08 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-early-ra.cc (allocno_info::chain_next): + Put into an enum with... + (allocno_info::last_def_point): ...new member variable. + (allocno_info::m_current_bb_point): New member variable. + (likely_operand_match_p): Switch based on get_constraint_type, + rather than based on rtx code. Handle relaxed and special memory + constraints. + (early_ra::record_copy): Allow the source of an equivalence to be + assigned to more than once. + (early_ra::record_allocno_use): Invalidate any previous equivalence. + Initialize last_def_point. + (early_ra::record_allocno_def): Set last_def_point. + (early_ra::valid_equivalence_p): New function, split out from... + (early_ra::record_copy): ...here. Use last_def_point to handle + source registers that have a later definition. + (make_pass_aarch64_early_ra): Fix comment. + +2023-12-08 Richard Earnshaw <rearnsha@arm.com> + + Revert: + 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com> + + * config/arm/arm_neon.h + (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New. + (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New. + (vld1q_f16_x2, vld1q_f32_x2): New. + (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New. + (vld1q_bf16_x2): New. + * config/arm/arm_neon_builtins.def (vld1_x2): New entries. + * config/arm/neon.md (vld1_x2<mode>): New. + +2023-12-08 Richard Earnshaw <rearnsha@arm.com> + + Revert: + 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com> + + * config/arm/arm_neon.h + (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New. + (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New. + (vld1q_f16_x3, vld1q_f32_x3): New. + (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New. + (vld1q_bf16_x3): New. + * config/arm/arm_neon_builtins.def (vld1_x3): New entries. + * config/arm/neon.md (vld1_x3<mode>): New. + +2023-12-08 Richard Earnshaw <rearnsha@arm.com> + + Revert: + 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com> + + * config/arm/arm_neon.h + (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New. + (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New. + (vld1q_f16_x4, vld1q_f32_x4): New. + (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New. + (vld1q_bf16_x4): New. + * config/arm/arm_neon_builtins.def (vld1_x4): New entries. + * config/arm/neon.md (vld1_x4<mode>): New. + +2023-12-08 Richard Earnshaw <rearnsha@arm.com> + + Revert: + 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com> + + * config/arm/arm_neon.h + (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New. + (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New. + (vst1_f16_x2, vst1_f32_x2): New. + (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New. + (vst1_bf16_x2): New. + * config/arm/arm_neon_builtins.def (vst1_x2): New entries. + * config/arm/neon.md (vst1_x2<mode>): New. + +2023-12-08 Richard Earnshaw <rearnsha@arm.com> + + Revert: + 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com> + + * config/arm/arm_neon.h + (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New. + (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New. + (vst1_f16_x3, vst1_f32_x3): New. + (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New. + (vst1_bf16_x3): New. + * config/arm/arm_neon_builtins.def (vst1_x3): New entries. + * config/arm/neon.md (vst1_x3<mode>): New. + +2023-12-08 Richard Earnshaw <rearnsha@arm.com> + + Revert: + 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com> + + * config/arm/arm_neon.h + (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New. + (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New. + (vst1_f16_x4, vst1_f32_x4): New. + (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New. + (vst1_bf16_x4): New. + * config/arm/arm_neon_builtins.def (vst1_x4): New entries. + * config/arm/neon.md (vst1_x4<mode>): New. + +2023-12-08 Richard Earnshaw <rearnsha@arm.com> + + Revert: + 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com> + + * config/arm/arm_neon.h + (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New. + (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New. + (vst1q_f16_x2, vst1q_f32_x2): New. + (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New. + (vst1q_bf16_x2): New. + * config/arm/arm_neon_builtins.def (vst1q_x2): New entries. + * config/arm/neon.md + (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from + neon_vst1_x2<mode>. + * config/arm/iterators.md (VMEMX2): New mode iterator. + (VMEMX2_q): New mode attribute. + +2023-12-08 Richard Earnshaw <rearnsha@arm.com> + + Revert: + 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com> + + * config/arm/arm_neon.h + (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New. + (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New. + (vst1q_f16_x3, vst1q_f32_x3): New. + (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New. + (vst1q_bf16_x3): New. + * config/arm/arm_neon_builtins.def (vst1q_x3): New entries. + * config/arm/neon.md (neon_vst1q_x3<mode>): New. + +2023-12-08 Richard Earnshaw <rearnsha@arm.com> + + Revert: + 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com> + + * config/arm/arm_neon.h + (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New. + (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New. + (vst1q_f16_x4, vst1q_f32_x4): New. + (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New. + (vst1q_bf16_x4): New. + * config/arm/arm_neon_builtins.def (vst1q_x4): New entries. + * config/arm/neon.md (neon_vst1q_x4<mode>): New. + +2023-12-08 Richard Earnshaw <rearnsha@arm.com> + + Revert: + 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com> + + * config/arm/arm_neon.h + (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New + (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New. + (vld1_f16_x2, vld1_f32_x2): New. + (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New. + (vld1_bf16_x2): New. + (vld1q_types_x2): Updated to use vld1q_x2 from + arm_neon_builtins.def + * config/arm/arm_neon_builtins.def + (vld1_x2): Updated entries. + (vld1q_x2): New entries, but comes from the old vld1_x2 + * config/arm/neon.md + (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated + from neon_vld1_x2<mode>. + +2023-12-08 Richard Earnshaw <rearnsha@arm.com> + + Revert: + 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com> + + * config/arm/arm_neon.h + (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New + (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New. + (vld1_f16_x3, vld1_f32_x3): New. + (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New. + (vld1_bf16_x3): New. + (vld1q_types_x3): Updated to use vld1q_x3 from + arm_neon_builtins.def + * config/arm/arm_neon_builtins.def + (vld1_x3): Updated entries. + (vld1q_x3): New entries, but comes from the old vld1_x2 + * config/arm/neon.md (neon_vld1q_x3<mode>): Updated from + neon_vld1_x3<mode>. + +2023-12-08 Richard Earnshaw <rearnsha@arm.com> + + Revert: + 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com> + + * config/arm/arm_neon.h + (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New + (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New. + (vld1_f16_x4, vld1_f32_x4): New. + (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New. + (vld1_bf16_x4): New. + (vld1q_types_x4): Updated to use vld1q_x4 + from arm_neon_builtins.def + * config/arm/arm_neon_builtins.def + (vld1_x4): Updated entries. + (vld1q_x4): New entries, but comes from the old vld1_x2 + * config/arm/neon.md (neon_vld1q_x4<mode>): + Updated from neon_vld1_x4<mode>. + +2023-12-08 Tobias Burnus <tobias@codesourcery.com> + + * builtin-types.def (BT_FN_PTR_PTR_SIZE_PTRMODE_PTRMODE): New. + * omp-builtins.def (BUILT_IN_GOMP_REALLOC): New. + * builtins.cc (builtin_fnspec): Handle it. + * gimple-ssa-warn-access.cc (fndecl_alloc_p, + matching_alloc_calls_p): Likewise. + * gimple.cc (nonfreeing_call_p): Likewise. + * predict.cc (expr_expected_value_1): Likewise. + * tree-ssa-ccp.cc (evaluate_stmt): Likewise. + * tree.cc (fndecl_dealloc_argno): Likewise. + +2023-12-08 Richard Biener <rguenther@suse.de> + + PR tree-optimization/112909 + * tree-ssa-uninit.cc (find_uninit_use): Look through a + single level of SSA name copies with single use. + +2023-12-08 Jiahao Xu <xujiahao@loongson.cn> + + * config/loongarch/loongarch.cc (loongarch_try_expand_lsx_vshuf_const): Use + simplify_gen_subreg instead of gen_rtx_SUBREG. + (loongarch_expand_vec_perm_const_2): Ditto. + (loongarch_expand_vec_cond_expr): Ditto. + +2023-12-08 Jiahao Xu <xujiahao@loongson.cn> + + * config/loongarch/loongarch.cc (loongarch_vector_costs::determine_suggested_unroll_factor): + If m_has_recip is true, uf return 1. + (loongarch_vector_costs::add_stmt_cost): Detect the use of approximate instruction sequence. + +2023-12-08 Jiahao Xu <xujiahao@loongson.cn> + + * config/loongarch/genopts/loongarch.opt.in (recip_mask): New variable. + (-mrecip, -mrecip): New options. + * config/loongarch/lasx.md (div<mode>3): New expander. + (*div<mode>3): Rename. + (sqrt<mode>2): New expander. + (*sqrt<mode>2): Rename. + (rsqrt<mode>2): New expander. + * config/loongarch/loongarch-protos.h (loongarch_emit_swrsqrtsf): New prototype. + (loongarch_emit_swdivsf): Ditto. + * config/loongarch/loongarch.cc (loongarch_option_override_internal): Set + recip_mask for -mrecip and -mrecip= options. + (loongarch_emit_swrsqrtsf): New function. + (loongarch_emit_swdivsf): Ditto. + * config/loongarch/loongarch.h (RECIP_MASK_NONE, RECIP_MASK_DIV, RECIP_MASK_SQRT + RECIP_MASK_RSQRT, RECIP_MASK_VEC_DIV, RECIP_MASK_VEC_SQRT, RECIP_MASK_VEC_RSQRT + RECIP_MASK_ALL): New bitmasks. + (TARGET_RECIP_DIV, TARGET_RECIP_SQRT, TARGET_RECIP_RSQRT, TARGET_RECIP_VEC_DIV + TARGET_RECIP_VEC_SQRT, TARGET_RECIP_VEC_RSQRT): New tests. + * config/loongarch/loongarch.md (sqrt<mode>2): New expander. + (*sqrt<mode>2): Rename. + (rsqrt<mode>2): New expander. + * config/loongarch/loongarch.opt (recip_mask): New variable. + (-mrecip, -mrecip): New options. + * config/loongarch/lsx.md (div<mode>3): New expander. + (*div<mode>3): Rename. + (sqrt<mode>2): New expander. + (*sqrt<mode>2): Rename. + (rsqrt<mode>2): New expander. + * config/loongarch/predicates.md (reg_or_vecotr_1_operand): New predicate. + * doc/invoke.texi (LoongArch Options): Document new options. + +2023-12-08 Jiahao Xu <xujiahao@loongson.cn> + + * config/loongarch/lasx.md (lasx_xvfrecip_<flasxfmt>): Renamed to .. + (recip<mode>3): .. this. + * config/loongarch/loongarch-builtins.cc (CODE_FOR_lsx_vfrecip_d): Redefine + to new pattern name. + (CODE_FOR_lsx_vfrecip_s): Ditto. + (CODE_FOR_lasx_xvfrecip_d): Ditto. + (CODE_FOR_lasx_xvfrecip_s): Ditto. + (loongarch_expand_builtin_direct): For the vector recip instructions, construct a + temporary parameter const1_vector. + * config/loongarch/lsx.md (lsx_vfrecip_<flsxfmt>): Renamed to .. + (recip<mode>3): .. this. + * config/loongarch/predicates.md (const_vector_1_operand): New predicate. + +2023-12-08 Jiahao Xu <xujiahao@loongson.cn> + + * config/loongarch/lasx.md (lasx_xvfrsqrt_<flasxfmt>): Renamed to .. + (rsqrt<mode>2): .. this. + * config/loongarch/loongarch-builtins.cc + (CODE_FOR_lsx_vfrsqrt_d): Redefine to standard pattern name. + (CODE_FOR_lsx_vfrsqrt_s): Ditto. + (CODE_FOR_lasx_xvfrsqrt_d): Ditto. + (CODE_FOR_lasx_xvfrsqrt_s): Ditto. + * config/loongarch/loongarch.cc (use_rsqrt_p): New function. + (loongarch_optab_supported_p): Ditto. + (TARGET_OPTAB_SUPPORTED_P): New hook. + * config/loongarch/loongarch.md (*rsqrt<mode>a): Remove. + (*rsqrt<mode>2): New insn pattern. + (*rsqrt<mode>b): Remove. + * config/loongarch/lsx.md (lsx_vfrsqrt_<flsxfmt>): Renamed to .. + (rsqrt<mode>2): .. this. + +2023-12-08 Jiahao Xu <xujiahao@loongson.cn> + + * config/loongarch/genopts/isa-evolution.in (fecipe): Add. + * config/loongarch/larchintrin.h (__frecipe_s): New intrinsic. + (__frecipe_d): Ditto. + (__frsqrte_s): Ditto. + (__frsqrte_d): Ditto. + * config/loongarch/lasx.md (lasx_xvfrecipe_<flasxfmt>): New insn pattern. + (lasx_xvfrsqrte_<flasxfmt>): Ditto. + * config/loongarch/lasxintrin.h (__lasx_xvfrecipe_s): New intrinsic. + (__lasx_xvfrecipe_d): Ditto. + (__lasx_xvfrsqrte_s): Ditto. + (__lasx_xvfrsqrte_d): Ditto. + * config/loongarch/loongarch-builtins.cc (AVAIL_ALL): Add predicates. + (LSX_EXT_BUILTIN): New macro. + (LASX_EXT_BUILTIN): Ditto. + * config/loongarch/loongarch-cpucfg-map.h: Regenerate. + * config/loongarch/loongarch-c.cc: Add builtin macro "__loongarch_frecipe". + * config/loongarch/loongarch-def.cc: Regenerate. + * config/loongarch/loongarch-str.h (OPTSTR_FRECIPE): Regenerate. + * config/loongarch/loongarch.cc (loongarch_asm_code_end): Dump status for TARGET_FRECIPE. + * config/loongarch/loongarch.md (loongarch_frecipe_<fmt>): New insn pattern. + (loongarch_frsqrte_<fmt>): Ditto. + * config/loongarch/loongarch.opt: Regenerate. + * config/loongarch/lsx.md (lsx_vfrecipe_<flsxfmt>): New insn pattern. + (lsx_vfrsqrte_<flsxfmt>): Ditto. + * config/loongarch/lsxintrin.h (__lsx_vfrecipe_s): New intrinsic. + (__lsx_vfrecipe_d): Ditto. + (__lsx_vfrsqrte_s): Ditto. + (__lsx_vfrsqrte_d): Ditto. + * doc/extend.texi: Add documentation for LoongArch new builtins and intrinsics. + +2023-12-08 Richard Biener <rguenther@suse.de> + + * tree-outof-ssa.cc (rewrite_out_of_ssa): Dump GIMPLE once only, + after final IL adjustments. + +2023-12-08 Pan Li <pan2.li@intel.com> + + * config/riscv/vector-iterators.md: Replace RVVM2SI to RVVM2SF + for mode attr V_F2DI_CONVERT_BRIDGE. + +2023-12-08 Jiahao Xu <xujiahao@loongson.cn> + + * config/loongarch/lasx.md (xorsign<mode>3): New expander. + * config/loongarch/loongarch.cc (loongarch_can_change_mode_class): Allow + conversion between LSX vector mode and scalar fp mode. + * config/loongarch/loongarch.md (@xorsign<mode>3): New expander. + * config/loongarch/lsx.md (@xorsign<mode>3): Ditto. + +2023-12-08 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/112902 + * gimple-lower-bitint.cc (gimple_lower_bitint): For a narrowing + or same precision cast don't set SSA_NAME_VERSION in m_names only + if use_stmt is mergeable_op or fall through into the check that + use is a store or rhs1 is not mergeable or other reasons prevent + merging. + +2023-12-08 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/112901 + * vr-values.cc + (simplify_using_ranges::simplify_float_conversion_using_ranges): + Return false if rhs1 has BITINT_TYPE type with BLKmode TYPE_MODE. + +2023-12-08 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/112411 + * haifa-sched.cc (extend_h_i_d): Use 3U instead of 3 in + 3 * get_max_uid () / 2 calculation. + +2023-12-08 Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/genopts/loongarch-strings: Delete STR_ISA_BASE_LA64V110. + * config/loongarch/genopts/loongarch.opt.in: Likewise. + * config/loongarch/loongarch-cpu.cc (ISA_BASE_LA64V110_FEATURES): Delete macro. + (fill_native_cpu_config): Define a new variable hw_isa_evolution record the + extended instruction set support read from cpucfg. + * config/loongarch/loongarch-def.cc: Set evolution at initialization. + * config/loongarch/loongarch-def.h (ISA_BASE_LA64V100): Delete. + (ISA_BASE_LA64V110): Likewise. + (N_ISA_BASE_TYPES): Likewise. + (defined): Likewise. + * config/loongarch/loongarch-opts.cc: Likewise. + * config/loongarch/loongarch-opts.h (TARGET_64BIT): Likewise. + (ISA_BASE_IS_LA64V110): Likewise. + * config/loongarch/loongarch-str.h (STR_ISA_BASE_LA64V110): Likewise. + * config/loongarch/loongarch.opt: Regenerate. + +2023-12-08 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/loongarch-def.h: Remove extern "C". + (loongarch_isa_base_strings): Declare as loongarch_def_array + instead of plain array. + (loongarch_isa_ext_strings): Likewise. + (loongarch_abi_base_strings): Likewise. + (loongarch_abi_ext_strings): Likewise. + (loongarch_cmodel_strings): Likewise. + (loongarch_cpu_strings): Likewise. + (loongarch_cpu_default_isa): Likewise. + (loongarch_cpu_issue_rate): Likewise. + (loongarch_cpu_multipass_dfa_lookahead): Likewise. + (loongarch_cpu_cache): Likewise. + (loongarch_cpu_align): Likewise. + (loongarch_cpu_rtx_cost_data): Likewise. + (loongarch_isa): Add a constructor and field setter functions. + * config/loongarch/loongarch-opts.h (loongarch-defs.h): Do not + include for target libraries. + * config/loongarch/loongarch-opts.cc: Comment code that doesn't + run and causes compilation errors. + * config/loongarch/loongarch-tune.h (LOONGARCH_TUNE_H): Likewise. + (struct loongarch_rtx_cost_data): Likewise. + (struct loongarch_cache): Likewise. + (struct loongarch_align): Likewise. + * config/loongarch/t-loongarch: Compile loongarch-def.cc with the + C++ compiler. + * config/loongarch/loongarch-def-array.h: New file for a + std:array like data structure with position setter function. + * config/loongarch/loongarch-def.c: Rename to ... + * config/loongarch/loongarch-def.cc: ... here. + (loongarch_cpu_strings): Define as loongarch_def_array instead + of plain array. + (loongarch_cpu_default_isa): Likewise. + (loongarch_cpu_cache): Likewise. + (loongarch_cpu_align): Likewise. + (loongarch_cpu_rtx_cost_data): Likewise. + (loongarch_cpu_issue_rate): Likewise. + (loongarch_cpu_multipass_dfa_lookahead): Likewise. + (loongarch_isa_base_strings): Likewise. + (loongarch_isa_ext_strings): Likewise. + (loongarch_abi_base_strings): Likewise. + (loongarch_abi_ext_strings): Likewise. + (loongarch_cmodel_strings): Likewise. + (abi_minimal_isa): Likewise. + (loongarch_rtx_cost_optimize_size): Use field setter functions + instead of designated initializers. + (loongarch_rtx_cost_data): Implement default constructor. + +2023-12-08 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/112411 + * params.opt (-param=min-nondebug-insn-uid=): Add + IntegerRange(0, 1073741824). + * lra.cc (check_and_expand_insn_recog_data): Use 3U rather than 3 + in * 3 / 2 computation and if the result is smaller or equal to + index, use index + 1. + +2023-12-08 Haochen Jiang <haochen.jiang@intel.com> + + * config/i386/driver-i386.cc (host_detect_local_cpu): + Do not append "-mno-" for Xeon Phi ISAs. + * config/i386/i386-options.cc (ix86_option_override_internal): + Emit a warning for KNL/KNM targets. + * config/i386/i386.opt: Emit a warning for Xeon Phi ISAs. + +2023-12-08 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): + Remove redundant check. + +2023-12-08 Hao Liu <hliu@os.amperecomputing.com> + + PR tree-optimization/112774 + * tree-pretty-print.cc: if nonwrapping flag is set, chrec will be + printed with additional <nw> info. + * tree-scalar-evolution.cc: add record_nonwrapping_chrec and + nonwrapping_chrec_p to set and check the new flag respectively. + * tree-scalar-evolution.h: Likewise. + * tree-ssa-loop-niter.cc (idx_infer_loop_bounds, + infer_loop_bounds_from_pointer_arith, infer_loop_bounds_from_signedness, + scev_probably_wraps_p): call record_nonwrapping_chrec before + record_nonwrapping_iv, call nonwrapping_chrec_p to check the flag is + set and return false from scev_probably_wraps_p. + * tree-vect-loop.cc (vect_analyze_loop): call + free_numbers_of_iterations_estimates explicitly. + * tree-core.h: document the nothrow_flag usage in CHREC_NOWRAP + * tree.h: add CHREC_NOWRAP(NODE), base.nothrow_flag is used to + represent the nonwrapping info. + +2023-12-08 Fei Gao <gaofei@eswincomputing.com> + + * ifcvt.cc (noce_try_cond_zero_arith): New function. + (noce_emit_czero, get_base_reg): Likewise. + (noce_cond_zero_binary_op_supported): Likewise. + (noce_bbs_ok_for_cond_zero_arith): Likewise. + (noce_process_if_block): Use noce_try_cond_zero_arith. + Co-authored-by: Xiao Zeng<zengxiao@eswincomputing.com> + 2023-12-07 Juzhe-Zhong <juzhe.zhong@rivai.ai> * config/riscv/riscv-protos.h (expand_vec_series): Adapt function. diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 9e29639..98957cd 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20231208 +20231209 diff --git a/gcc/analyzer/ChangeLog b/gcc/analyzer/ChangeLog index 296acce..cf056de 100644 --- a/gcc/analyzer/ChangeLog +++ b/gcc/analyzer/ChangeLog @@ -1,3 +1,25 @@ +2023-12-08 David Malcolm <dmalcolm@redhat.com> + + * sm-taint.cc (taint_state_machine::alt_get_inherited_state): Fix + handling of TRUNC_MOD_EXPR. + +2023-12-08 David Malcolm <dmalcolm@redhat.com> + + * region-model.cc (contains_uninit_p): Only check for + svalues that the infoleak warning can handle. + +2023-12-08 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/112889 + * store.h (concrete_binding::concrete_binding): Strengthen + assertion to require size to be be positive, rather than just + non-zero. + (concrete_binding::mark_deleted): Use size rather than start bit + offset. + (concrete_binding::mark_empty): Likewise. + (concrete_binding::is_deleted): Likewise. + (concrete_binding::is_empty): Likewise. + 2023-12-07 Alexandre Oliva <oliva@adacore.com> * region-model.cc (has_nondefault_case_for_value_p): Take diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 53c8dce..3939154 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,40 @@ +2023-12-08 Patrick Palka <ppalka@redhat.com> + + PR c++/83167 + * semantics.cc (capture_decltype): Inline into its only caller ... + (finish_decltype_type): ... here. Update nearby comment to refer + to recent standard. Add FIXME. Restrict uncaptured variable type + transformation to happen only for lambdas with a by-copy + capture-default. + +2023-12-08 Jakub Jelinek <jakub@redhat.com> + + * parser.cc (cp_parser_std_attribute_spec): Return void_list_node + rather than NULL_TREE if token is neither CPP_OPEN_SQUARE nor + RID_ALIGNAS CPP_KEYWORD. + (cp_parser_std_attribute_spec_seq): For attr_spec == void_list_node + break, for attr_spec == NULL_TREE continue. + +2023-12-08 Jakub Jelinek <jakub@redhat.com> + + PR sanitizer/112727 + * cp-gimplify.cc (cp_fold): If SAVE_EXPR has been previously + folded, unshare_expr what is returned. + +2023-12-08 Patrick Palka <ppalka@redhat.com> + + PR c++/112658 + * parser.cc (cp_parser_expression_statement): If the statement + is error_mark_node, make sure we've seen_error(). + +2023-12-08 Patrick Palka <ppalka@redhat.com> + + PR c++/112658 + PR c++/94264 + * typeck.cc (cp_build_c_cast): If we're committed to a const_cast + and the result is erroneous, call build_const_cast_1 a second + time to issue errors. Use complain=tf_none instead of =false. + 2023-12-06 David Malcolm <dmalcolm@redhat.com> * cp-tree.h (cxx_print_error_function): Make diagnostic_info param diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index 5a823ee..04b7111 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,45 @@ +2023-12-08 Tobias Burnus <tobias@codesourcery.com> + + * dump-parse-tree.cc (show_omp_node): Handle EXEC_OMP_ALLOCATE + and EXEC_OMP_ALLOCATORS. + * f95-lang.cc (ATTR_ALLOC_WARN_UNUSED_RESULT_SIZE_2_NOTHROW_LIST): + Add 'ECF_LEAF | ECF_MALLOC' to existing 'ECF_NOTHROW'. + (ATTR_ALLOC_WARN_UNUSED_RESULT_SIZE_2_NOTHROW_LEAF_LIST): Define. + * gfortran.h (gfc_omp_clauses): Add contained_in_target_construct. + * invoke.texi (-fopenacc, -fopenmp): Update based on C version. + (-fopenmp-simd): New, based on C version. + (-fopenmp-allocators): New. + * lang.opt (fopenmp-allocators): Add. + * openmp.cc (resolve_omp_clauses): For allocators/allocate directive, + add target and no dynamic_allocators diagnostic and more invalid + diagnostic. + * parse.cc (decode_omp_directive): Set contains_teams_construct. + * trans-array.h (gfc_array_allocate): Update prototype. + (gfc_conv_descriptor_version): New prototype. + * trans-decl.cc (gfc_init_default_dt): Fix comment. + * trans-array.cc (gfc_conv_descriptor_version): New. + (gfc_array_allocate): Support GOMP_alloc allocation. + (gfc_alloc_allocatable_for_assignment, structure_alloc_comps): + Handle GOMP_free/omp_realloc as needed. + * trans-expr.cc (gfc_conv_procedure_call): Likewise. + (alloc_scalar_allocatable_for_assignment): Likewise. + * trans-intrinsic.cc (conv_intrinsic_move_alloc): Likewise. + * trans-openmp.cc (gfc_trans_omp_allocators, + gfc_trans_omp_directive): Handle allocators/allocate directive. + (gfc_omp_call_add_alloc, gfc_omp_call_is_alloc): New. + * trans-stmt.h (gfc_trans_allocate): Update prototype. + * trans-stmt.cc (gfc_trans_allocate): Support GOMP_alloc. + * trans-types.cc (gfc_get_dtype_rank_type): Set version field. + * trans.cc (gfc_allocate_using_malloc, gfc_allocate_allocatable): + Update to handle GOMP_alloc. + (gfc_deallocate_with_status, gfc_deallocate_scalar_with_status): + Handle GOMP_free. + (trans_code): Update call. + * trans.h (gfc_allocate_allocatable, gfc_allocate_using_malloc): + Update prototype. + (gfc_omp_call_add_alloc, gfc_omp_call_is_alloc): New prototype. + * types.def (BT_FN_PTR_PTR_SIZE_PTRMODE_PTRMODE): New. + 2023-12-06 David Malcolm <dmalcolm@redhat.com> * error.cc (gfc_diagnostic_starter): Make diagnostic_info param diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index ea17860..61cb3fb 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,381 @@ +2023-12-08 Patrick Palka <ppalka@redhat.com> + + PR c++/83167 + * g++.dg/cpp0x/lambda/lambda-decltype4.C: New test. + +2023-12-08 David Malcolm <dmalcolm@redhat.com> + + * c-c++-common/analyzer/taint-modulus-1.c: New test. + +2023-12-08 David Malcolm <dmalcolm@redhat.com> + + * gcc.dg/plugin/infoleak-uninit-size-1.c: New test. + * gcc.dg/plugin/infoleak-uninit-size-2.c: New test. + * gcc.dg/plugin/plugin.exp: Add the new tests. + +2023-12-08 Vladimir N. Makarov <vmakarov@redhat.com> + + PR rtl-optimization/112875 + * gcc.target/i386/pr112875.c: New test. + +2023-12-08 Jakub Jelinek <jakub@redhat.com> + + * g++.dg/cpp0x/gen-attrs-79.C: New test. + +2023-12-08 Jakub Jelinek <jakub@redhat.com> + + PR sanitizer/112727 + * c-c++-common/ubsan/pr112727.c: New test. + +2023-12-08 Marek Polacek <polacek@redhat.com> + + PR c++/88848 + * g++.dg/inherit/multiple2.C: New test. + +2023-12-08 Patrick Palka <ppalka@redhat.com> + + PR c++/112658 + PR c++/94264 + * g++.dg/cpp0x/initlist-array20.C: New test. + +2023-12-08 Robin Dapp <rdapp@ventanamicro.com> + + * gcc.target/riscv/rvv/autovec/builtin/strcmp-run.c: New test. + * gcc.target/riscv/rvv/autovec/builtin/strcmp.c: New test. + * gcc.target/riscv/rvv/autovec/builtin/strncmp-run.c: New test. + * gcc.target/riscv/rvv/autovec/builtin/strncmp.c: New test. + +2023-12-08 Robin Dapp <rdapp@ventanamicro.com> + + * gcc.target/riscv/rvv/autovec/builtin/strlen-run.c: New test. + * gcc.target/riscv/rvv/autovec/builtin/strlen.c: New test. + +2023-12-08 Richard Sandiford <richard.sandiford@arm.com> + + * gcc.target/aarch64/sme/strided_2.c: New test. + +2023-12-08 Richard Earnshaw <rearnsha@arm.com> + + Revert: + 2023-12-08 Ezra Sitorus <ezra.sitorus@arm.com> + + * gcc.target/arm/simd/vld1q_base_xN_1.c: Add new test. + * gcc.target/arm/simd/vld1q_bf16_xN_1.c: Add new test. + * gcc.target/arm/simd/vld1q_fp16_xN_1.c: Add new test. + * gcc.target/arm/simd/vld1q_p64_xN_1.c: Add new test. + +2023-12-08 Richard Earnshaw <rearnsha@arm.com> + + Revert: + 2023-12-08 Ezra Sitorus <ezra.sitorus@arm.com> + + * gcc.target/arm/simd/vld1q_base_xN_1.c: Add new tests. + * gcc.target/arm/simd/vld1q_bf16_xN_1.c: Add new tests. + * gcc.target/arm/simd/vld1q_fp16_xN_1.c: Add new tests. + * gcc.target/arm/simd/vld1q_p64_xN_1.c: Add new tests. + +2023-12-08 Richard Earnshaw <rearnsha@arm.com> + + Revert: + 2023-12-08 Ezra Sitorus <ezra.sitorus@arm.com> + + * gcc.target/arm/simd/vld1q_base_xN_1.c: Add new tests. + * gcc.target/arm/simd/vld1q_bf16_xN_1.c: Add new tests. + * gcc.target/arm/simd/vld1q_fp16_xN_1.c: Add new tests. + * gcc.target/arm/simd/vld1q_p64_xN_1.c: Add new tests. + +2023-12-08 Richard Earnshaw <rearnsha@arm.com> + + Revert: + 2023-12-08 Ezra Sitorus <ezra.sitorus@arm.com> + + * gcc.target/arm/simd/vst1_base_xN_1.c: Add new tests. + * gcc.target/arm/simd/vst1_bf16_xN_1.c: Add new tests. + * gcc.target/arm/simd/vst1_fp16_xN_1.c: Add new tests. + * gcc.target/arm/simd/vst1_p64_xN_1.c: Add new tests. + +2023-12-08 Richard Earnshaw <rearnsha@arm.com> + + Revert: + 2023-12-08 Ezra Sitorus <ezra.sitorus@arm.com> + + * gcc.target/arm/simd/vst1_base_xN_1.c: Add new test. + * gcc.target/arm/simd/vst1_bf16_xN_1.c: Add new test. + * gcc.target/arm/simd/vst1_fp16_xN_1.c: Add new test. + * gcc.target/arm/simd/vst1_p64_xN_1.c: Add new test. + +2023-12-08 Richard Earnshaw <rearnsha@arm.com> + + Revert: + 2023-12-08 Ezra Sitorus <ezra.sitorus@arm.com> + + * gcc.target/arm/simd/vst1_base_xN_1.c: Add new test. + * gcc.target/arm/simd/vst1_bf16_xN_1.c: Add new test. + * gcc.target/arm/simd/vst1_fp16_xN_1.c: Add new test. + * gcc.target/arm/simd/vst1_p64_xN_1.c: Add new test. + +2023-12-08 Richard Earnshaw <rearnsha@arm.com> + + Revert: + 2023-12-08 Ezra Sitorus <ezra.sitorus@arm.com> + + * gcc.target/arm/simd/vst1q_base_xN_1.c: Add new tests. + * gcc.target/arm/simd/vst1q_bf16_xN_1.c: Add new tests. + * gcc.target/arm/simd/vst1q_fp16_xN_1.c: Add new tests. + * gcc.target/arm/simd/vst1q_p64_xN_1.c: Add new tests. + +2023-12-08 Richard Earnshaw <rearnsha@arm.com> + + Revert: + 2023-12-08 Ezra Sitorus <ezra.sitorus@arm.com> + + * gcc.target/arm/simd/vst1q_base_xN_1.c: Add new tests. + * gcc.target/arm/simd/vst1q_bf16_xN_1.c: Add new tests. + * gcc.target/arm/simd/vst1q_fp16_xN_1.c: Add new tests. + * gcc.target/arm/simd/vst1q_p64_xN_1.c: Add new tests. + +2023-12-08 Richard Earnshaw <rearnsha@arm.com> + + Revert: + 2023-12-08 Ezra Sitorus <ezra.sitorus@arm.com> + + * gcc.target/arm/simd/vst1q_base_xN_1.c: Add new tests. + * gcc.target/arm/simd/vst1q_bf16_xN_1.c: Add new tests. + * gcc.target/arm/simd/vst1q_fp16_xN_1.c: Add new tests. + * gcc.target/arm/simd/vst1q_p64_xN_1.c: Add new tests. + +2023-12-08 Richard Earnshaw <rearnsha@arm.com> + + Revert: + 2023-12-08 Ezra Sitorus <ezra.sitorus@arm.com> + + * gcc.target/arm/simd/vld1_base_xN_1.c: Add new tests. + * gcc.target/arm/simd/vld1_bf16_xN_1.c: Add new tests. + * gcc.target/arm/simd/vld1_fp16_xN_1.c: Add new tests. + * gcc.target/arm/simd/vld1_p64_xN_1.c: Add new tests. + +2023-12-08 Richard Earnshaw <rearnsha@arm.com> + + Revert: + 2023-12-08 Ezra Sitorus <ezra.sitorus@arm.com> + + * gcc.target/arm/simd/vld1_base_xN_1.c: Add new tests. + * gcc.target/arm/simd/vld1_bf16_xN_1.c: Add new tests. + * gcc.target/arm/simd/vld1_fp16_xN_1.c: Add new tests. + * gcc.target/arm/simd/vld1_p64_xN_1.c: Add new tests. + +2023-12-08 Richard Earnshaw <rearnsha@arm.com> + + Revert: + 2023-12-08 Ezra Sitorus <ezra.sitorus@arm.com> + + * gcc.target/arm/simd/vld1_base_xN_1.c: Add new tests. + * gcc.target/arm/simd/vld1_bf16_xN_1.c: Add new tests. + * gcc.target/arm/simd/vld1_fp16_xN_1.c: Add new tests. + * gcc.target/arm/simd/vld1_p64_xN_1.c: Add new tests. + +2023-12-08 Tobias Burnus <tobias@codesourcery.com> + + * gfortran.dg/gomp/allocate-14.f90: Add coarray and + not-listed tests. + * gfortran.dg/gomp/allocate-5.f90: Remove sorry dg-message. + * gfortran.dg/bind_c_array_params_2.f90: Update expected + dump for dtype '.version=0'. + * gfortran.dg/gomp/allocate-16.f90: New test. + * gfortran.dg/gomp/allocators-3.f90: New test. + * gfortran.dg/gomp/allocators-4.f90: New test. + +2023-12-08 Richard Biener <rguenther@suse.de> + + PR tree-optimization/112909 + * gcc.dg/uninit-pr112909.c: New testcase. + +2023-12-08 Marc Poulhiès <poulhies@adacore.com> + + Revert: + 2023-12-07 Marc Poulhiès <poulhies@adacore.com> + + * gcc.dg/vect/vect-ifcvt-18.c: Add dep on avx_runtime. + * gcc.dg/vect/vect-simd-clone-16f.c: Likewise. + * gcc.dg/vect/vect-simd-clone-18f.c: Likewise. + +2023-12-08 Jiahao Xu <xujiahao@loongson.cn> + + * gcc.target/loongarch/pr112476-3.c: New test. + * gcc.target/loongarch/pr112476-4.c: New test. + +2023-12-08 Jiahao Xu <xujiahao@loongson.cn> + + PR target/112611 + * gcc.target/loongarch/vector/lasx/lasx-xvshuf_b.c: Sure index less than 64. + * gcc.target/loongarch/vector/lsx/lsx-vshuf.c: Ditto. + +2023-12-08 Jiahao Xu <xujiahao@loongson.cn> + + * gcc.target/loongarch/divf.c: New test. + * gcc.target/loongarch/recip-divf.c: New test. + * gcc.target/loongarch/recip-sqrtf.c: New test. + * gcc.target/loongarch/sqrtf.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-divf.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-recip-divf.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-recip-sqrtf.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-recip.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-sqrtf.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-divf.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-recip-divf.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-recip-sqrtf.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-recip.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-sqrtf.c: New test. + +2023-12-08 Jiahao Xu <xujiahao@loongson.cn> + + * gcc.target/loongarch/vector/lasx/lasx-rsqrt.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-rsqrt.c: New test. + +2023-12-08 Jiahao Xu <xujiahao@loongson.cn> + + * gcc.target/loongarch/larch-frecipe-builtin.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-frecipe-builtin.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-frecipe-builtin.c: New test. + +2023-12-08 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c: New test. + +2023-12-08 Jiahao Xu <xujiahao@loongson.cn> + + * gcc.target/loongarch/vector/lasx/lasx-xorsign-run.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xorsign.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-xorsign-run.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-xorsign.c: New test. + * gcc.target/loongarch/xorsign-run.c: New test. + * gcc.target/loongarch/xorsign.c: New test. + +2023-12-08 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/112902 + * gcc.dg/bitint-52.c: New test. + +2023-12-08 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/112901 + * gcc.dg/bitint-51.c: New test. + +2023-12-08 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/112411 + * gcc.dg/params/blocksort-part.c: Add dg-skip-if for + --param min-nondebug-insn-uid=1073741824. + +2023-12-08 Haochen Jiang <haochen.jiang@intel.com> + + * g++.dg/other/i386-2.C: Adjust testcases. + * g++.dg/other/i386-3.C: Ditto. + * g++.dg/pr80481.C: Ditto. + * gcc.dg/pr71279.c: Ditto. + * gcc.target/i386/avx5124fmadd-v4fmaddps-1.c: Ditto. + * gcc.target/i386/avx5124fmadd-v4fmaddps-2.c: Ditto. + * gcc.target/i386/avx5124fmadd-v4fmaddss-1.c: Ditto. + * gcc.target/i386/avx5124fmadd-v4fnmaddps-1.c: Ditto. + * gcc.target/i386/avx5124fmadd-v4fnmaddps-2.c: Ditto. + * gcc.target/i386/avx5124fmadd-v4fnmaddss-1.c: Ditto. + * gcc.target/i386/avx5124vnniw-vp4dpwssd-1.c: Ditto. + * gcc.target/i386/avx5124vnniw-vp4dpwssd-2.c: Ditto. + * gcc.target/i386/avx5124vnniw-vp4dpwssds-1.c: Ditto. + * gcc.target/i386/avx5124vnniw-vp4dpwssds-2.c: Ditto. + * gcc.target/i386/avx512er-vexp2pd-1.c: Ditto. + * gcc.target/i386/avx512er-vexp2pd-2.c: Ditto. + * gcc.target/i386/avx512er-vexp2ps-1.c: Ditto. + * gcc.target/i386/avx512er-vexp2ps-2.c: Ditto. + * gcc.target/i386/avx512er-vrcp28pd-1.c: Ditto. + * gcc.target/i386/avx512er-vrcp28pd-2.c: Ditto. + * gcc.target/i386/avx512er-vrcp28ps-1.c: Ditto. + * gcc.target/i386/avx512er-vrcp28ps-2.c: Ditto. + * gcc.target/i386/avx512er-vrcp28ps-3.c: Ditto. + * gcc.target/i386/avx512er-vrcp28ps-4.c: Ditto. + * gcc.target/i386/avx512er-vrcp28sd-1.c: Ditto. + * gcc.target/i386/avx512er-vrcp28sd-2.c: Ditto. + * gcc.target/i386/avx512er-vrcp28ss-1.c: Ditto. + * gcc.target/i386/avx512er-vrcp28ss-2.c: Ditto. + * gcc.target/i386/avx512er-vrsqrt28pd-1.c: Ditto. + * gcc.target/i386/avx512er-vrsqrt28pd-2.c: Ditto. + * gcc.target/i386/avx512er-vrsqrt28ps-1.c: Ditto. + * gcc.target/i386/avx512er-vrsqrt28ps-2.c: Ditto. + * gcc.target/i386/avx512er-vrsqrt28ps-3.c: Ditto. + * gcc.target/i386/avx512er-vrsqrt28ps-4.c: Ditto. + * gcc.target/i386/avx512er-vrsqrt28ps-5.c: Ditto. + * gcc.target/i386/avx512er-vrsqrt28ps-6.c: Ditto. + * gcc.target/i386/avx512er-vrsqrt28sd-1.c: Ditto. + * gcc.target/i386/avx512er-vrsqrt28sd-2.c: Ditto. + * gcc.target/i386/avx512er-vrsqrt28ss-1.c: Ditto. + * gcc.target/i386/avx512er-vrsqrt28ss-2.c: Ditto. + * gcc.target/i386/avx512f-gather-1.c: Ditto. + * gcc.target/i386/avx512f-gather-2.c: Ditto. + * gcc.target/i386/avx512f-gather-3.c: Ditto. + * gcc.target/i386/avx512f-gather-4.c: Ditto. + * gcc.target/i386/avx512f-gather-5.c: Ditto. + * gcc.target/i386/avx512f-i32gatherd512-1.c: Ditto. + * gcc.target/i386/avx512f-i32gatherd512-2.c: Ditto. + * gcc.target/i386/avx512f-i32gatherpd512-1.c: Ditto. + * gcc.target/i386/avx512f-i32gatherpd512-2.c: Ditto. + * gcc.target/i386/avx512f-i32gatherps512-1.c: Ditto. + * gcc.target/i386/avx512f-vect-perm-1.c: Ditto. + * gcc.target/i386/avx512f-vect-perm-2.c: Ditto. + * gcc.target/i386/avx512pf-vgatherpf0dpd-1.c: Ditto. + * gcc.target/i386/avx512pf-vgatherpf0dps-1.c: Ditto. + * gcc.target/i386/avx512pf-vgatherpf0qpd-1.c: Ditto. + * gcc.target/i386/avx512pf-vgatherpf0qps-1.c: Ditto. + * gcc.target/i386/avx512pf-vgatherpf1dpd-1.c: Ditto. + * gcc.target/i386/avx512pf-vgatherpf1dps-1.c: Ditto. + * gcc.target/i386/avx512pf-vgatherpf1qpd-1.c: Ditto. + * gcc.target/i386/avx512pf-vgatherpf1qps-1.c: Ditto. + * gcc.target/i386/avx512pf-vscatterpf0dpd-1.c: Ditto. + * gcc.target/i386/avx512pf-vscatterpf0dps-1.c: Ditto. + * gcc.target/i386/avx512pf-vscatterpf0qpd-1.c: Ditto. + * gcc.target/i386/avx512pf-vscatterpf0qps-1.c: Ditto. + * gcc.target/i386/avx512pf-vscatterpf1dpd-1.c: Ditto. + * gcc.target/i386/avx512pf-vscatterpf1dps-1.c: Ditto. + * gcc.target/i386/avx512pf-vscatterpf1qpd-1.c: Ditto. + * gcc.target/i386/avx512pf-vscatterpf1qps-1.c: Ditto. + * gcc.target/i386/funcspec-56.inc: Ditto. + * gcc.target/i386/pr103404.c: Ditto. + * gcc.target/i386/pr104448.c: Ditto. + * gcc.target/i386/pr107934.c: Ditto. + * gcc.target/i386/pr64387.c: Ditto. + * gcc.target/i386/pr70728.c: Ditto. + * gcc.target/i386/pr71346.c: Ditto. + * gcc.target/i386/pr82941-2.c: Ditto. + * gcc.target/i386/pr82942-1.c: Ditto. + * gcc.target/i386/pr82942-2.c: Ditto. + * gcc.target/i386/pr82990-1.c: Ditto. + * gcc.target/i386/pr82990-3.c: Ditto. + * gcc.target/i386/pr82990-4.c: Ditto. + * gcc.target/i386/pr82990-6.c: Ditto. + * gcc.target/i386/pr88713-3.c: Ditto. + * gcc.target/i386/pr89523-5.c: Ditto. + * gcc.target/i386/pr89523-6.c: Ditto. + * gcc.target/i386/pr91033.c: Ditto. + * gcc.target/i386/pr94561.c: Ditto. + * gcc.target/i386/prefetchwt1-1.c: Ditto. + * gcc.target/i386/sse-12.c: Ditto. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-14.c: Ditto. + * gcc.target/i386/sse-26.c: Ditto. + * gcc.target/i386/pr69471-3.c: Removed. + +2023-12-08 Hao Liu <hliu@os.amperecomputing.com> + + * gcc.dg/tree-ssa/scev-16.c: New test. + +2023-12-08 Fei Gao <gaofei@eswincomputing.com> + + * gcc.target/riscv/zicond_ifcvt_opt.c: New file. + +2023-12-08 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/112889 + * c-c++-common/analyzer/ice-pr112889.c: New test. + 2023-12-07 Juzhe-Zhong <juzhe.zhong@rivai.ai> * gcc.target/riscv/rvv/autovec/slp-interleave-1.c: New test. diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog index 8dc9785..279d718 100644 --- a/libgcc/ChangeLog +++ b/libgcc/ChangeLog @@ -1,3 +1,41 @@ +2023-12-08 Florian Weimer <fweimer@redhat.com> + + * libgcov-interface.c (__gcov_fork): Use __builtin_fork instead + of fork. + +2023-12-08 Szabolcs Nagy <szabolcs.nagy@arm.com> + + * config.in: Regenerate. + +2023-12-08 Szabolcs Nagy <szabolcs.nagy@arm.com> + + * config/aarch64/__arm_za_disable.S: Add hidden alias. + * config/aarch64/aarch64-unwind.h: Reset the SME state before + EH return via the _Unwind_Frames_Extra hook. + +2023-12-08 Szabolcs Nagy <szabolcs.nagy@arm.com> + + * config/aarch64/t-aarch64: Add sources to the build. + * config/aarch64/__aarch64_have_sme.c: New file. + * config/aarch64/__arm_sme_state.S: New file. + * config/aarch64/__arm_tpidr2_restore.S: New file. + * config/aarch64/__arm_tpidr2_save.S: New file. + * config/aarch64/__arm_za_disable.S: New file. + * config/aarch64/aarch64-asm.h: New file. + * config/aarch64/libgcc-sme.ver: New file. + +2023-12-08 Szabolcs Nagy <szabolcs.nagy@arm.com> + + * config.in: Undef HAVE___GETAUXVAL. + * configure: Regenerate. + * configure.ac: Check for __getauxval. + +2023-12-08 Szabolcs Nagy <szabolcs.nagy@arm.com> + + * config.in: Undef HAVE_AS_VARIANT_PCS. + * configure: Regenerate. + * configure.ac: Check for .variant_pcs. + 2023-12-07 Alexandre Oliva <oliva@adacore.com> * configure.ac: Check for strub support. diff --git a/libgomp/ChangeLog b/libgomp/ChangeLog index 9e74537..77280e0 100644 --- a/libgomp/ChangeLog +++ b/libgomp/ChangeLog @@ -1,3 +1,25 @@ +2023-12-08 Tobias Burnus <tobias@codesourcery.com> + + * allocator.c (struct fort_alloc_splay_tree_key_s, + fort_alloc_splay_compare, GOMP_add_alloc, GOMP_is_alloc): New. + * libgomp.h: Define splay_tree_static for 'reverse' splay tree. + * libgomp.map (GOMP_5.1.2): New; add GOMP_add_alloc and + GOMP_is_alloc; move GOMP_target_map_indirect_ptr from ... + (GOMP_5.1.1): ... here. + * libgomp.texi (Impl. Status, Memory management): Update for + allocators/allocate directives. + * splay-tree.c: Handle splay_tree_static define to declare all + functions as static. + (splay_tree_lookup_node): New. + * splay-tree.h: Handle splay_tree_decl_only define. + (splay_tree_lookup_node): New prototype. + * target.c: Define splay_tree_static for 'reverse'. + * testsuite/libgomp.fortran/allocators-1.f90: New test. + * testsuite/libgomp.fortran/allocators-2.f90: New test. + * testsuite/libgomp.fortran/allocators-3.f90: New test. + * testsuite/libgomp.fortran/allocators-4.f90: New test. + * testsuite/libgomp.fortran/allocators-5.f90: New test. + 2023-12-06 Andrew Stubbs <ams@codesourcery.com> * config/gcn/libgomp-gcn.h (TEAM_ARENA_START): Move to here. |