diff options
| -rw-r--r-- | gcc/ChangeLog | 32 | ||||
| -rw-r--r-- | gcc/config/sparc/constraints.md | 47 | ||||
| -rw-r--r-- | gcc/config/sparc/sparc-protos.h | 2 | ||||
| -rw-r--r-- | gcc/config/sparc/sparc.c | 39 | ||||
| -rw-r--r-- | gcc/config/sparc/sparc.h | 25 | ||||
| -rw-r--r-- | gcc/config/sparc/sparc.md | 36 |
6 files changed, 107 insertions, 74 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b6527de..8ffb990 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,35 @@ +2015-09-21 David S. Miller <davem@davemloft.net> + + PR/67622 + Revert: + 2015-09-11 David S. Miller <davem@davemloft.net> + + * config/sparc/constraints.md: Make "U" constraint a real register + constraint. + * config/sparc/sparc.c (TARGET_LRA_P): Define. + (D_MODES, DF_MODES): Add missing cast. + (TF_MODES, TF_MODES_NO_S): Include T_MODE. + (OF_MODES, OF_MODES_NO_S): Include O_MODE. + (sparc_register_move_cost): Decrease Niagara/UltrsSPARC memory + cost to 8. + * config/sparc/sparc.h (PROMOTE_MODE): Define. + * config/sparc/sparc.md (*movsi_lo_sum, *movsi_high): Do not + provide these insn when flag_pic. + + 2015-09-17 David S. Miller <davem@davemloft.net> + + * config/sparc/sparc-protos.h (sparc_secondary_memory_needed): + Declare. + * config/sparc/sparc.c (sparc_secondary_memory_needed): New + function. + * config/sparc/sparc.h (SECONDARY_MEMORY_NEEDED): Use it. + (HARD_REGNO_CALLER_SAVE_MODE): Define. + * config/sparc/sparc.md (sethi_di_medlow, losum_di_medlow, seth44) + (setm44, setl44, sethh, setlm, sethm, setlo, embmedany_sethi) + (embmedany_losum, embmedany_brsum, embmedany_textuhi) + (embmedany_texthi, embmedany_textulo, embmedany_textlo): Do not + provide when flag_pic. + 2015-09-21 Jeff Law <law@redhat.com> * config/h8300/h8300.md (andsi3_ashift_n_lower): Avoid undefined diff --git a/gcc/config/sparc/constraints.md b/gcc/config/sparc/constraints.md index 7a18879..e12efa1 100644 --- a/gcc/config/sparc/constraints.md +++ b/gcc/config/sparc/constraints.md @@ -44,8 +44,6 @@ (define_register_constraint "h" "(TARGET_V9 && TARGET_V8PLUS ? I64_REGS : NO_REGS)" "64-bit global or out register in V8+ mode") -(define_register_constraint "U" "(TARGET_ARCH32 ? GENERAL_REGS : NO_REGS)") - ;; Floating-point constant constraints (define_constraint "G" @@ -137,6 +135,51 @@ (match_code "mem") (match_test "memory_ok_for_ldd (op)"))) +;; This awkward register constraint is necessary because it is not +;; possible to express the "must be even numbered register" condition +;; using register classes. The problem is that membership in a +;; register class requires that all registers of a multi-regno +;; register be included in the set. It is add_to_hard_reg_set +;; and in_hard_reg_set_p which populate and test regsets with these +;; semantics. +;; +;; So this means that we would have to put both the even and odd +;; register into the register class, which would not restrict things +;; at all. +;; +;; Using a combination of GENERAL_REGS and HARD_REGNO_MODE_OK is not a +;; full solution either. In fact, even though IRA uses the macro +;; HARD_REGNO_MODE_OK to calculate which registers are prohibited from +;; use in certain modes, it still can allocate an odd hard register +;; for DImode values. This is due to how IRA populates the table +;; ira_useful_class_mode_regs[][]. It suffers from the same problem +;; as using a register class to describe this restriction. Namely, it +;; sets both the odd and even part of an even register pair in the +;; regset. Therefore IRA can and will allocate odd registers for +;; DImode values on 32-bit. +;; +;; There are legitimate cases where DImode values can end up in odd +;; hard registers, the most notable example is argument passing. +;; +;; What saves us is reload and the DImode splitters. Both are +;; necessary. The odd register splitters cannot match if, for +;; example, we have a non-offsetable MEM. Reload will notice this +;; case and reload the address into a single hard register. +;; +;; The real downfall of this awkward register constraint is that it does +;; not evaluate to a true register class like a bonafide use of +;; define_register_constraint would. This currently means that we cannot +;; use LRA on Sparc, since the constraint processing of LRA really depends +;; upon whether an extra constraint is for registers or not. It uses +;; reg_class_for_constraint, and checks it against NO_REGS. +(define_constraint "U" + "Pseudo-register or hard even-numbered integer register" + (and (match_test "TARGET_ARCH32") + (match_code "reg") + (ior (match_test "REGNO (op) < FIRST_PSEUDO_REGISTER") + (not (match_test "reload_in_progress && reg_renumber [REGNO (op)] < 0"))) + (match_test "register_ok_for_ldd (op)"))) + ;; Equivalent to 'T' but available in 64-bit mode (define_memory_constraint "W" "Memory reference for 'e' constraint floating-point register" diff --git a/gcc/config/sparc/sparc-protos.h b/gcc/config/sparc/sparc-protos.h index 18192fd..1431437 100644 --- a/gcc/config/sparc/sparc-protos.h +++ b/gcc/config/sparc/sparc-protos.h @@ -62,8 +62,6 @@ extern bool constant_address_p (rtx); extern bool legitimate_pic_operand_p (rtx); extern rtx sparc_legitimize_reload_address (rtx, machine_mode, int, int, int, int *win); -extern bool sparc_secondary_memory_needed (enum reg_class, enum reg_class, - machine_mode); extern void load_got_register (void); extern void sparc_emit_call_insn (rtx, rtx); extern void sparc_defer_case_vector (rtx, rtx, int); diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index f4ad68d..ed8a166 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -808,9 +808,6 @@ char sparc_hard_reg_printed[8]; #undef TARGET_CAN_ELIMINATE #define TARGET_CAN_ELIMINATE sparc_can_eliminate -#undef TARGET_LRA_P -#define TARGET_LRA_P hook_bool_void_true - #undef TARGET_PREFERRED_RELOAD_CLASS #define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class @@ -4694,7 +4691,7 @@ enum sparc_mode_class { ((1 << (int) H_MODE) | (1 << (int) S_MODE) | (1 << (int) SF_MODE)) /* Modes for double-word and smaller quantities. */ -#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << (int) DF_MODE)) +#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE)) /* Modes for quad-word and smaller quantities. */ #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE)) @@ -4706,24 +4703,22 @@ enum sparc_mode_class { #define SF_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE)) /* Modes for double-float and smaller quantities. */ -#define DF_MODES (SF_MODES | (1 << (int) D_MODE) | (1 << (int) DF_MODE)) +#define DF_MODES (SF_MODES | (1 << (int) D_MODE) | (1 << DF_MODE)) /* Modes for quad-float and smaller quantities. */ -#define TF_MODES (DF_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE)) +#define TF_MODES (DF_MODES | (1 << (int) TF_MODE)) /* Modes for quad-float pairs and smaller quantities. */ -#define OF_MODES (TF_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE)) +#define OF_MODES (TF_MODES | (1 << (int) OF_MODE)) /* Modes for double-float only quantities. */ #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE)) /* Modes for quad-float and double-float only quantities. */ -#define TF_MODES_NO_S \ - (DF_MODES_NO_S | (1 << (int) T_MODE) | (1 << (int) TF_MODE)) +#define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE)) /* Modes for quad-float pairs and double-float only quantities. */ -#define OF_MODES_NO_S \ - (TF_MODES_NO_S | (1 << (int) O_MODE) | (1 << (int) OF_MODE)) +#define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE)) /* Modes for condition codes. */ #define CC_MODES (1 << (int) CC_MODE) @@ -11193,7 +11188,7 @@ sparc_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, || sparc_cpu == PROCESSOR_NIAGARA2 || sparc_cpu == PROCESSOR_NIAGARA3 || sparc_cpu == PROCESSOR_NIAGARA4) - return 8; + return 12; return 6; } @@ -12283,26 +12278,6 @@ sparc_expand_vector_init (rtx target, rtx vals) emit_move_insn (target, mem); } -bool sparc_secondary_memory_needed (enum reg_class class1, enum reg_class class2, - machine_mode mode) -{ - if (FP_REG_CLASS_P (class1) != FP_REG_CLASS_P (class2)) - { - if (! TARGET_VIS3 - || GET_MODE_SIZE (mode) > 8 - || GET_MODE_SIZE (mode) < 4) - return true; - return false; - } - - if (GET_MODE_SIZE (mode) == 4 - && ((class1 == FP_REGS && class2 == EXTRA_FP_REGS) - || (class1 == EXTRA_FP_REGS && class2 == FP_REGS))) - return true; - - return false; -} - /* Implement TARGET_SECONDARY_RELOAD. */ static reg_class_t diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index 1f26232..2cbe0d9 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -452,17 +452,6 @@ extern enum cmodel sparc_cmodel; /* target machine storage layout */ -/* Define this macro if it is advisable to hold scalars in registers - in a wider mode than that declared by the program. In such cases, - the value is constrained to be within the bounds of the declared - type, but kept valid in the wider mode. The signedness of the - extension may differ from that of the type. */ - -#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ - if (GET_MODE_CLASS (MODE) == MODE_INT \ - && GET_MODE_SIZE (MODE) < (TARGET_ARCH64 ? 8 : 4)) \ - (MODE) = TARGET_ARCH64 ? DImode : SImode; - /* Define this if most significant bit is lowest numbered in instructions that operate on numbered bit-fields. */ #define BITS_BIG_ENDIAN 1 @@ -747,12 +736,6 @@ extern int sparc_mode_class[]; register window instruction in the prologue. */ #define HARD_REGNO_RENAME_OK(FROM, TO) ((FROM) != 1) -/* Select a register mode required for caller save of hard regno REGNO. */ -#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ - (((MODE) == VOIDmode) ? \ - choose_hard_reg_mode ((REGNO), (NREGS), false) : \ - (MODE)) - #define MODES_TIEABLE_P(MODE1, MODE2) sparc_modes_tieable_p (MODE1, MODE2) /* Specify the registers used for certain standard purposes. @@ -1050,10 +1033,12 @@ extern char leaf_reg_remap[]; (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode))) /* On SPARC when not VIS3 it is not possible to directly move data - between GENERAL_REGS and FP_REGS. We also cannot move 4-byte values - between FP_REGS and EXTRA_FP_REGS. */ + between GENERAL_REGS and FP_REGS. */ #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ - sparc_secondary_memory_needed (CLASS1, CLASS2, MODE) + ((FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2)) \ + && (! TARGET_VIS3 \ + || GET_MODE_SIZE (MODE) > 8 \ + || GET_MODE_SIZE (MODE) < 4)) /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9 because the movsi and movsf patterns don't handle r/f moves. diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index e6a1831..5b9f051 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -1467,13 +1467,13 @@ [(set (match_operand:SI 0 "register_operand" "=r") (lo_sum:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "immediate_operand" "in")))] - "! flag_pic" + "" "or\t%1, %%lo(%a2), %0") (define_insn "*movsi_high" [(set (match_operand:SI 0 "register_operand" "=r") (high:SI (match_operand:SI 1 "immediate_operand" "in")))] - "! flag_pic" + "" "sethi\t%%hi(%a1), %0") ;; The next two patterns must wrap the SYMBOL_REF in an UNSPEC @@ -1745,105 +1745,105 @@ (define_insn "*sethi_di_medlow" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (match_operand:DI 1 "symbolic_operand" "")))] - "TARGET_CM_MEDLOW && !flag_pic" + "TARGET_CM_MEDLOW && check_pic (1)" "sethi\t%%hi(%a1), %0") (define_insn "*losum_di_medlow" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "symbolic_operand" "")))] - "TARGET_CM_MEDLOW && !flag_pic" + "TARGET_CM_MEDLOW" "or\t%1, %%lo(%a2), %0") (define_insn "seth44" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETH44)))] - "TARGET_CM_MEDMID && !flag_pic" + "TARGET_CM_MEDMID" "sethi\t%%h44(%a1), %0") (define_insn "setm44" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] UNSPEC_SETM44)))] - "TARGET_CM_MEDMID && !flag_pic" + "TARGET_CM_MEDMID" "or\t%1, %%m44(%a2), %0") (define_insn "setl44" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "symbolic_operand" "")))] - "TARGET_CM_MEDMID && !flag_pic" + "TARGET_CM_MEDMID" "or\t%1, %%l44(%a2), %0") (define_insn "sethh" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETHH)))] - "TARGET_CM_MEDANY && !flag_pic" + "TARGET_CM_MEDANY" "sethi\t%%hh(%a1), %0") (define_insn "setlm" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETLM)))] - "TARGET_CM_MEDANY && !flag_pic" + "TARGET_CM_MEDANY" "sethi\t%%lm(%a1), %0") (define_insn "sethm" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] UNSPEC_EMB_SETHM)))] - "TARGET_CM_MEDANY && !flag_pic" + "TARGET_CM_MEDANY" "or\t%1, %%hm(%a2), %0") (define_insn "setlo" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "symbolic_operand" "")))] - "TARGET_CM_MEDANY && !flag_pic" + "TARGET_CM_MEDANY" "or\t%1, %%lo(%a2), %0") (define_insn "embmedany_sethi" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (unspec:DI [(match_operand:DI 1 "data_segment_operand" "")] UNSPEC_EMB_HISUM)))] - "TARGET_CM_EMBMEDANY && !flag_pic" + "TARGET_CM_EMBMEDANY && check_pic (1)" "sethi\t%%hi(%a1), %0") (define_insn "embmedany_losum" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "data_segment_operand" "")))] - "TARGET_CM_EMBMEDANY && !flag_pic" + "TARGET_CM_EMBMEDANY" "add\t%1, %%lo(%a2), %0") (define_insn "embmedany_brsum" [(set (match_operand:DI 0 "register_operand" "=r") (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_EMB_HISUM))] - "TARGET_CM_EMBMEDANY && !flag_pic" + "TARGET_CM_EMBMEDANY" "add\t%1, %_, %0") (define_insn "embmedany_textuhi" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] UNSPEC_EMB_TEXTUHI)))] - "TARGET_CM_EMBMEDANY && !flag_pic" + "TARGET_CM_EMBMEDANY && check_pic (1)" "sethi\t%%uhi(%a1), %0") (define_insn "embmedany_texthi" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] UNSPEC_EMB_TEXTHI)))] - "TARGET_CM_EMBMEDANY && !flag_pic" + "TARGET_CM_EMBMEDANY && check_pic (1)" "sethi\t%%hi(%a1), %0") (define_insn "embmedany_textulo" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (unspec:DI [(match_operand:DI 2 "text_segment_operand" "")] UNSPEC_EMB_TEXTULO)))] - "TARGET_CM_EMBMEDANY && !flag_pic" + "TARGET_CM_EMBMEDANY" "or\t%1, %%ulo(%a2), %0") (define_insn "embmedany_textlo" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "text_segment_operand" "")))] - "TARGET_CM_EMBMEDANY && !flag_pic" + "TARGET_CM_EMBMEDANY" "or\t%1, %%lo(%a2), %0") ;; Now some patterns to help reload out a bit. |