diff options
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 3 | ||||
| -rw-r--r-- | gcc/doc/sourcebuild.texi | 3 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/acle/jcvt_2.c | 33 | ||||
| -rw-r--r-- | gcc/testsuite/lib/target-supports.exp | 21 |
4 files changed, 59 insertions, 1 deletions
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index d5ca189..df780b8 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -7059,7 +7059,8 @@ (define_insn "aarch64_fjcvtzs" [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(match_operand:DF 1 "register_operand" "w")] - UNSPEC_FJCVTZS))] + UNSPEC_FJCVTZS)) + (clobber (reg:CC CC_REGNUM))] "TARGET_JSCVT" "fjcvtzs\\t%w0, %d1" [(set_attr "type" "f_cvtf2i")] diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index a7a922d..63216a0 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2063,6 +2063,9 @@ whether it does so by default). @itemx aarch64_sve2048_hw Like @code{aarch64_sve_hw}, but also test for an exact hardware vector length. +@item aarch64_fjcvtzs_hw +AArch64 target that is able to generate and execute armv8.3-a FJCVTZS +instruction. @end table @subsubsection MIPS-specific attributes diff --git a/gcc/testsuite/gcc.target/aarch64/acle/jcvt_2.c b/gcc/testsuite/gcc.target/aarch64/acle/jcvt_2.c new file mode 100644 index 0000000..ea2dfd1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/jcvt_2.c @@ -0,0 +1,33 @@ +/* Test the __jcvt ACLE intrinsic. */ +/* { dg-do run } */ +/* { dg-options "-O2 -march=armv8.3-a -save-temps" } */ +/* { dg-require-effective-target aarch64_fjcvtzs_hw } */ + +#include <arm_acle.h> + +extern void abort (void); + +#ifdef __ARM_FEATURE_JCVT +volatile int32_t x; + +int __attribute__((noinline)) +foo (double a, int b, int c) +{ + b = b > c; + x = __jcvt (a); + return b; +} + +int +main (void) +{ + int x = foo (1.1, 2, 3); + if (x) + abort (); + + return 0; +} + +#endif + +/* { dg-final { scan-assembler-times "fjcvtzs\tw\[0-9\]+, d\[0-9\]+\n" 1 } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index ba9db0b..e79015b 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -4848,6 +4848,27 @@ proc check_effective_target_aarch64_bti_hw { } { } "-O2" ] } +# Return 1 if the target supports executing the armv8.3-a FJCVTZS +# instruction. +proc check_effective_target_aarch64_fjcvtzs_hw { } { + if { ![istarget aarch64*-*-*] } { + return 0 + } + return [check_runtime aarch64_fjcvtzs_hw_available { + int + main (void) + { + double in = 25.1; + int out; + asm volatile ("fjcvtzs %w0, %d1" + : "=r" (out) + : "w" (in) + : /* No clobbers. */); + return out != 25; + } + } "-march=armv8.3-a" ] +} + # Return 1 if GCC was configured with --enable-standard-branch-protection proc check_effective_target_default_branch_protection { } { return [check_configured_with "enable-standard-branch-protection"] |