diff options
-rw-r--r-- | gcc/ChangeLog | 11 | ||||
-rw-r--r-- | gcc/c-typeck.c | 2 | ||||
-rw-r--r-- | gcc/common.opt | 4 | ||||
-rw-r--r-- | gcc/doc/invoke.texi | 15 | ||||
-rw-r--r-- | gcc/testsuite/ChangeLog | 6 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/i386/warn-vect-op-1.c | 21 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/i386/warn-vect-op-2.c | 23 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/i386/warn-vect-op-3.c | 21 | ||||
-rw-r--r-- | gcc/tree-vect-generic.c | 21 |
9 files changed, 120 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8e42253..3aeb6ab 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2011-10-11 Artjoms Sinkarovs <artyom.shinkaroff@gmail.com> + + * doc/invoke.texi: Document new warning. + * common.opt (Wvector-operation-performance): Define new warning. + * tree-vect-generic.c (expand_vector_piecewise): Warn about expanded + vector operation. + (exapnd_vector_parallel): Warn about expanded vector operation. + (lower_vec_shuffle): Warn about expanded vector operation. + * c-typeck.c (c_build_vec_perm_expr): Store correct location + when creating VEC_PERM_EXPR. + 2011-10-11 Richard Guenther <rguenther@suse.de> PR tree-optimization/50204 diff --git a/gcc/c-typeck.c b/gcc/c-typeck.c index 6dc0210..d0a0b5e 100644 --- a/gcc/c-typeck.c +++ b/gcc/c-typeck.c @@ -2930,7 +2930,7 @@ c_build_vec_perm_expr (location_t loc, tree v0, tree v1, tree mask) mask = c_fully_fold (mask, false, &maybe_const); wrap &= maybe_const; - ret = build3 (VEC_PERM_EXPR, TREE_TYPE (v0), v0, v1, mask); + ret = build3_loc (loc, VEC_PERM_EXPR, TREE_TYPE (v0), v0, v1, mask); if (!wrap) ret = c_wrap_maybe_const (ret, true); diff --git a/gcc/common.opt b/gcc/common.opt index b6b28cc..13bbf9e 100644 --- a/gcc/common.opt +++ b/gcc/common.opt @@ -694,6 +694,10 @@ Wcoverage-mismatch Common Var(warn_coverage_mismatch) Init(1) Warning Warn in case profiles in -fprofile-use do not match +Wvector-operation-performance +Common Var(warn_vector_operation_performance) Warning +Warn when a vector operation is compiled outside the SIMD + Xassembler Driver Separate diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 6888928..8be5e25 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -271,7 +271,8 @@ Objective-C and Objective-C++ Dialects}. -Wunused-label -Wunused-local-typedefs -Wunused-parameter @gol -Wno-unused-result -Wunused-value @gol -Wunused-variable @gol -Wunused-but-set-parameter -Wunused-but-set-variable @gol --Wvariadic-macros -Wvla -Wvolatile-register-var -Wwrite-strings} +-Wvariadic-macros -Wvector-operation-performance -Wvla +-Wvolatile-register-var -Wwrite-strings} @item C and Objective-C-only Warning Options @gccoptlist{-Wbad-function-cast -Wmissing-declarations @gol @@ -4542,6 +4543,18 @@ Warn if variadic macros are used in pedantic ISO C90 mode, or the GNU alternate syntax when in pedantic ISO C99 mode. This is default. To inhibit the warning messages, use @option{-Wno-variadic-macros}. +@item -Wvector-operation-performance +@opindex Wvector-operation-performance +@opindex Wno-vector-operation-performance +Warn if vector operation is not implemented via SIMD capabilities of the +architecture. Mainly useful for the performance tuning. +Vector operation can be implemented @code{piecewise} which means that the +scalar operation is performed on every vector element; +@code{in parallel} which means that the vector operation is implemented +using scalars of wider type, which normally is more performance efficient; +and @code{as a single scalar} which means that vector fits into a +scalar type. + @item -Wvla @opindex Wvla @opindex Wno-vla diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a8364c5..b8e7eba 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2011-10-11 Artjoms Sinkarovs <artyom.shinkaroff@gmail.com> + + * gcc.target/i386/warn-vect-op-3.c: New test. + * gcc.target/i386/warn-vect-op-1.c: New test. + * gcc.target/i386/warn-vect-op-2.c: New test. + 2011-10-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * gcc.dg/pr49994-3.c: Add -mbackchain for s390 and s390x. diff --git a/gcc/testsuite/gcc.target/i386/warn-vect-op-1.c b/gcc/testsuite/gcc.target/i386/warn-vect-op-1.c new file mode 100644 index 0000000..f87cf59 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/warn-vect-op-1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-sse -Wvector-operation-performance" } */ +#define vector(elcount, type) \ +__attribute__((vector_size((elcount)*sizeof(type)))) type + +int main (int argc, char *argv[]) +{ + vector (4, int) v0 = {argc, 1, 15, 38}; + vector (4, int) v1 = {-4, argc, 2, 11}; + vector (4, int) res[] = + { + v0 + v1, /* { dg-warning "expanded piecewise" } */ + v0 - v1, /* { dg-warning "expanded piecewise" } */ + v0 > v1, /* { dg-warning "expanded piecewise" } */ + v0 & v1, /* { dg-warning "expanded in parallel" } */ + __builtin_shuffle (v0, v1), /* { dg-warning "expanded piecewise" } */ + __builtin_shuffle (v0, v1, v1) /* { dg-warning "expanded piecewise" } */ + }; + + return res[argc][argc]; +} diff --git a/gcc/testsuite/gcc.target/i386/warn-vect-op-2.c b/gcc/testsuite/gcc.target/i386/warn-vect-op-2.c new file mode 100644 index 0000000..f081d8a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/warn-vect-op-2.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-sse -Wvector-operation-performance" } */ +#define vector(elcount, type) \ +__attribute__((vector_size((elcount)*sizeof(type)))) type + +int main (int argc, char *argv[]) +{ + vector (16, signed char) v0 = {argc, 1, 15, 38, 12, -1, argc, 2, + argc, 1, 15, 38, 12, -1, argc, 2}; + vector (16, signed char) v1 = {-4, argc, 2, 11, 1, 17, -8, argc, + argc, 1, 15, 38, 12, -1, argc, 2}; + vector (16, signed char) res[] = + { + v0 + v1, /* { dg-warning "expanded in parallel" } */ + v0 - v1, /* { dg-warning "expanded in parallel" } */ + v0 > v1, /* { dg-warning "expanded piecewise" } */ + v0 & v1, /* { dg-warning "expanded in parallel" } */ + __builtin_shuffle (v0, v1), /* { dg-warning "expanded piecewise" } */ + __builtin_shuffle (v0, v1, v1) /* { dg-warning "expanded piecewise" } */ + }; + + return res[argc][argc]; +} diff --git a/gcc/testsuite/gcc.target/i386/warn-vect-op-3.c b/gcc/testsuite/gcc.target/i386/warn-vect-op-3.c new file mode 100644 index 0000000..ccb9e98 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/warn-vect-op-3.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-sse -Wvector-operation-performance" } */ +#define vector(elcount, type) \ +__attribute__((vector_size((elcount)*sizeof(type)))) type + +int main (int argc, char *argv[]) +{ + vector (8, short) v0 = {argc, 1, 15, 38, 12, -1, argc, 2}; + vector (8, short) v1 = {-4, argc, 2, 11, 1, 17, -8, argc}; + vector (8, short) res[] = + { + v0 + v1, /* { dg-warning "expanded in parallel" } */ + v0 - v1, /* { dg-warning "expanded in parallel" } */ + v0 > v1, /* { dg-warning "expanded piecewise" } */ + v0 & v1, /* { dg-warning "expanded in parallel" } */ + __builtin_shuffle (v0, v1), /* { dg-warning "expanded piecewise" } */ + __builtin_shuffle (v0, v1, v1) /* { dg-warning "expanded piecewise" } */ + }; + + return res[argc][argc]; +} diff --git a/gcc/tree-vect-generic.c b/gcc/tree-vect-generic.c index 1d11701..4e79b15 100644 --- a/gcc/tree-vect-generic.c +++ b/gcc/tree-vect-generic.c @@ -235,6 +235,14 @@ expand_vector_piecewise (gimple_stmt_iterator *gsi, elem_op_func f, int delta = tree_low_cst (part_width, 1) / tree_low_cst (TYPE_SIZE (TREE_TYPE (type)), 1); int i; + location_t loc = gimple_location (gsi_stmt (*gsi)); + + if (types_compatible_p (gimple_expr_type (gsi_stmt (*gsi)), type)) + warning_at (loc, OPT_Wvector_operation_performance, + "vector operation will be expanded piecewise"); + else + warning_at (loc, OPT_Wvector_operation_performance, + "vector operation will be expanded in parallel"); v = VEC_alloc(constructor_elt, gc, (nunits + delta - 1) / delta); for (i = 0; i < nunits; @@ -260,6 +268,7 @@ expand_vector_parallel (gimple_stmt_iterator *gsi, elem_op_func f, tree type, tree result, compute_type; enum machine_mode mode; int n_words = tree_low_cst (TYPE_SIZE_UNIT (type), 1) / UNITS_PER_WORD; + location_t loc = gimple_location (gsi_stmt (*gsi)); /* We have three strategies. If the type is already correct, just do the operation an element at a time. Else, if the vector is wider than @@ -284,6 +293,9 @@ expand_vector_parallel (gimple_stmt_iterator *gsi, elem_op_func f, tree type, mode = mode_for_size (tree_low_cst (TYPE_SIZE (type), 1), MODE_INT, 0); compute_type = lang_hooks.types.type_for_mode (mode, 1); result = f (gsi, compute_type, a, b, NULL_TREE, NULL_TREE, code); + warning_at (loc, OPT_Wvector_operation_performance, + "vector operation will be expanded with a " + "single scalar operation"); } return result; @@ -400,8 +412,8 @@ expand_vector_operation (gimple_stmt_iterator *gsi, tree type, tree compute_type case PLUS_EXPR: case MINUS_EXPR: if (!TYPE_OVERFLOW_TRAPS (type)) - return expand_vector_addition (gsi, do_binop, do_plus_minus, type, - gimple_assign_rhs1 (assign), + return expand_vector_addition (gsi, do_binop, do_plus_minus, type, + gimple_assign_rhs1 (assign), gimple_assign_rhs2 (assign), code); break; @@ -626,10 +638,15 @@ lower_vec_perm (gimple_stmt_iterator *gsi) tree constr, t, si, i_val; tree vec0tmp = NULL_TREE, vec1tmp = NULL_TREE, masktmp = NULL_TREE; bool two_operand_p = !operand_equal_p (vec0, vec1, 0); + location_t loc = gimple_location (gsi_stmt (*gsi)); unsigned i; if (expand_vec_perm_expr_p (TYPE_MODE (vect_type), vec0, vec1, mask)) return; + + warning_at (loc, OPT_Wvector_operation_performance, + "vector shuffling operation will be expanded piecewise"); + v = VEC_alloc (constructor_elt, gc, elements); for (i = 0; i < elements; i++) |