diff options
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 22 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c | 1 |
5 files changed, 38 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index abf7c62..57a7df7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2016-02-02 Wilco Dijkstra <wdijkstr@arm.com> + + * config/aarch64/aarch64.c + (TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS): New define. + (aarch64_ira_change_pseudo_allocno_class): New function. + 2016-02-02 Uros Bizjak <ubizjak@gmail.com> PR target/67032 diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index aee6685..e7cfcb6 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -724,6 +724,24 @@ aarch64_err_no_fpadvsimd (machine_mode mode, const char *msg) error ("%qs feature modifier is incompatible with %s %s", "+nofp", mc, msg); } +/* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS. + The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have + the same cost even if ALL_REGS has a much larger cost. This results in bad + allocations and spilling. To avoid this we force the class to GENERAL_REGS + if the mode is integer. */ + +static reg_class_t +aarch64_ira_change_pseudo_allocno_class (int regno, reg_class_t allocno_class) +{ + enum machine_mode mode; + + if (allocno_class != ALL_REGS) + return allocno_class; + + mode = PSEUDO_REGNO_MODE (regno); + return FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode) ? FP_REGS : GENERAL_REGS; +} + static unsigned int aarch64_min_divisions_for_recip_mul (enum machine_mode mode) { @@ -14009,6 +14027,10 @@ aarch64_optab_supported_p (int op, machine_mode, machine_mode, #undef TARGET_INIT_BUILTINS #define TARGET_INIT_BUILTINS aarch64_init_builtins +#undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS +#define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \ + aarch64_ira_change_pseudo_allocno_class + #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 9ed6c54..5229fa1 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,11 @@ +2016-02-02 Wilco Dijkstra <wdijkstr@arm.com> + + * gcc.target/aarch64/scalar_shift_1.c + (test_corners_sisd_di): Improve force to SIMD register. + (test_corners_sisd_si): Likewise. + * gcc.target/aarch64/vect-ld1r-compile-fp.c: + Remove scan-assembler check for ldr. + 2016-02-02 Richard Biener <rguenther@suse.de> PR tree-optimization/69595 diff --git a/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c b/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c index 363f554..8465c89 100644 --- a/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c +++ b/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c @@ -186,9 +186,9 @@ test_corners_sisd_di (Int64x1 b) { force_simd_di (b); b = b >> 63; + force_simd_di (b); b = b >> 0; b += b >> 65; /* { dg-warning "right shift count >= width of type" } */ - force_simd_di (b); return b; } @@ -199,9 +199,9 @@ test_corners_sisd_si (Int32x1 b) { force_simd_si (b); b = b >> 31; + force_simd_si (b); b = b >> 0; b += b >> 33; /* { dg-warning "right shift count >= width of type" } */ - force_simd_si (b); return b; } diff --git a/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c b/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c index 66e0168..4711c61 100644 --- a/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c +++ b/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c @@ -8,6 +8,5 @@ DEF (float) DEF (double) /* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.4s"} } */ -/* { dg-final { scan-assembler "ldr\\t\x\[0-9\]+"} } */ /* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.2d"} } */ |