diff options
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 6 |
2 files changed, 8 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index aae7575..3ec5aa7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2015-04-27 Yvan Roux <yvan.roux@linaro.org> + + * config/arm/arm.md (*arm_subsi3_insn): Fixed redundant + alternatives. + 2015-04-26 Tom de Vries <tom@codesourcery.com> PR tree-optimization/65826 diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 85d27d9..57b95bf 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -1177,9 +1177,9 @@ ; ??? Check Thumb-2 split length (define_insn_and_split "*arm_subsi3_insn" - [(set (match_operand:SI 0 "s_register_operand" "=l,l ,l ,l ,r ,r,r,rk,r") - (minus:SI (match_operand:SI 1 "reg_or_int_operand" "l ,0 ,l ,Pz,rI,r,r,k ,?n") - (match_operand:SI 2 "reg_or_int_operand" "l ,Py,Pd,l ,r ,I,r,r ,r")))] + [(set (match_operand:SI 0 "s_register_operand" "=l,l ,l ,l ,r,r,r,rk,r") + (minus:SI (match_operand:SI 1 "reg_or_int_operand" "l ,0 ,l ,Pz,I,r,r,k ,?n") + (match_operand:SI 2 "reg_or_int_operand" "l ,Py,Pd,l ,r,I,r,r ,r")))] "TARGET_32BIT" "@ sub%?\\t%0, %1, %2 |