diff options
| -rw-r--r-- | gcc/ChangeLog | 54 | ||||
| -rw-r--r-- | gcc/config/arm/arm-c.c | 4 | ||||
| -rw-r--r-- | gcc/config/arm/arm-cpus.in | 35 | ||||
| -rw-r--r-- | gcc/config/arm/arm-protos.h | 8 | ||||
| -rw-r--r-- | gcc/config/arm/arm-tables.opt | 62 | ||||
| -rw-r--r-- | gcc/config/arm/arm.c | 33 | ||||
| -rw-r--r-- | gcc/config/arm/arm.h | 16 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 26 | ||||
| -rw-r--r-- | gcc/config/arm/t-arm-elf | 4 | ||||
| -rw-r--r-- | gcc/config/arm/t-multilib | 2 | ||||
| -rw-r--r-- | gcc/config/arm/thumb1.md | 8 | ||||
| -rw-r--r-- | gcc/config/arm/vxworks.h | 9 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 3 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 9 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/armv5_thumb_isa.c | 8 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/di-longlong64-sync-withhelpers.c | 6 | ||||
| -rw-r--r-- | gcc/testsuite/lib/target-supports.exp | 5 | ||||
| -rw-r--r-- | libgcc/ChangeLog | 4 | ||||
| -rw-r--r-- | libgcc/config/arm/libunwind.S | 4 |
19 files changed, 160 insertions, 140 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index da16d87..ce3dc01 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,57 @@ +2018-05-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/arm/arm-cpus.in (armv5, armv5e): Delete features. + (armv5t, armv5te): New features. + (ARMv5, ARMv5e): Delete fgroups. + (ARMv5t, ARMv5te): Adjust for above changes. + (ARMv6m): Likewise. + (armv5, armv5e): Delete arches. + * config/arm/arm.md (*call_reg_armv5): Use arm_arch5t instead of + arm_arch5. + (*call_reg_arm): Likewise. + (*call_value_reg_armv5): Likewise. + (*call_value_reg_arm): Likewise. + (*call_symbol): Likewise. + (*call_value_symbol): Likewise. + (*sibcall_insn): Likewise. + (*sibcall_value_insn): Likewise. + (clzsi2): Likewise. + (prefetch): Likewise. + (define_split and define_peephole2 dependent on arm_arch5): + Likewise. + * config/arm/arm.h (TARGET_LDRD): Use arm_arch5te instead of + arm_arch5e. + (TARGET_ARM_QBIT): Likewise. + (TARGET_DSP_MULTIPLY): Likewise. + (enum base_architecture): Delete BASE_ARCH_5, BASE_ARCH_5E. + (arm_arch5, arm_arch5e): Delete. + (arm_arch5t, arm_arch5te): Declare. + * config/arm/arm.c (arm_arch5, arm_arch5e): Delete. + (arm_arch5t): Declare. + (arm_option_reconfigure_globals): Update for the above. + (arm_options_perform_arch_sanity_checks): Update comment, replace + use of arm_arch5 with arm_arch5t. + (use_return_insn): Likewise. + (arm_emit_call_insn): Likewise. + (output_return_instruction): Likewise. + (arm_final_prescan_insn): Likewise. + (arm_coproc_builtin_available): Likewise. + * config/arm/arm-c.c (arm_cpu_builtins): Replace arm_arch5 and + arm_arch5e with arm_arch5t and arm_arch5te. + * config/arm/arm-protos.h (arm_arch5, arm_arch5e): Delete. + (arm_arch5t, arm_arch5te): Declare. + * config/arm/arm-tables.opt: Regenerate. + * config/arm/t-arm-elf: Remove references to armv5, armv5e. + * config/arm/t-multilib: Likewise. + * config/arm/thumb1.md (*call_reg_thumb1_v5): Check arm_arch5t + instead of arm_arch5. + (*call_reg_thumb1): Likewise. + (*call_value_reg_thumb1_v5): Likewise. + (*call_value_reg_thumb1): Likewise. + * config/arm/vxworks.h (TARGET_OS_CPP_BUILTINS): Remove now + unreachable path. + * doc/invoke.texi (ARM Options): Remove references to armv5, armv5e. + 2018-05-18 Martin Liska <mliska@suse.cz> PR gcov-profile/84846 diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c index 7c741e9..4471f79 100644 --- a/gcc/config/arm/arm-c.c +++ b/gcc/config/arm/arm-c.c @@ -212,9 +212,9 @@ arm_cpu_builtins (struct cpp_reader* pfile) { int coproc_level = 0x1; - if (arm_arch5) + if (arm_arch5t) coproc_level |= 0x2; - if (arm_arch5e) + if (arm_arch5te) coproc_level |= 0x4; if (arm_arch6) coproc_level |= 0x8; diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index 96972a0..0a31887 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -60,14 +60,14 @@ define feature mode32 # Architecture rel 4 define feature armv4 -# Architecture rel 5 -define feature armv5 - # Thumb aware. define feature thumb -# Architecture rel 5e. -define feature armv5e +# Architecture rel 5t. +define feature armv5t + +# Architecture rel 5te. +define feature armv5te # XScale. define feature xscale @@ -220,10 +220,8 @@ define fgroup ARMv3 ARMv2 mode32 define fgroup ARMv3m ARMv3 armv3m define fgroup ARMv4 ARMv3m armv4 define fgroup ARMv4t ARMv4 thumb -define fgroup ARMv5 ARMv4 armv5 -define fgroup ARMv5t ARMv5 thumb -define fgroup ARMv5e ARMv5 armv5e -define fgroup ARMv5te ARMv5e thumb +define fgroup ARMv5t ARMv4t armv5t +define fgroup ARMv5te ARMv5t armv5te define fgroup ARMv5tej ARMv5te define fgroup ARMv6 ARMv5te armv6 be8 define fgroup ARMv6j ARMv6 @@ -234,7 +232,7 @@ define fgroup ARMv6zk ARMv6k define fgroup ARMv6t2 ARMv6 thumb2 # This is suspect. ARMv6-m doesn't really pull in any useful features # from ARMv5* or ARMv6. -define fgroup ARMv6m mode32 armv3m armv4 thumb armv5 armv5e armv6 be8 +define fgroup ARMv6m mode32 armv3m armv4 thumb armv5t armv5te armv6 be8 # This is suspect, the 'common' ARMv7 subset excludes the thumb2 'DSP' and # integer SIMD instructions that are in ARMv6T2. */ define fgroup ARMv7 ARMv6m thumb2 armv7 @@ -325,13 +323,6 @@ begin arch armv4t isa ARMv4t end arch armv4t -begin arch armv5 - tune for arm10tdmi - tune flags CO_PROC - base 5 - isa ARMv5 -end arch armv5 - begin arch armv5t tune for arm10tdmi tune flags CO_PROC @@ -339,16 +330,6 @@ begin arch armv5t isa ARMv5t end arch armv5t -begin arch armv5e - tune for arm1026ej-s - tune flags CO_PROC - base 5E - isa ARMv5e - option fp add VFPv2 FP_DBL - optalias vfpv2 fp - option nofp remove ALL_FP -end arch armv5e - begin arch armv5te tune for arm1026ej-s tune flags CO_PROC diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 9d0acde..ea2cf69 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -388,11 +388,11 @@ extern int arm_arch4; /* Nonzero if this chip supports the ARM Architecture 4t extensions. */ extern int arm_arch4t; -/* Nonzero if this chip supports the ARM Architecture 5 extensions. */ -extern int arm_arch5; +/* Nonzero if this chip supports the ARM Architecture 5t extensions. */ +extern int arm_arch5t; -/* Nonzero if this chip supports the ARM Architecture 5E extensions. */ -extern int arm_arch5e; +/* Nonzero if this chip supports the ARM Architecture 5te extensions. */ +extern int arm_arch5te; /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ extern int arm_arch6; diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index 60e5065..b05da64 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -383,94 +383,88 @@ EnumValue Enum(arm_arch) String(armv4t) Value(5) EnumValue -Enum(arm_arch) String(armv5) Value(6) +Enum(arm_arch) String(armv5t) Value(6) EnumValue -Enum(arm_arch) String(armv5t) Value(7) +Enum(arm_arch) String(armv5te) Value(7) EnumValue -Enum(arm_arch) String(armv5e) Value(8) +Enum(arm_arch) String(armv5tej) Value(8) EnumValue -Enum(arm_arch) String(armv5te) Value(9) +Enum(arm_arch) String(armv6) Value(9) EnumValue -Enum(arm_arch) String(armv5tej) Value(10) +Enum(arm_arch) String(armv6j) Value(10) EnumValue -Enum(arm_arch) String(armv6) Value(11) +Enum(arm_arch) String(armv6k) Value(11) EnumValue -Enum(arm_arch) String(armv6j) Value(12) +Enum(arm_arch) String(armv6z) Value(12) EnumValue -Enum(arm_arch) String(armv6k) Value(13) +Enum(arm_arch) String(armv6kz) Value(13) EnumValue -Enum(arm_arch) String(armv6z) Value(14) +Enum(arm_arch) String(armv6zk) Value(14) EnumValue -Enum(arm_arch) String(armv6kz) Value(15) +Enum(arm_arch) String(armv6t2) Value(15) EnumValue -Enum(arm_arch) String(armv6zk) Value(16) +Enum(arm_arch) String(armv6-m) Value(16) EnumValue -Enum(arm_arch) String(armv6t2) Value(17) +Enum(arm_arch) String(armv6s-m) Value(17) EnumValue -Enum(arm_arch) String(armv6-m) Value(18) +Enum(arm_arch) String(armv7) Value(18) EnumValue -Enum(arm_arch) String(armv6s-m) Value(19) +Enum(arm_arch) String(armv7-a) Value(19) EnumValue -Enum(arm_arch) String(armv7) Value(20) +Enum(arm_arch) String(armv7ve) Value(20) EnumValue -Enum(arm_arch) String(armv7-a) Value(21) +Enum(arm_arch) String(armv7-r) Value(21) EnumValue -Enum(arm_arch) String(armv7ve) Value(22) +Enum(arm_arch) String(armv7-m) Value(22) EnumValue -Enum(arm_arch) String(armv7-r) Value(23) +Enum(arm_arch) String(armv7e-m) Value(23) EnumValue -Enum(arm_arch) String(armv7-m) Value(24) +Enum(arm_arch) String(armv8-a) Value(24) EnumValue -Enum(arm_arch) String(armv7e-m) Value(25) +Enum(arm_arch) String(armv8.1-a) Value(25) EnumValue -Enum(arm_arch) String(armv8-a) Value(26) +Enum(arm_arch) String(armv8.2-a) Value(26) EnumValue -Enum(arm_arch) String(armv8.1-a) Value(27) +Enum(arm_arch) String(armv8.3-a) Value(27) EnumValue -Enum(arm_arch) String(armv8.2-a) Value(28) +Enum(arm_arch) String(armv8.4-a) Value(28) EnumValue -Enum(arm_arch) String(armv8.3-a) Value(29) +Enum(arm_arch) String(armv8-m.base) Value(29) EnumValue -Enum(arm_arch) String(armv8.4-a) Value(30) +Enum(arm_arch) String(armv8-m.main) Value(30) EnumValue -Enum(arm_arch) String(armv8-m.base) Value(31) +Enum(arm_arch) String(armv8-r) Value(31) EnumValue -Enum(arm_arch) String(armv8-m.main) Value(32) +Enum(arm_arch) String(iwmmxt) Value(32) EnumValue -Enum(arm_arch) String(armv8-r) Value(33) - -EnumValue -Enum(arm_arch) String(iwmmxt) Value(34) - -EnumValue -Enum(arm_arch) String(iwmmxt2) Value(35) +Enum(arm_arch) String(iwmmxt2) Value(33) Enum Name(arm_fpu) Type(enum fpu_type) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 08120c6..3bfc0d5 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -859,11 +859,8 @@ int arm_arch4 = 0; /* Nonzero if this chip supports the ARM Architecture 4t extensions. */ int arm_arch4t = 0; -/* Nonzero if this chip supports the ARM Architecture 5 extensions. */ -int arm_arch5 = 0; - -/* Nonzero if this chip supports the ARM Architecture 5E extensions. */ -int arm_arch5e = 0; +/* Nonzero if this chip supports the ARM Architecture 5T extensions. */ +int arm_arch5t = 0; /* Nonzero if this chip supports the ARM Architecture 5TE extensions. */ int arm_arch5te = 0; @@ -3642,10 +3639,8 @@ arm_option_reconfigure_globals (void) arm_arch3m = bitmap_bit_p (arm_active_target.isa, isa_bit_armv3m); arm_arch4 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv4); arm_arch4t = arm_arch4 && bitmap_bit_p (arm_active_target.isa, isa_bit_thumb); - arm_arch5 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv5); - arm_arch5e = bitmap_bit_p (arm_active_target.isa, isa_bit_armv5e); - arm_arch5te = arm_arch5e - && bitmap_bit_p (arm_active_target.isa, isa_bit_thumb); + arm_arch5t = bitmap_bit_p (arm_active_target.isa, isa_bit_armv5t); + arm_arch5te = bitmap_bit_p (arm_active_target.isa, isa_bit_armv5te); arm_arch6 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv6); arm_arch6k = bitmap_bit_p (arm_active_target.isa, isa_bit_armv6k); arm_arch_notm = bitmap_bit_p (arm_active_target.isa, isa_bit_notm); @@ -3694,7 +3689,7 @@ arm_option_reconfigure_globals (void) void arm_options_perform_arch_sanity_checks (void) { - /* V5 code we generate is completely interworking capable, so we turn off + /* V5T code we generate is completely interworking capable, so we turn off TARGET_INTERWORK here to avoid many tests later on. */ /* XXX However, we must pass the right pre-processor defines to CPP @@ -3702,7 +3697,7 @@ arm_options_perform_arch_sanity_checks (void) if (TARGET_INTERWORK) arm_cpp_interwork = 1; - if (arm_arch5) + if (arm_arch5t) target_flags &= ~MASK_INTERWORK; if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN) @@ -4061,10 +4056,10 @@ use_return_insn (int iscond, rtx sibling) the other registers, since that is never slower than executing another instruction. - We test for !arm_arch5 here, because code for any architecture + We test for !arm_arch5t here, because code for any architecture less than this could potentially be run on one of the buggy chips. */ - if (stack_adjust == 4 && !arm_arch5 && TARGET_ARM) + if (stack_adjust == 4 && !arm_arch5t && TARGET_ARM) { /* Validate that r3 is a call-clobbered register (always true in the default abi) ... */ @@ -18097,7 +18092,7 @@ arm_emit_call_insn (rtx pat, rtx addr, bool sibcall) const char * output_call (rtx *operands) { - gcc_assert (!arm_arch5); /* Patterns should call blx <reg> directly. */ + gcc_assert (!arm_arch5t); /* Patterns should call blx <reg> directly. */ /* Handle calls to lr using ip (which may be clobbered in subr anyway). */ if (REGNO (operands[0]) == LR_REGNUM) @@ -19732,7 +19727,7 @@ output_return_instruction (rtx operand, bool really_return, bool reverse, stack_adjust = offsets->outgoing_args - offsets->saved_regs; gcc_assert (stack_adjust == 0 || stack_adjust == 4); - if (stack_adjust && arm_arch5 && TARGET_ARM) + if (stack_adjust && arm_arch5t && TARGET_ARM) sprintf (instr, "ldmib%s\t%%|sp, {", conditional); else { @@ -19807,7 +19802,7 @@ output_return_instruction (rtx operand, bool really_return, bool reverse, break; case ARM_FT_INTERWORKED: - gcc_assert (arm_arch5 || arm_arch4t); + gcc_assert (arm_arch5t || arm_arch4t); sprintf (instr, "bx%s\t%%|lr", conditional); break; @@ -19855,7 +19850,7 @@ output_return_instruction (rtx operand, bool really_return, bool reverse, snprintf (instr, sizeof (instr), "bxns\t%%|lr"); } /* Use bx if it's available. */ - else if (arm_arch5 || arm_arch4t) + else if (arm_arch5t || arm_arch4t) sprintf (instr, "bx%s\t%%|lr", conditional); else sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional); @@ -23459,7 +23454,7 @@ arm_final_prescan_insn (rtx_insn *insn) used since they make interworking inefficient (the linker can't transform BL<cond> into BLX). That's only a problem if the machine has BLX. */ - if (arm_arch5) + if (arm_arch5t) { fail = TRUE; break; @@ -31433,7 +31428,7 @@ arm_coproc_builtin_available (enum unspecv builtin) case VUNSPEC_MRC2: /* Only present in ARMv5*, ARMv6 (but not ARMv6-M), ARMv7* and ARMv8-{A,M}. */ - if (arm_arch5) + if (arm_arch5t) return true; break; case VUNSPEC_MCRR: diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 2809112..f3a6f7d 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -155,7 +155,7 @@ extern tree arm_fp16_type_node; /* Thumb-1 only. */ #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) -#define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN \ +#define TARGET_LDRD (arm_arch5te && ARM_DOUBLEWORD_ALIGN \ && !TARGET_THUMB1) #define TARGET_CRC32 (arm_arch_crc) @@ -233,13 +233,13 @@ extern tree arm_fp16_type_node; /* Q-bit is present. */ #define TARGET_ARM_QBIT \ - (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7)) + (TARGET_32BIT && arm_arch5te && (arm_arch_notm || arm_arch7)) /* Saturation operation, e.g. SSAT. */ #define TARGET_ARM_SAT \ (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7)) /* "DSP" multiply instructions, eg. SMULxy. */ #define TARGET_DSP_MULTIPLY \ - (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em)) + (TARGET_32BIT && arm_arch5te && (arm_arch_notm || arm_arch7em)) /* Integer SIMD instructions, and extend-accumulate instructions. */ #define TARGET_INT_SIMD \ (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em)) @@ -375,8 +375,6 @@ enum base_architecture BASE_ARCH_3M = 3, BASE_ARCH_4 = 4, BASE_ARCH_4T = 4, - BASE_ARCH_5 = 5, - BASE_ARCH_5E = 5, BASE_ARCH_5T = 5, BASE_ARCH_5TE = 5, BASE_ARCH_5TEJ = 5, @@ -410,11 +408,11 @@ extern int arm_arch4; /* Nonzero if this chip supports the ARM Architecture 4T extensions. */ extern int arm_arch4t; -/* Nonzero if this chip supports the ARM Architecture 5 extensions. */ -extern int arm_arch5; +/* Nonzero if this chip supports the ARM Architecture 5T extensions. */ +extern int arm_arch5t; -/* Nonzero if this chip supports the ARM Architecture 5E extensions. */ -extern int arm_arch5e; +/* Nonzero if this chip supports the ARM Architecture 5TE extensions. */ +extern int arm_arch5te; /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ extern int arm_arch6; diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 2d5359e..118cecf 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -8087,7 +8087,7 @@ (match_operand 1 "" "")) (use (match_operand 2 "" "")) (clobber (reg:SI LR_REGNUM))] - "TARGET_ARM && arm_arch5 && !SIBLING_CALL_P (insn)" + "TARGET_ARM && arm_arch5t && !SIBLING_CALL_P (insn)" "blx%?\\t%0" [(set_attr "type" "call")] ) @@ -8097,7 +8097,7 @@ (match_operand 1 "" "")) (use (match_operand 2 "" "")) (clobber (reg:SI LR_REGNUM))] - "TARGET_ARM && !arm_arch5 && !SIBLING_CALL_P (insn)" + "TARGET_ARM && !arm_arch5t && !SIBLING_CALL_P (insn)" "* return output_call (operands); " @@ -8179,7 +8179,7 @@ (match_operand 2 "" ""))) (use (match_operand 3 "" "")) (clobber (reg:SI LR_REGNUM))] - "TARGET_ARM && arm_arch5 && !SIBLING_CALL_P (insn)" + "TARGET_ARM && arm_arch5t && !SIBLING_CALL_P (insn)" "blx%?\\t%1" [(set_attr "type" "call")] ) @@ -8190,7 +8190,7 @@ (match_operand 2 "" ""))) (use (match_operand 3 "" "")) (clobber (reg:SI LR_REGNUM))] - "TARGET_ARM && !arm_arch5 && !SIBLING_CALL_P (insn)" + "TARGET_ARM && !arm_arch5t && !SIBLING_CALL_P (insn)" "* return output_call (&operands[1]); " @@ -8216,7 +8216,7 @@ /* Switch mode now when possible. */ if (SYMBOL_REF_DECL (op) && !TREE_PUBLIC (SYMBOL_REF_DECL (op)) - && arm_arch5 && arm_change_mode_p (SYMBOL_REF_DECL (op))) + && arm_arch5t && arm_change_mode_p (SYMBOL_REF_DECL (op))) return NEED_PLT_RELOC ? \"blx%?\\t%a0(PLT)\" : \"blx%?\\t(%a0)\"; return NEED_PLT_RELOC ? \"bl%?\\t%a0(PLT)\" : \"bl%?\\t%a0\"; @@ -8240,7 +8240,7 @@ /* Switch mode now when possible. */ if (SYMBOL_REF_DECL (op) && !TREE_PUBLIC (SYMBOL_REF_DECL (op)) - && arm_arch5 && arm_change_mode_p (SYMBOL_REF_DECL (op))) + && arm_arch5t && arm_change_mode_p (SYMBOL_REF_DECL (op))) return NEED_PLT_RELOC ? \"blx%?\\t%a1(PLT)\" : \"blx%?\\t(%a1)\"; return NEED_PLT_RELOC ? \"bl%?\\t%a1(PLT)\" : \"bl%?\\t%a1\"; @@ -8325,7 +8325,7 @@ return NEED_PLT_RELOC ? \"b%?\\t%a0(PLT)\" : \"b%?\\t%a0\"; else { - if (arm_arch5 || arm_arch4t) + if (arm_arch5t || arm_arch4t) return \"bx%?\\t%0\\t%@ indirect register sibling call\"; else return \"mov%?\\t%|pc, %0\\t%@ indirect register sibling call\"; @@ -8346,7 +8346,7 @@ return NEED_PLT_RELOC ? \"b%?\\t%a1(PLT)\" : \"b%?\\t%a1\"; else { - if (arm_arch5 || arm_arch4t) + if (arm_arch5t || arm_arch4t) return \"bx%?\\t%1\"; else return \"mov%?\\t%|pc, %1\\t@ indirect sibling call \"; @@ -8984,7 +8984,7 @@ (eq:SI (match_operand:SI 1 "s_register_operand" "") (const_int 0))) (clobber (reg:CC CC_REGNUM))] - "arm_arch5 && TARGET_32BIT" + "arm_arch5t && TARGET_32BIT" [(set (match_dup 0) (clz:SI (match_dup 1))) (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 5)))] ) @@ -9077,7 +9077,7 @@ (set (match_operand:SI 0 "register_operand" "") (const_int 0))) (cond_exec (eq (reg:CC CC_REGNUM) (const_int 0)) (set (match_dup 0) (const_int 1)))] - "arm_arch5 && TARGET_32BIT && peep2_regno_dead_p (3, CC_REGNUM)" + "arm_arch5t && TARGET_32BIT && peep2_regno_dead_p (3, CC_REGNUM)" [(set (match_dup 0) (clz:SI (match_dup 1))) (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 5)))] ) @@ -9116,7 +9116,7 @@ (set (match_operand:SI 0 "register_operand" "") (const_int 0))) (cond_exec (eq (reg:CC CC_REGNUM) (const_int 0)) (set (match_dup 0) (const_int 1)))] - "arm_arch5 && TARGET_32BIT && peep2_regno_dead_p (3, CC_REGNUM) + "arm_arch5t && TARGET_32BIT && peep2_regno_dead_p (3, CC_REGNUM) && !(TARGET_THUMB2 && optimize_insn_for_size_p ())" [(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2))) (set (match_dup 0) (clz:SI (match_dup 0))) @@ -11273,7 +11273,7 @@ (define_insn "clzsi2" [(set (match_operand:SI 0 "s_register_operand" "=r") (clz:SI (match_operand:SI 1 "s_register_operand" "r")))] - "TARGET_32BIT && arm_arch5" + "TARGET_32BIT && arm_arch5t" "clz%?\\t%0, %1" [(set_attr "predicable" "yes") (set_attr "type" "clz")]) @@ -11309,7 +11309,7 @@ [(prefetch (match_operand:SI 0 "address_operand" "p") (match_operand:SI 1 "" "") (match_operand:SI 2 "" ""))] - "TARGET_32BIT && arm_arch5e" + "TARGET_32BIT && arm_arch5te" "pld\\t%a0" [(set_attr "type" "load_4")] ) diff --git a/gcc/config/arm/t-arm-elf b/gcc/config/arm/t-arm-elf index 9ec5bf0..aa36ff0 100644 --- a/gcc/config/arm/t-arm-elf +++ b/gcc/config/arm/t-arm-elf @@ -39,9 +39,9 @@ v7ve_fps := vfpv3-d16 vfpv3 vfpv3-d16-fp16 vfpv3-fp16 vfpv4 neon \ v8_fps := simd fp16 crypto fp16+crypto dotprod fp16fml # We don't do anything special with these. Pre-v4t probably doesn't work. -all_early_nofp := armv2 armv2a armv3 armv3m armv4 armv4t armv5 armv5t +all_early_nofp := armv2 armv2a armv3 armv3m armv4 armv4t armv5t -all_early_arch := armv5e armv5tej armv6 armv6j armv6k armv6z armv6kz \ +all_early_arch := armv5tej armv6 armv6j armv6k armv6z armv6kz \ armv6zk armv6t2 iwmmxt iwmmxt2 all_v7_a_r := armv7-a armv7ve armv7-r diff --git a/gcc/config/arm/t-multilib b/gcc/config/arm/t-multilib index 3d0c824..25788ad 100644 --- a/gcc/config/arm/t-multilib +++ b/gcc/config/arm/t-multilib @@ -58,7 +58,7 @@ all_feat_combs = +$(firstword $(1)) \ +$(firstword $(1))$(OPT) $(OPT)),) # Variables used. -all_early_arch := armv5e armv5tej armv6 armv6j armv6k armv6z armv6kz \ +all_early_arch := armv5tej armv6 armv6j armv6k armv6z armv6kz \ armv6zk armv6t2 iwmmxt iwmmxt2 v7_a_nosimd_variants := +fp +vfpv3 +vfpv3-d16-fp16 +vfpv3-fp16 +vfpv4-d16 +vfpv4 v7_a_simd_variants := +simd +neon-fp16 +neon-vfpv4 diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md index a345c79..19dcdbc 100644 --- a/gcc/config/arm/thumb1.md +++ b/gcc/config/arm/thumb1.md @@ -1725,7 +1725,7 @@ (match_operand 1 "" "")) (use (match_operand 2 "" "")) (clobber (reg:SI LR_REGNUM))] - "TARGET_THUMB1 && arm_arch5 && !SIBLING_CALL_P (insn)" + "TARGET_THUMB1 && arm_arch5t && !SIBLING_CALL_P (insn)" "blx\\t%0" [(set_attr "length" "2") (set_attr "type" "call")] @@ -1748,7 +1748,7 @@ (match_operand 1 "" "")) (use (match_operand 2 "" "")) (clobber (reg:SI LR_REGNUM))] - "TARGET_THUMB1 && !arm_arch5 && !SIBLING_CALL_P (insn)" + "TARGET_THUMB1 && !arm_arch5t && !SIBLING_CALL_P (insn)" "* { if (!TARGET_CALLER_INTERWORKING) @@ -1769,7 +1769,7 @@ (match_operand 2 "" ""))) (use (match_operand 3 "" "")) (clobber (reg:SI LR_REGNUM))] - "TARGET_THUMB1 && arm_arch5" + "TARGET_THUMB1 && arm_arch5t" "blx\\t%1" [(set_attr "length" "2") (set_attr "type" "call")] @@ -1795,7 +1795,7 @@ (match_operand 2 "" ""))) (use (match_operand 3 "" "")) (clobber (reg:SI LR_REGNUM))] - "TARGET_THUMB1 && !arm_arch5" + "TARGET_THUMB1 && !arm_arch5t" "* { if (!TARGET_CALLER_INTERWORKING) diff --git a/gcc/config/arm/vxworks.h b/gcc/config/arm/vxworks.h index 4c99563..fc0e411 100644 --- a/gcc/config/arm/vxworks.h +++ b/gcc/config/arm/vxworks.h @@ -60,13 +60,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see else \ builtin_define ("CPU=ARMARCH6"); \ } \ - else if (arm_arch5) \ - { \ - if (TARGET_THUMB) \ - builtin_define ("CPU=ARMARCH5_T"); \ - else \ - builtin_define ("CPU=ARMARCH5"); \ - } \ + else if (arm_arch5t) \ + builtin_define ("CPU=ARMARCH5_T"); \ else if (arm_arch4) \ { \ if (TARGET_THUMB) \ diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 77e183c..d221bb9 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -15906,7 +15906,7 @@ Permissible names are: Additionally, the following architectures, which lack support for the Thumb execution state, are recognized but support is deprecated: @samp{armv2}, @samp{armv2a}, @samp{armv3}, @samp{armv3m}, -@samp{armv4}, @samp{armv5} and @samp{armv5e}. +@samp{armv4}. Many of the architectures support extensions. These can be added by appending @samp{+@var{extension}} to the architecture name. Extension @@ -15934,7 +15934,6 @@ The table below lists the supported extensions for each architecture. Architectures not mentioned do not support any extensions. @table @samp -@item armv5e @itemx armv5te @itemx armv6 @itemx armv6j diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index cbd2266..d8cf65b 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,12 @@ +2018-05-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * gcc.target/arm/pr40887.c: Update comment. + * lib/target-supports.exp: Don't generate effective target checks + and related helpers for armv5. Update comment. + * gcc.target/arm/armv5_thumb_isa.c: Delete. + * gcc.target/arm/di-longlong64-sync-withhelpers.c: Update effective + target check and options. + 2018-05-18 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> PR middle-end/85817 diff --git a/gcc/testsuite/gcc.target/arm/armv5_thumb_isa.c b/gcc/testsuite/gcc.target/arm/armv5_thumb_isa.c deleted file mode 100644 index 80a00ae..0000000 --- a/gcc/testsuite/gcc.target/arm/armv5_thumb_isa.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-require-effective-target arm_arch_v5_ok } */ -/* { dg-add-options arm_arch_v5 } */ - -#if __ARM_ARCH_ISA_THUMB -#error "__ARM_ARCH_ISA_THUMB defined for ARMv5" -#endif - -int foo; diff --git a/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withhelpers.c b/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withhelpers.c index c295916..422b061 100644 --- a/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withhelpers.c +++ b/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withhelpers.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ -/* { dg-require-effective-target arm_arch_v5_ok } */ -/* { dg-options "-std=gnu99" } */ -/* { dg-add-options arm_arch_v5 } */ +/* { dg-require-effective-target arm_arch_v5t_ok } */ +/* { dg-options "-marm -std=gnu99" } */ +/* { dg-add-options arm_arch_v5t } */ /* { dg-message "note: '__sync_fetch_and_nand' changed semantics in GCC 4.4" "fetch_and_nand" { target *-*-* } 0 } */ /* { dg-message "note: '__sync_nand_and_fetch' changed semantics in GCC 4.4" "nand_and_fetch" { target *-*-* } 0 } */ /* { dg-message "file included" "In file included" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 7ce7271..aa1296e6 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -4096,12 +4096,11 @@ proc check_effective_target_arm_fp16_hw { } { # extension (eg. ARMv8.1-A) since there is no macro defined for them. See # how only __ARM_ARCH_8A__ is checked for ARMv8.1-A. # Usage: /* { dg-require-effective-target arm_arch_v5_ok } */ -# /* { dg-add-options arm_arch_v5 } */ -# /* { dg-require-effective-target arm_arch_v5_multilib } */ +# /* { dg-add-options arm_arch_v5t } */ +# /* { dg-require-effective-target arm_arch_v5t_multilib } */ foreach { armfunc armflag armdefs } { v4 "-march=armv4 -marm" __ARM_ARCH_4__ v4t "-march=armv4t" __ARM_ARCH_4T__ - v5 "-march=armv5 -marm" __ARM_ARCH_5__ v5t "-march=armv5t" __ARM_ARCH_5T__ v5te "-march=armv5te" __ARM_ARCH_5TE__ v6 "-march=armv6" __ARM_ARCH_6__ diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog index df3d21a..f6cf15e 100644 --- a/libgcc/ChangeLog +++ b/libgcc/ChangeLog @@ -1,3 +1,7 @@ +2018-05-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/arm/libunwind.S: Update comment relating to armv5. + 2018-05-17 Jerome Lambourg <lambourg@adacore.com> * config/arm/cmse.c (cmse_check_address_range): Replace diff --git a/libgcc/config/arm/libunwind.S b/libgcc/config/arm/libunwind.S index 8d0ef97..3302447 100644 --- a/libgcc/config/arm/libunwind.S +++ b/libgcc/config/arm/libunwind.S @@ -47,8 +47,8 @@ .endm #if (__ARM_ARCH__ == 4) -/* Some coprocessors require armv5. We know this code will never be run on - other cpus. Tell gas to allow armv5, but only mark the objects as armv4. +/* Some coprocessors require armv5t. We know this code will never be run on + other cpus. Tell gas to allow armv5t, but only mark the objects as armv4. */ .arch armv5t #ifdef __ARM_ARCH_4T__ |