diff options
| -rw-r--r-- | gcc/ChangeLog | 12 | ||||
| -rw-r--r-- | gcc/config/alpha/alpha-protos.h | 1 | ||||
| -rw-r--r-- | gcc/config/alpha/alpha.c | 58 | ||||
| -rw-r--r-- | gcc/config/alpha/alpha.md | 111 |
4 files changed, 63 insertions, 119 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0d959dc..58b8bad 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,17 @@ 2004-12-22 Richard Henderson <rth@redhat.com> + * config/alpha/alpha.c (alpha_expand_mov): Split out ... + (alpha_expand_movmisalign): ... misaligned vector support. + (TARGET_VECTORIZE_MISALIGNED_MEM_OK): Remove. + * config/alpha/alpha-protos.h: Update. + * config/alpha/alpha.md (VEC): New macro. + (movv8qi, movv4hi, movv2si): Compress with VEC. + (movv8qi_fix, movv4hi_fix, movv2si_fix): Likewise. + (movv8qi_nofix, movv4hi_nofix, movv2si_nofix): Likewise. + (movmisalign<mode>): New. + +2004-12-22 Richard Henderson <rth@redhat.com> + * optabs.h (OTI_movmisalign, movmisalign_optab): New. * optabs.c (init_optabs): Create it. * genopinit.c (optabs): Initialize it. diff --git a/gcc/config/alpha/alpha-protos.h b/gcc/config/alpha/alpha-protos.h index 07d7064..24f24e6 100644 --- a/gcc/config/alpha/alpha-protos.h +++ b/gcc/config/alpha/alpha-protos.h @@ -60,6 +60,7 @@ extern rtx alpha_emit_set_const (rtx, enum machine_mode, HOST_WIDE_INT, int); extern rtx alpha_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT); extern bool alpha_expand_mov (enum machine_mode, rtx *); extern bool alpha_expand_mov_nobwx (enum machine_mode, rtx *); +extern void alpha_expand_movmisalign (enum machine_mode, rtx *); extern void alpha_emit_floatuns (rtx[]); extern rtx alpha_emit_conditional_move (rtx, enum machine_mode); extern void alpha_split_tfmode_pair (rtx[]); diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c index 26a1cd7..823cdbc 100644 --- a/gcc/config/alpha/alpha.c +++ b/gcc/config/alpha/alpha.c @@ -1982,36 +1982,11 @@ alpha_emit_set_long_const (rtx target, HOST_WIDE_INT c1, HOST_WIDE_INT c2) bool alpha_expand_mov (enum machine_mode mode, rtx *operands) { - /* Honor misaligned loads, for those we promised to do so. */ - if (GET_CODE (operands[1]) == MEM - && alpha_vector_mode_supported_p (mode) - && MEM_ALIGN (operands[1]) < GET_MODE_ALIGNMENT (mode)) - { - rtx tmp; - if (register_operand (operands[0], mode)) - tmp = operands[0]; - else - tmp = gen_reg_rtx (mode); - alpha_expand_unaligned_load (tmp, operands[1], 8, 0, 0); - if (tmp == operands[0]) - return true; - operands[1] = tmp; - } - /* If the output is not a register, the input must be. */ if (GET_CODE (operands[0]) == MEM && ! reg_or_0_operand (operands[1], mode)) operands[1] = force_reg (mode, operands[1]); - /* Honor misaligned stores, for those we promised to do so. */ - if (GET_CODE (operands[0]) == MEM - && alpha_vector_mode_supported_p (mode) - && MEM_ALIGN (operands[0]) < GET_MODE_ALIGNMENT (mode)) - { - alpha_expand_unaligned_store (operands[0], operands[1], 8, 0); - return true; - } - /* Allow legitimize_address to perform some simplifications. */ if (mode == Pmode && symbolic_operand (operands[1], mode)) { @@ -2211,6 +2186,36 @@ alpha_expand_mov_nobwx (enum machine_mode mode, rtx *operands) return false; } +/* Implement the movmisalign patterns. One of the operands is a memory + that is not natually aligned. Emit instructions to load it. */ + +void +alpha_expand_movmisalign (enum machine_mode mode, rtx *operands) +{ + /* Honor misaligned loads, for those we promised to do so. */ + if (MEM_P (operands[1])) + { + rtx tmp; + + if (register_operand (operands[0], mode)) + tmp = operands[0]; + else + tmp = gen_reg_rtx (mode); + + alpha_expand_unaligned_load (tmp, operands[1], 8, 0, 0); + if (tmp != operands[0]) + emit_move_insn (operands[0], tmp); + } + else if (MEM_P (operands[0])) + { + if (!reg_or_0_operand (operands[1], mode)) + operands[1] = force_reg (mode, operands[1]); + alpha_expand_unaligned_store (operands[0], operands[1], 8, 0); + } + else + gcc_unreachable (); +} + /* Generate an unsigned DImode to FP conversion. This is the same code optabs would emit if we didn't have TFmode patterns. @@ -9457,9 +9462,6 @@ alpha_init_libfuncs (void) #undef TARGET_BUILD_BUILTIN_VA_LIST #define TARGET_BUILD_BUILTIN_VA_LIST alpha_build_builtin_va_list -#undef TARGET_VECTORIZE_MISALIGNED_MEM_OK -#define TARGET_VECTORIZE_MISALIGNED_MEM_OK alpha_vector_mode_supported_p - struct gcc_target targetm = TARGET_INITIALIZER; diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 21bf64b..145e23c 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -6092,103 +6092,32 @@ ;; Vector operations -(define_expand "movv8qi" - [(set (match_operand:V8QI 0 "nonimmediate_operand" "") - (match_operand:V8QI 1 "general_operand" ""))] - "" -{ - if (alpha_expand_mov (V8QImode, operands)) - DONE; -}) - -(define_insn "*movv8qi_fix" - [(set (match_operand:V8QI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f") - (match_operand:V8QI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))] - "TARGET_FIX - && (register_operand (operands[0], V8QImode) - || reg_or_0_operand (operands[1], V8QImode))" - "@ - bis $31,%r1,%0 - ldq %0,%1 - stq %r1,%0 - cpys %R1,%R1,%0 - ldt %0,%1 - stt %R1,%0 - ftoit %1,%0 - itoft %1,%0" - [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")]) - -(define_insn "*movv8qi_nofix" - [(set (match_operand:V8QI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m") - (match_operand:V8QI 1 "input_operand" "rW,m,rW,*fW,m,*f"))] - "! TARGET_FIX - && (register_operand (operands[0], V8QImode) - || reg_or_0_operand (operands[1], V8QImode))" - "@ - bis $31,%r1,%0 - ldq %0,%1 - stq %r1,%0 - cpys %R1,%R1,%0 - ldt %0,%1 - stt %R1,%0" - [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")]) +(define_mode_macro VEC [V8QI V4HI V2SI]) -(define_expand "movv4hi" - [(set (match_operand:V4HI 0 "nonimmediate_operand" "") - (match_operand:V4HI 1 "general_operand" ""))] +(define_expand "mov<mode>" + [(set (match_operand:VEC 0 "nonimmediate_operand" "") + (match_operand:VEC 1 "general_operand" ""))] "" { - if (alpha_expand_mov (V4HImode, operands)) + if (alpha_expand_mov (<MODE>mode, operands)) DONE; }) -(define_insn "*movv4hi_fix" - [(set (match_operand:V4HI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f") - (match_operand:V4HI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))] - "TARGET_FIX - && (register_operand (operands[0], V4HImode) - || reg_or_0_operand (operands[1], V4HImode))" - "@ - bis $31,%r1,%0 - ldq %0,%1 - stq %r1,%0 - cpys %R1,%R1,%0 - ldt %0,%1 - stt %R1,%0 - ftoit %1,%0 - itoft %1,%0" - [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")]) - -(define_insn "*movv4hi_nofix" - [(set (match_operand:V4HI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m") - (match_operand:V4HI 1 "input_operand" "rW,m,rW,*fW,m,*f"))] - "! TARGET_FIX - && (register_operand (operands[0], V4HImode) - || reg_or_0_operand (operands[1], V4HImode))" - "@ - bis $31,%r1,%0 - ldq %0,%1 - stq %r1,%0 - cpys %R1,%R1,%0 - ldt %0,%1 - stt %R1,%0" - [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")]) - -(define_expand "movv2si" - [(set (match_operand:V2SI 0 "nonimmediate_operand" "") - (match_operand:V2SI 1 "general_operand" ""))] +(define_expand "movmisalign<mode>" + [(set (match_operand:VEC 0 "nonimmediate_operand" "") + (match_operand:VEC 1 "general_operand" ""))] "" { - if (alpha_expand_mov (V2SImode, operands)) - DONE; + alpha_expand_movmisalign (<MODE>mode, operands); + DONE; }) -(define_insn "*movv2si_fix" - [(set (match_operand:V2SI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f") - (match_operand:V2SI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))] +(define_insn "*mov<mode>_fix" + [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f") + (match_operand:VEC 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))] "TARGET_FIX - && (register_operand (operands[0], V2SImode) - || reg_or_0_operand (operands[1], V2SImode))" + && (register_operand (operands[0], <MODE>mode) + || reg_or_0_operand (operands[1], <MODE>mode))" "@ bis $31,%r1,%0 ldq %0,%1 @@ -6200,12 +6129,12 @@ itoft %1,%0" [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")]) -(define_insn "*movv2si_nofix" - [(set (match_operand:V2SI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m") - (match_operand:V2SI 1 "input_operand" "rW,m,rW,*fW,m,*f"))] +(define_insn "*mov<mode>_nofix" + [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,m,*f,*f,m") + (match_operand:VEC 1 "input_operand" "rW,m,rW,*fW,m,*f"))] "! TARGET_FIX - && (register_operand (operands[0], V2SImode) - || reg_or_0_operand (operands[1], V2SImode))" + && (register_operand (operands[0], <MODE>mode) + || reg_or_0_operand (operands[1], <MODE>mode))" "@ bis $31,%r1,%0 ldq %0,%1 |