diff options
| -rw-r--r-- | gcc/config/riscv/vector.md | 1 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/base/pr117990-run-1.c | 24 |
2 files changed, 25 insertions, 0 deletions
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index a3b46ba..58406f3 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -2381,6 +2381,7 @@ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec:V_VLS [(match_operand:V_VLS 3 "memory_operand" " m, m, m, m, m, m") + (mem:BLK (scratch)) (match_operand 4 "<V_VLS:stride_predicate>" "<V_VLS:stride_load_constraint>")] UNSPEC_STRIDED) (match_operand:V_VLS 2 "vector_merge_operand" " 0, vu, vu, 0, vu, vu")))] "TARGET_VECTOR" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr117990-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr117990-run-1.c new file mode 100644 index 0000000..414bebd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr117990-run-1.c @@ -0,0 +1,24 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#define STEP 10 + +char d[225]; +int e[STEP]; + +int main() { + // store 0, 10, 20, 30, 40, 50, 60, 70, 80, 90 + for (long h = 0; h < STEP; ++h) + d[h * STEP] = 9; + + // load 30, 40, 50, 60, 70, 80, 90 + // store 3, 4, 5, 6, 7, 8, 9 + for (int h = 3; h < STEP; h += 1) + e[h] = d[h * STEP]; + + if (e[5] != 9) { + __builtin_abort (); + } + + return 0; +} |