diff options
| -rw-r--r-- | gcc/ChangeLog | 103 | ||||
| -rw-r--r-- | gcc/config/m68k/cf.md | 1922 | ||||
| -rw-r--r-- | gcc/config/m68k/m68k-protos.h | 3 | ||||
| -rw-r--r-- | gcc/config/m68k/m68k.c | 869 | ||||
| -rw-r--r-- | gcc/config/m68k/m68k.h | 4 | ||||
| -rw-r--r-- | gcc/config/m68k/m68k.md | 489 |
6 files changed, 2161 insertions, 1229 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ebc3aad..7679020 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,106 @@ +2008-05-07 Maxim Kuvyrkov <maxim@codesourcery.com> + + Cleanup ColdFire scheduling support and add V4 pipeline model. + + * config/m68k/m68k.md (UNSPEC_TIE): New constant. + (define_attr cpu): Add cfv4 value. + (define_attr type, define_attr type1): Merge into a single 'type' + attribute. Update all uses. + (define_attr opx_type, define_attr opy_type, define_attr opx_access): + Rearrange and update. Rename value 'reg' to 'Rn', add value 'FPn'. + Update all uses. + (define_attr opx_mem, define_attr opy_mem): Remove. + (define_attr op_mem): Clean up, update comment. + (define_attr size): Use specific values instead of general int. + (define_attr guess, define_attr split): Remove. Update all uses. + (movdf_internal, tstsi_internal, tsthi_internal, tstqi_internal, + tst<mode>_68881, pushexthisi_const, movsi_const0_68000_10, + movsi_const0_68040_60, movsi_const0, movsi_cf, movstrictqi_cf, + zero_extendhisi2_cf, zero_extendqisi2_cfv4, cfv4_extendhisi2, + 68k_extendhisi2, extendqihi2, cfv4_extendqisi2, 68k_extendqisi2, + floatsi<mode>2_68881, ftrunc<mode>2_68881, ftrunc<mode>2_cf, + fix<mode>qi2_68881, fix<mode>hi2_68881, fix<mode>si2_68881, + adddi_dishl32, addsi3_5200, add<mode>3_floatsi_68881, + add<mode>3_floathi_68881, add<mode>3_floatqi_68881, + add<mode>3_68881, add<mode>3_cf, subdi_dishl32, subsi3, + sub<mode>3_floatsi_68881, sub<mode>3_floathi_68881, + sub<mode>3_floatqi_68881, sub<mode>3_68881, sub<mode>3_cf, + mulhi3, mulhisi3, mulhisisi3_s, mulsi3_68020, mulsi3_cf, + umulhisi3, mulhisisi3_z, mul<mode>3_floatsi_68881, + mul<mode>3_floathi_68881, mul<mode>3_floatqi_68881, fmul<mode>3_cf, + div<mode>3_cf, sqrt<mode>2_cf, abs<mode>2_cf, clzsi2, + one_cmplsi2_5200, subreghi1ashrdi_const32, ashrsi3, lshrsi3, + bsetmemqi, bsetmemqi_ext, bclrmemqi, bclrmemqi_ext, + beq, bne, bgt, blt, bordered, bunordered, buneq, bunge, bungt, bunle, + bunlt, bltgt, tablejump_internal, call, non_symbolic_call_value, + symbolic_call_value_jsr, symbolic_call_value_bsr, link): + Update or set attributes. + (stack_tie): New fake instruction. + + * config/m68k/m68k.h (TUNE_CFV4): New macro. + (m68k_sched_attr_size): Update declaration. + (m68k_sched_attr_type2): Remove. + (m68k_sched_address_bypass_p, m68k_sched_indexed_address_bypass_p): + Declare new bypass predicates. + + * config/m68k/m68k.c (m68k_sched_issue_rate, + m68k_sched_first_cycle_multipass_dfa_lookahead): Declare hook + implementations. + (TARGET_SCHED_ISSUE_RATE, + TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD): Override hooks. + (override_options): Handle scheduling for ColdFire V4 core. + (m68k_expand_prologue): Emit stack_tie. + (enum attr_op_type): Split value 'OP_TYPE_REG' to 'OP_TYPE_RN' and + 'OP_TYPE_FPN'. Update all uses. + (sched_guess_p): Remove. + (sched_address_type): Handle symbolic addresses. + (sched_get_operand): New static function. + (sched_operand_type): Merge into sched_attr_op_type. + (sched_attr_op_type): Handle FP registers, handle quick constants, + update. + (m68k_sched_attr_opx_type, m68k_sched_attr_opy_type): Update. + (m68k_sched_attr_size): Update. Move logic to ... + (sched_get_attr_size_int): New static function. + (sched_get_opxy_mem_type): New static function. + (m68k_sched_attr_op_mem): Update. + (m68k_sched_attr_type2): Remove. + (sched_cfv4_bypass_data): New static variable. + (m68k_sched_adjust_cost): Handle ColdFire V4 bypass. + (m68k_sched_issue_rate): Implement scheduler hook. + (struct _sched_ib: enabled_p): New field. + (m68k_sched_variable_issue): Update. Handle V4. + (SCHED_DUMP_TODO, SCHED_DUMP_DONE, SCHED_DUMP_NOTHING, + sched_dump_class_func_t, sched_dump_split_class, + sched_dump_dfa_guess_unit_code, sched_dump_dfa_state, + sched_dump_dfa_class, m68k_sched_dump): Remove. + (m68k_sched_first_cycle_multipass_dfa_lookahead): Implement scheduler + hook. + (m68k_sched_init_global): Remove statisctics dumping, introduce + sanity check that all instructions have pipeline reservations. Handle + ColdFire V4 core. + (m68k_sched_dfa_pre_advance_cycle, m68k_sched_dfa_post_advance_cycle): + Handle ColdFire V4 core. + (sched_mem_operand_p, sched_get_reg_operand, sched_get_mem_operand): + New static functions. + (m68k_sched_address_bypass_p): New bypass predicate. + (sched_get_indexed_address_scale): New static function. + (m68k_sched_indexed_address_bypass_p): New bypass predicate. + + * cf.md: Update comments. + (define_attr type2): Remove. Use 'type' attribute instead. + Update all uses. + (cf_ib): Rename to cfv123_ib. Update all uses. + (cf_oep): Rename to cfv123_oep. Update all uses. + (cf_chr): Rename to cfv123_chr. Update all uses. + (cf_mem): Rename to cfv123_mem. Update all uses. + (cf_mac): Move to more appropriate place. + (cfv123_guess): New automaton and cpu_unit. + (cfv123_*, cfv12_*, cfv1_*, cfv2_*, cfv3_*): Use type attribute. + Update uses of 'size' attribute. Handle before reload scheduling. + (cfv123_guess): New dummy reservation for unhandled instructions. + (cfv4_*): Pipeline description of ColdFire V4 core. + (ignore): New reservation to handle 'ignore' type. + 2008-05-07 Ian Lance Taylor <iant@google.com> PR middle-end/36013 diff --git a/gcc/config/m68k/cf.md b/gcc/config/m68k/cf.md index 546e995..7c4b37a 100644 --- a/gcc/config/m68k/cf.md +++ b/gcc/config/m68k/cf.md @@ -1,6 +1,6 @@ -;; ColdFire V1, V2 and V3 DFA description. +;; ColdFire V1, V2, V3 and V4/V4e DFA description. ;; Copyright (C) 2007 Free Software Foundation, Inc. -;; Contributed by CodeSourcery Inc. +;; Contributed by CodeSourcery Inc., www.codesourcery.com ;; ;; This file is part of GCC. ;; @@ -19,24 +19,12 @@ ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, ;; Boston, MA 02110-1301, USA. -;; Intruction types recognized by DFA. -;; This attribute correspond to type1 attribute with the exceptions below. -;; omove - optimized move. All explicit loads on cfv1 and long explicit -;; loads on cfv2 execute one cycle faster then they should. -;; Supposedly, that is due to combined instruction decoding -;; and address generation phases. -;; ??? To let genattrtab live, implement this attribute in C. -(define_attr "type2" - "alu, alu_reg, bcc, bra, call, jmp, lea, mul_l, mul_w, omove, pea, - rts, unlk, unknown" - (symbol_ref "m68k_sched_attr_type2 (insn)")) - ;; Instruction Buffer -(define_automaton "cf_ib") +(define_automaton "cfv123_ib") ;; These pseudo units are used to model instruction buffer of ColdFire cores. ;; Instruction of size N can be issued only when cf_ib_wN is available. -(define_cpu_unit "cf_ib_w1, cf_ib_w2, cf_ib_w3" "cf_ib") +(define_cpu_unit "cf_ib_w1, cf_ib_w2, cf_ib_w3" "cfv123_ib") ;; Instruction occupies 1 word in the instruction buffer. (define_reservation "cf_ib1" "cf_ib_w1") @@ -61,29 +49,38 @@ "cf_ib_w3|cf_ib_w2|cf_ib_w1") ;; Operand Execution Pipeline -(define_automaton "cf_oep") +(define_automaton "cfv123_oep") -(define_cpu_unit "cf_dsoc, cf_agex" "cf_oep") +(define_cpu_unit "cf_dsoc,cf_agex" "cfv123_oep") ;; A memory unit that is reffered to as 'certain hardware resources' in ;; ColdFire reference manuals. This unit remains occupied for two cycles ;; after last dsoc cycle of a store - hence there is a 2 cycle delay between ;; two consecutive stores. -(define_automaton "cf_chr") +(define_automaton "cfv123_chr") -(define_cpu_unit "cf_chr" "cf_chr") +(define_cpu_unit "cf_chr" "cfv123_chr") ;; Memory bus -(define_automaton "cf_mem") +(define_automaton "cfv123_mem") ;; When memory bus is subscribed, that implies that instruction buffer won't ;; get its portion this cycle. To model that we query if cf_mem unit is ;; subscribed and adjust number of prefetched instruction words accordingly. ;; -(define_query_cpu_unit "cf_mem1, cf_mem2" "cf_mem") +(define_query_cpu_unit "cf_mem1, cf_mem2" "cfv123_mem") (define_reservation "cf_mem" "cf_mem1+cf_mem2") +(define_automaton "cf_mac") + +(define_cpu_unit "cf_mac1,cf_mac2,cf_mac3,cf_mac4" + "cf_mac") + +(define_automaton "cfv123_guess") + +(define_query_cpu_unit "cfv123_guess" "cfv123_guess") + ;; Register to register move. ;; Takes 1 cycle. (define_reservation "cfv123_alu_00" @@ -235,11 +232,6 @@ (define_reservation "cfv3_mul_w_i0" "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,(cf_agex+cf_dsoc)*8,cf_agex") -(define_automaton "cf_mac") - -(define_cpu_unit "cf_mac1,cf_mac2,cf_mac3,cf_mac4" - "cf_mac") - ;; Long multiplication with mac. ;; Takes 5 cycles. (define_reservation "cfv123_mac_l_00" @@ -345,1184 +337,1918 @@ (define_insn_reservation "cfv123_alu_00_1" 1 (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") - (eq_attr "type2" "alu,alu_reg,omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - (eq_attr "op_mem" "00")) + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst, +move_l,tst_l")) + (eq_attr "op_mem" "00")) + (eq_attr "size" "1")) "cf_ib1+cfv123_alu_00") (define_insn_reservation "cfv123_alu_00_2" 1 (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") - (eq_attr "type2" "alu,alu_reg,omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "00")) + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst, +move_l,tst_l")) + (eq_attr "op_mem" "00")) + (eq_attr "size" "2")) "cf_ib2+cfv123_alu_00") (define_insn_reservation "cfv123_alu_00_3" 1 (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") - (eq_attr "type2" "alu,alu_reg,omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "00")) + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst, +move_l,tst_l")) + (eq_attr "op_mem" "00")) + (eq_attr "size" "3")) "cf_ib3+cfv123_alu_00") -(define_insn_reservation "cfv12_alu_10_1" 3 - (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "alu")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - (eq_attr "op_mem" "10")) +(define_insn_reservation "cfv1_alu_10_1" 3 + (and (and (and (eq_attr "cpu" "cfv1") + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift")) + (eq_attr "op_mem" "10")) + (eq_attr "size" "1")) "cf_ib1+cfv12_alu_10") -(define_insn_reservation "cfv12_alu_10_2" 3 - (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "alu")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "10")) +(define_insn_reservation "cfv1_alu_10_2" 3 + (and (and (and (eq_attr "cpu" "cfv1") + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift")) + (eq_attr "op_mem" "10")) + (eq_attr "size" "2")) "cf_ib2+cfv12_alu_10") -(define_insn_reservation "cfv12_alu_10_3" 3 - (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "alu")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "10")) +(define_insn_reservation "cfv1_alu_10_3" 3 + (and (and (and (eq_attr "cpu" "cfv1") + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift")) + (eq_attr "op_mem" "10")) + (eq_attr "size" "3")) "cf_ib3+cfv12_alu_10") -(define_insn_reservation "cfv12_omove_10_1" 2 - (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - (eq_attr "op_mem" "10")) +(define_insn_reservation "cfv1_omove_10_1" 2 + (and (and (and (eq_attr "cpu" "cfv1") + (eq_attr "type" " +clr,clr_l,mov3q_l,move,moveq_l,tst, +move_l,tst_l")) + (eq_attr "op_mem" "10")) + (eq_attr "size" "1")) "cf_ib1+cfv12_omove_10") -(define_insn_reservation "cfv12_omove_10_2" 2 - (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "10")) +(define_insn_reservation "cfv1_omove_10_2" 2 + (and (and (and (eq_attr "cpu" "cfv1") + (eq_attr "type" " +clr,clr_l,mov3q_l,move,moveq_l,tst, +move_l,tst_l")) + (eq_attr "op_mem" "10")) + (eq_attr "size" "2")) "cf_ib2+cfv12_omove_10") -(define_insn_reservation "cfv12_omove_10_3" 2 - (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "10")) +(define_insn_reservation "cfv1_omove_10_3" 2 + (and (and (and (eq_attr "cpu" "cfv1") + (eq_attr "type" " +clr,clr_l,mov3q_l,move,moveq_l,tst, +move_l,tst_l")) + (eq_attr "op_mem" "10")) + (eq_attr "size" "3")) + "cf_ib3+cfv12_omove_10") + +(define_insn_reservation "cfv2_alu_10_1" 3 + (and (and (and (eq_attr "cpu" "cfv2") + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst")) + (eq_attr "op_mem" "10")) + (eq_attr "size" "1")) + "cf_ib1+cfv12_alu_10") + +(define_insn_reservation "cfv2_alu_10_2" 3 + (and (and (and (eq_attr "cpu" "cfv2") + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst")) + (eq_attr "op_mem" "10")) + (eq_attr "size" "2")) + "cf_ib2+cfv12_alu_10") + +(define_insn_reservation "cfv2_alu_10_3" 3 + (and (and (and (eq_attr "cpu" "cfv2") + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst")) + (eq_attr "op_mem" "10")) + (eq_attr "size" "3")) + "cf_ib3+cfv12_alu_10") + +(define_insn_reservation "cfv2_omove_10_1" 2 + (and (and (and (eq_attr "cpu" "cfv2") + (eq_attr "type" " +move_l,tst_l")) + (eq_attr "op_mem" "10")) + (eq_attr "size" "1")) + "cf_ib1+cfv12_omove_10") + +(define_insn_reservation "cfv2_omove_10_2" 2 + (and (and (and (eq_attr "cpu" "cfv2") + (eq_attr "type" " +move_l,tst_l")) + (eq_attr "op_mem" "10")) + (eq_attr "size" "2")) + "cf_ib2+cfv12_omove_10") + +(define_insn_reservation "cfv2_omove_10_3" 2 + (and (and (and (eq_attr "cpu" "cfv2") + (eq_attr "type" " +move_l,tst_l")) + (eq_attr "op_mem" "10")) + (eq_attr "size" "3")) "cf_ib3+cfv12_omove_10") (define_insn_reservation "cfv3_alu_10_1" 4 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "alu")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - (eq_attr "op_mem" "10")) + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst")) + (eq_attr "op_mem" "10")) + (eq_attr "size" "1")) "cf_ib1+cfv3_alu_10") (define_insn_reservation "cfv3_alu_10_2" 4 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "alu")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "10")) + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst")) + (eq_attr "op_mem" "10")) + (eq_attr "size" "2")) "cf_ib2+cfv3_alu_10") (define_insn_reservation "cfv3_alu_10_3" 4 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "alu")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "10")) + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst")) + (eq_attr "op_mem" "10")) + (eq_attr "size" "3")) "cf_ib3+cfv3_alu_10") (define_insn_reservation "cfv3_omove_10_1" 3 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - (eq_attr "op_mem" "10")) + (eq_attr "type" " +move_l,tst_l")) + (eq_attr "op_mem" "10")) + (eq_attr "size" "1")) "cf_ib1+cfv3_omove_10") (define_insn_reservation "cfv3_omove_10_2" 3 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "10")) + (eq_attr "type" " +move_l,tst_l")) + (eq_attr "op_mem" "10")) + (eq_attr "size" "2")) "cf_ib2+cfv3_omove_10") (define_insn_reservation "cfv3_omove_10_3" 3 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "10")) + (eq_attr "type" " +move_l,tst_l")) + (eq_attr "op_mem" "10")) + (eq_attr "size" "3")) "cf_ib3+cfv3_omove_10") -(define_insn_reservation "cfv12_alu_i0_2" 4 - (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "alu")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "i0")) +(define_insn_reservation "cfv1_alu_i0_2" 4 + (and (and (and (eq_attr "cpu" "cfv1") + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift")) + (eq_attr "op_mem" "i0")) + (eq_attr "size" "1,2")) "cf_ib2+cfv12_alu_i0") -(define_insn_reservation "cfv12_alu_i0_3" 4 - (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "alu")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "i0")) +(define_insn_reservation "cfv1_alu_i0_3" 4 + (and (and (and (eq_attr "cpu" "cfv1") + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift")) + (eq_attr "op_mem" "i0")) + (eq_attr "size" "3")) "cf_ib3+cfv12_alu_i0") -(define_insn_reservation "cfv12_omove_i0_2" 3 - (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "i0")) +(define_insn_reservation "cfv1_omove_i0_2" 3 + (and (and (and (eq_attr "cpu" "cfv1") + (eq_attr "type" " +clr,clr_l,mov3q_l,move,moveq_l,tst, +move_l,tst_l")) + (eq_attr "op_mem" "i0")) + (eq_attr "size" "1,2")) "cf_ib2+cfv12_omove_i0") -(define_insn_reservation "cfv12_omove_i0_3" 3 - (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "i0")) +(define_insn_reservation "cfv1_omove_i0_3" 3 + (and (and (and (eq_attr "cpu" "cfv1") + (eq_attr "type" " +clr,clr_l,mov3q_l,move,moveq_l,tst, +move_l,tst_l")) + (eq_attr "op_mem" "i0")) + (eq_attr "size" "3")) + "cf_ib3+cfv12_omove_i0") + +(define_insn_reservation "cfv2_alu_i0_2" 4 + (and (and (and (eq_attr "cpu" "cfv2") + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst")) + (eq_attr "op_mem" "i0")) + (eq_attr "size" "1,2")) + "cf_ib2+cfv12_alu_i0") + +(define_insn_reservation "cfv2_alu_i0_3" 4 + (and (and (and (eq_attr "cpu" "cfv2") + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst")) + (eq_attr "op_mem" "i0")) + (eq_attr "size" "3")) + "cf_ib3+cfv12_alu_i0") + +(define_insn_reservation "cfv2_omove_i0_2" 3 + (and (and (and (eq_attr "cpu" "cfv2") + (eq_attr "type" " +move_l,tst_l")) + (eq_attr "op_mem" "i0")) + (eq_attr "size" "1,2")) + "cf_ib2+cfv12_omove_i0") + +(define_insn_reservation "cfv2_omove_i0_3" 3 + (and (and (and (eq_attr "cpu" "cfv2") + (eq_attr "type" " +move_l,tst_l")) + (eq_attr "op_mem" "i0")) + (eq_attr "size" "3")) "cf_ib3+cfv12_omove_i0") (define_insn_reservation "cfv3_alu_i0_2" 5 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "alu")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "i0")) + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst")) + (eq_attr "op_mem" "i0")) + (eq_attr "size" "1,2")) "cf_ib2+cfv3_alu_i0") (define_insn_reservation "cfv3_alu_i0_3" 5 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "alu")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "i0")) + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst")) + (eq_attr "op_mem" "i0")) + (eq_attr "size" "3")) "cf_ib3+cfv3_alu_i0") (define_insn_reservation "cfv3_omove_i0_2" 4 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "i0")) + (eq_attr "type" " +move_l,tst_l")) + (eq_attr "op_mem" "i0")) + (eq_attr "size" "1,2")) "cf_ib2+cfv3_omove_i0") (define_insn_reservation "cfv3_omove_i0_3" 4 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "i0")) + (eq_attr "type" " +move_l,tst_l")) + (eq_attr "op_mem" "i0")) + (eq_attr "size" "3")) "cf_ib3+cfv3_omove_i0") -(define_insn_reservation "cfv12_alu_01_1" 0 +(define_insn_reservation "cfv12_alu_01_1" 1 (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "alu,omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - (eq_attr "op_mem" "01")) + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst, +move_l,tst_l")) + (eq_attr "op_mem" "01")) + (eq_attr "size" "1")) "cf_ib1+cfv12_alu_01") -(define_insn_reservation "cfv12_alu_01_2" 0 +(define_insn_reservation "cfv12_alu_01_2" 1 (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "alu,omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "01")) + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst, +move_l,tst_l")) + (eq_attr "op_mem" "01")) + (eq_attr "size" "2")) "cf_ib2+cfv12_alu_01") -(define_insn_reservation "cfv12_alu_01_3" 0 +(define_insn_reservation "cfv12_alu_01_3" 1 (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "alu,omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "01")) + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst, +move_l,tst_l")) + (eq_attr "op_mem" "01")) + (eq_attr "size" "3")) "cf_ib3+cfv12_alu_01") -(define_insn_reservation "cfv3_alu_01_1" 0 +(define_insn_reservation "cfv3_alu_01_1" 1 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "alu,omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - (eq_attr "op_mem" "01")) + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst, +move_l,tst_l")) + (eq_attr "op_mem" "01")) + (eq_attr "size" "1")) "cf_ib1+cfv3_alu_01") -(define_insn_reservation "cfv3_alu_01_2" 0 +(define_insn_reservation "cfv3_alu_01_2" 1 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "alu,omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "01")) + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst, +move_l,tst_l")) + (eq_attr "op_mem" "01")) + (eq_attr "size" "2")) "cf_ib2+cfv3_alu_01") -(define_insn_reservation "cfv3_alu_01_3" 0 +(define_insn_reservation "cfv3_alu_01_3" 1 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "alu,omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "01")) + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst, +move_l,tst_l")) + (eq_attr "op_mem" "01")) + (eq_attr "size" "3")) "cf_ib3+cfv3_alu_01") -(define_insn_reservation "cfv12_alu_0i_2" 0 +(define_insn_reservation "cfv12_alu_0i_2" 2 (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "alu,omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "0i")) + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst, +move_l,tst_l")) + (eq_attr "op_mem" "0i")) + (eq_attr "size" "1,2")) "cf_ib2+cfv12_alu_0i") -(define_insn_reservation "cfv12_alu_0i_3" 0 +(define_insn_reservation "cfv12_alu_0i_3" 2 (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "alu,omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "0i")) + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst, +move_l,tst_l")) + (eq_attr "op_mem" "0i")) + (eq_attr "size" "3")) "cf_ib3+cfv12_alu_0i") -(define_insn_reservation "cfv3_alu_0i_2" 0 +(define_insn_reservation "cfv3_alu_0i_2" 2 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "alu,omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "0i")) + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst, +move_l,tst_l")) + (eq_attr "op_mem" "0i")) + (eq_attr "size" "1,2")) "cf_ib2+cfv3_alu_0i") -(define_insn_reservation "cfv3_alu_0i_3" 0 +(define_insn_reservation "cfv3_alu_0i_3" 2 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "alu,omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "0i")) + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst, +move_l,tst_l")) + (eq_attr "op_mem" "0i")) + (eq_attr "size" "3")) "cf_ib3+cfv3_alu_0i") -(define_insn_reservation "cfv12_alu_11_1" 0 - (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "alu")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - (eq_attr "op_mem" "11")) +(define_insn_reservation "cfv1_alu_11_1" 1 + (and (and (and (eq_attr "cpu" "cfv1") + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift")) + (eq_attr "op_mem" "11")) + (eq_attr "size" "1")) "cf_ib1+cfv12_alu_11") -(define_insn_reservation "cfv12_alu_11_2" 0 - (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "alu")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "11")) +(define_insn_reservation "cfv1_alu_11_2" 1 + (and (and (and (eq_attr "cpu" "cfv1") + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift")) + (eq_attr "op_mem" "11")) + (eq_attr "size" "2")) "cf_ib2+cfv12_alu_11") -(define_insn_reservation "cfv12_alu_11_3" 0 - (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "alu")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "11")) +(define_insn_reservation "cfv1_alu_11_3" 1 + (and (and (and (eq_attr "cpu" "cfv1") + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift")) + (eq_attr "op_mem" "11")) + (eq_attr "size" "3")) "cf_ib3+cfv12_alu_11") -(define_insn_reservation "cfv12_omove_11_1" 0 - (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - (eq_attr "op_mem" "11")) +(define_insn_reservation "cfv1_omove_11_1" 1 + (and (and (and (eq_attr "cpu" "cfv1") + (eq_attr "type" " +clr,clr_l,mov3q_l,move,moveq_l,tst, +move_l,tst_l")) + (eq_attr "op_mem" "11")) + (eq_attr "size" "1")) "cf_ib1+cfv12_omove_11") -(define_insn_reservation "cfv12_omove_11_2" 0 - (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "11")) +(define_insn_reservation "cfv1_omove_11_2" 1 + (and (and (and (eq_attr "cpu" "cfv1") + (eq_attr "type" " +clr,clr_l,mov3q_l,move,moveq_l,tst, +move_l,tst_l")) + (eq_attr "op_mem" "11")) + (eq_attr "size" "2")) "cf_ib2+cfv12_omove_11") -(define_insn_reservation "cfv12_omove_11_3" 0 - (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "11")) +(define_insn_reservation "cfv1_omove_11_3" 1 + (and (and (and (eq_attr "cpu" "cfv1") + (eq_attr "type" " +clr,clr_l,mov3q_l,move,moveq_l,tst, +move_l,tst_l")) + (eq_attr "op_mem" "11")) + (eq_attr "size" "3")) + "cf_ib3+cfv12_omove_11") + +(define_insn_reservation "cfv2_alu_11_1" 1 + (and (and (and (eq_attr "cpu" "cfv2") + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst")) + (eq_attr "op_mem" "11")) + (eq_attr "size" "1")) + "cf_ib1+cfv12_alu_11") + +(define_insn_reservation "cfv2_alu_11_2" 1 + (and (and (and (eq_attr "cpu" "cfv2") + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst")) + (eq_attr "op_mem" "11")) + (eq_attr "size" "2")) + "cf_ib2+cfv12_alu_11") + +(define_insn_reservation "cfv2_alu_11_3" 1 + (and (and (and (eq_attr "cpu" "cfv2") + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst")) + (eq_attr "op_mem" "11")) + (eq_attr "size" "3")) + "cf_ib3+cfv12_alu_11") + +(define_insn_reservation "cfv2_omove_11_1" 1 + (and (and (and (eq_attr "cpu" "cfv2") + (eq_attr "type" " +move_l,tst_l")) + (eq_attr "op_mem" "11")) + (eq_attr "size" "1")) + "cf_ib1+cfv12_omove_11") + +(define_insn_reservation "cfv2_omove_11_2" 1 + (and (and (and (eq_attr "cpu" "cfv2") + (eq_attr "type" " +move_l,tst_l")) + (eq_attr "op_mem" "11")) + (eq_attr "size" "2")) + "cf_ib2+cfv12_omove_11") + +(define_insn_reservation "cfv2_omove_11_3" 1 + (and (and (and (eq_attr "cpu" "cfv2") + (eq_attr "type" " +move_l,tst_l")) + (eq_attr "op_mem" "11")) + (eq_attr "size" "3")) "cf_ib3+cfv12_omove_11") -(define_insn_reservation "cfv3_alu_11_1" 0 +(define_insn_reservation "cfv3_alu_11_1" 1 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "alu")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - (eq_attr "op_mem" "11")) + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst")) + (eq_attr "op_mem" "11")) + (eq_attr "size" "1")) "cf_ib1+cfv3_alu_11") -(define_insn_reservation "cfv3_alu_11_2" 0 +(define_insn_reservation "cfv3_alu_11_2" 1 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "alu")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst")) + (eq_attr "size" "2")) (eq_attr "op_mem" "11")) "cf_ib2+cfv3_alu_11") -(define_insn_reservation "cfv3_alu_11_3" 0 +(define_insn_reservation "cfv3_alu_11_3" 1 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "alu")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "11")) + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst")) + (eq_attr "op_mem" "11")) + (eq_attr "size" "3")) "cf_ib3+cfv3_alu_11") -(define_insn_reservation "cfv3_omove_11_1" 0 +(define_insn_reservation "cfv3_omove_11_1" 1 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - (eq_attr "op_mem" "11")) + (eq_attr "type" " +move_l,tst_l")) + (eq_attr "op_mem" "11")) + (eq_attr "size" "1")) "cf_ib1+cfv3_omove_11") -(define_insn_reservation "cfv3_omove_11_2" 0 +(define_insn_reservation "cfv3_omove_11_2" 1 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) + (eq_attr "type" " +move_l,tst_l")) + (eq_attr "size" "2")) (eq_attr "op_mem" "11")) "cf_ib2+cfv3_omove_11") -(define_insn_reservation "cfv3_omove_11_3" 0 +(define_insn_reservation "cfv3_omove_11_3" 1 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "11")) + (eq_attr "type" " +move_l,tst_l")) + (eq_attr "op_mem" "11")) + (eq_attr "size" "3")) "cf_ib3+cfv3_omove_11") -(define_insn_reservation "cfv12_alu_i1_2" 0 - (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "alu")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "i1")) +(define_insn_reservation "cfv1_alu_i1_2" 2 + (and (and (and (eq_attr "cpu" "cfv1") + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift")) + (eq_attr "op_mem" "i1")) + (eq_attr "size" "1,2")) "cf_ib2+cfv12_alu_i1") -(define_insn_reservation "cfv12_alu_i1_3" 0 - (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "alu")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "i1")) +(define_insn_reservation "cfv1_alu_i1_3" 2 + (and (and (and (eq_attr "cpu" "cfv1") + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift")) + (eq_attr "op_mem" "i1")) + (eq_attr "size" "3")) "cf_ib3+cfv12_alu_i1") -(define_insn_reservation "cfv12_omove_i1_2" 0 - (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "i1")) +(define_insn_reservation "cfv1_omove_i1_2" 2 + (and (and (and (eq_attr "cpu" "cfv1") + (eq_attr "type" " +clr,clr_l,mov3q_l,move,moveq_l,tst, +move_l,tst_l")) + (eq_attr "op_mem" "i1")) + (eq_attr "size" "1,2")) "cf_ib2+cfv12_omove_i1") -(define_insn_reservation "cfv12_omove_i1_3" 0 - (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "i1")) +(define_insn_reservation "cfv1_omove_i1_3" 2 + (and (and (and (eq_attr "cpu" "cfv1") + (eq_attr "type" " +clr,clr_l,mov3q_l,move,moveq_l,tst, +move_l,tst_l")) + (eq_attr "op_mem" "i1")) + (eq_attr "size" "3")) "cf_ib3+cfv12_omove_i1") -(define_insn_reservation "cfv3_alu_i1_2" 0 +(define_insn_reservation "cfv2_alu_i1_2" 2 + (and (and (and (eq_attr "cpu" "cfv2") + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst")) + (eq_attr "op_mem" "i1")) + (eq_attr "size" "1,2")) + "cf_ib2+cfv12_alu_i1") + +(define_insn_reservation "cfv2_alu_i1_3" 2 + (and (and (and (eq_attr "cpu" "cfv2") + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst")) + (eq_attr "op_mem" "i1")) + (eq_attr "size" "3")) + "cf_ib3+cfv12_alu_i1") + +(define_insn_reservation "cfv2_omove_i1_2" 2 + (and (and (and (eq_attr "cpu" "cfv2") + (eq_attr "type" " +move_l,tst_l")) + (eq_attr "op_mem" "i1")) + (eq_attr "size" "1,2")) + "cf_ib2+cfv12_omove_i1") + +(define_insn_reservation "cfv2_omove_i1_3" 2 + (and (and (and (eq_attr "cpu" "cfv2") + (eq_attr "type" " +move_l,tst_l")) + (eq_attr "op_mem" "i1")) + (eq_attr "size" "3")) + "cf_ib3+cfv12_omove_i1") + +(define_insn_reservation "cfv3_alu_i1_2" 2 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "alu")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "i1")) + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst")) + (eq_attr "op_mem" "i1")) + (eq_attr "size" "1,2")) "cf_ib2+cfv3_alu_i1") -(define_insn_reservation "cfv3_alu_i1_3" 0 +(define_insn_reservation "cfv3_alu_i1_3" 2 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "alu")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "i1")) + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst")) + (eq_attr "op_mem" "i1")) + (eq_attr "size" "3")) "cf_ib3+cfv3_alu_i1") -(define_insn_reservation "cfv3_omove_i1_2" 0 +(define_insn_reservation "cfv3_omove_i1_2" 2 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "i1")) + (eq_attr "type" " +move_l,tst_l")) + (eq_attr "op_mem" "i1")) + (eq_attr "size" "1,2")) "cf_ib2+cfv3_omove_i1") -(define_insn_reservation "cfv3_omove_i1_3" 0 +(define_insn_reservation "cfv3_omove_i1_3" 2 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "i1")) + (eq_attr "type" " +move_l,tst_l")) + (eq_attr "op_mem" "i1")) + (eq_attr "size" "3")) "cf_ib3+cfv3_omove_i1") -(define_insn_reservation "cfv12_alu_1i_2" 0 - (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "alu")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "1i")) +(define_insn_reservation "cfv1_alu_1i_2" 2 + (and (and (and (eq_attr "cpu" "cfv1") + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift")) + (eq_attr "op_mem" "1i")) + (eq_attr "size" "1,2")) "cf_ib2+cfv12_alu_1i") -(define_insn_reservation "cfv12_alu_1i_3" 0 - (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "alu")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "1i")) +(define_insn_reservation "cfv1_alu_1i_3" 2 + (and (and (and (eq_attr "cpu" "cfv1") + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift")) + (eq_attr "op_mem" "1i")) + (eq_attr "size" "3")) "cf_ib3+cfv12_alu_1i") -(define_insn_reservation "cfv12_omove_1i_2" 0 - (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "1i")) +(define_insn_reservation "cfv1_omove_1i_2" 2 + (and (and (and (eq_attr "cpu" "cfv1") + (eq_attr "type" " +clr,clr_l,mov3q_l,move,moveq_l,tst, +move_l,tst_l")) + (eq_attr "op_mem" "1i")) + (eq_attr "size" "1,2")) "cf_ib2+cfv12_omove_1i") -(define_insn_reservation "cfv12_omove_1i_3" 0 - (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "1i")) +(define_insn_reservation "cfv1_omove_1i_3" 2 + (and (and (and (eq_attr "cpu" "cfv1") + (eq_attr "type" " +clr,clr_l,mov3q_l,move,moveq_l,tst, +move_l,tst_l")) + (eq_attr "op_mem" "1i")) + (eq_attr "size" "3")) + "cf_ib3+cfv12_omove_1i") + +(define_insn_reservation "cfv2_alu_1i_2" 2 + (and (and (and (eq_attr "cpu" "cfv2") + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst")) + (eq_attr "op_mem" "1i")) + (eq_attr "size" "1,2")) + "cf_ib2+cfv12_alu_1i") + +(define_insn_reservation "cfv2_alu_1i_3" 2 + (and (and (and (eq_attr "cpu" "cfv2") + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst")) + (eq_attr "op_mem" "1i")) + (eq_attr "size" "3")) + "cf_ib3+cfv12_alu_1i") + +(define_insn_reservation "cfv2_omove_1i_2" 2 + (and (and (and (eq_attr "cpu" "cfv2") + (eq_attr "type" " +move_l,tst_l")) + (eq_attr "op_mem" "1i")) + (eq_attr "size" "1,2")) + "cf_ib2+cfv12_omove_1i") + +(define_insn_reservation "cfv2_omove_1i_3" 2 + (and (and (and (eq_attr "cpu" "cfv2") + (eq_attr "type" " +move_l,tst_l")) + (eq_attr "op_mem" "1i")) + (eq_attr "size" "3")) "cf_ib3+cfv12_omove_1i") -(define_insn_reservation "cfv3_alu_1i_2" 0 +(define_insn_reservation "cfv3_alu_1i_2" 2 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "alu")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "1i")) + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst")) + (eq_attr "op_mem" "1i")) + (eq_attr "size" "1,2")) "cf_ib2+cfv3_alu_1i") -(define_insn_reservation "cfv3_alu_1i_3" 0 +(define_insn_reservation "cfv3_alu_1i_3" 2 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "alu")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "1i")) + (eq_attr "type" " +alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, +clr,clr_l,mov3q_l,move,moveq_l,tst")) + (eq_attr "op_mem" "1i")) + (eq_attr "size" "3")) "cf_ib3+cfv3_alu_1i") -(define_insn_reservation "cfv3_omove_1i_2" 0 +(define_insn_reservation "cfv3_omove_1i_2" 2 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "1i")) + (eq_attr "type" " +move_l,tst_l")) + (eq_attr "op_mem" "1i")) + (eq_attr "size" "1,2")) "cf_ib2+cfv3_omove_1i") -(define_insn_reservation "cfv3_omove_1i_3" 0 +(define_insn_reservation "cfv3_omove_1i_3" 2 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "omove")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "1i")) + (eq_attr "type" " +move_l,tst_l")) + (eq_attr "op_mem" "1i")) + (eq_attr "size" "3")) "cf_ib3+cfv3_omove_1i") (define_insn_reservation "cfv123_lea_10_1" 1 (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") - (eq_attr "type2" "lea")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "lea")) + (eq_attr "op_mem" "10,11,1i")) + (eq_attr "size" "1")) "cf_ib1+cfv123_lea_10") (define_insn_reservation "cfv123_lea_10_2" 1 (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") - (eq_attr "type2" "lea")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "lea")) + (eq_attr "op_mem" "10,11,1i")) + (eq_attr "size" "2")) "cf_ib2+cfv123_lea_10") (define_insn_reservation "cfv123_lea_10_3" 1 (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") - (eq_attr "type2" "lea")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "lea")) + (eq_attr "op_mem" "10,11,1i")) + (eq_attr "size" "3")) "cf_ib3+cfv123_lea_10") (define_insn_reservation "cfv123_lea_i0_2" 2 (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") - (eq_attr "type2" "lea")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "i0")) + (eq_attr "type" "lea")) + (eq_attr "op_mem" "i0,i1")) + (eq_attr "size" "1,2")) "cf_ib2+cfv123_lea_i0") (define_insn_reservation "cfv123_lea_i0_3" 2 (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") - (eq_attr "type2" "lea")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "i0")) + (eq_attr "type" "lea")) + (eq_attr "op_mem" "i0,i1")) + (eq_attr "size" "3")) "cf_ib3+cfv123_lea_i0") -(define_insn_reservation "cfv12_pea_11_1" 0 +(define_insn_reservation "cfv12_pea_11_1" 1 (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "pea")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - (eq_attr "op_mem" "11")) + (eq_attr "type" "pea")) + (eq_attr "op_mem" "11")) + (eq_attr "size" "1")) "cf_ib1+cfv12_pea_11") -(define_insn_reservation "cfv12_pea_11_2" 0 +(define_insn_reservation "cfv12_pea_11_2" 1 (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "pea")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "11")) + (eq_attr "type" "pea")) + (eq_attr "op_mem" "11")) + (eq_attr "size" "2")) "cf_ib2+cfv12_pea_11") -(define_insn_reservation "cfv12_pea_11_3" 0 +(define_insn_reservation "cfv12_pea_11_3" 1 (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "pea")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "11")) + (eq_attr "type" "pea")) + (eq_attr "op_mem" "11")) + (eq_attr "size" "3")) "cf_ib3+cfv12_pea_11") -(define_insn_reservation "cfv3_pea_11_1" 0 +(define_insn_reservation "cfv3_pea_11_1" 1 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "pea")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - (eq_attr "op_mem" "11")) + (eq_attr "type" "pea")) + (eq_attr "op_mem" "11")) + (eq_attr "size" "1")) "cf_ib1+cfv3_pea_11") -(define_insn_reservation "cfv3_pea_11_2" 0 +(define_insn_reservation "cfv3_pea_11_2" 1 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "pea")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "11")) + (eq_attr "type" "pea")) + (eq_attr "op_mem" "11")) + (eq_attr "size" "2")) "cf_ib2+cfv3_pea_11") -(define_insn_reservation "cfv3_pea_11_3" 0 +(define_insn_reservation "cfv3_pea_11_3" 1 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "pea")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "11")) + (eq_attr "type" "pea")) + (eq_attr "op_mem" "11")) + (eq_attr "size" "3")) "cf_ib3+cfv3_pea_11") -(define_insn_reservation "cfv12_pea_i1_2" 0 +(define_insn_reservation "cfv12_pea_i1_2" 2 (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "pea")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "i1")) + (eq_attr "type" "pea")) + (eq_attr "op_mem" "i1")) + (eq_attr "size" "1,2")) "cf_ib2+cfv12_pea_i1") -(define_insn_reservation "cfv12_pea_i1_3" 0 +(define_insn_reservation "cfv12_pea_i1_3" 2 (and (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "pea")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "i1")) + (eq_attr "type" "pea")) + (eq_attr "op_mem" "i1")) + (eq_attr "size" "3")) "cf_ib3+cfv12_pea_i1") -(define_insn_reservation "cfv3_pea_i1_2" 0 +(define_insn_reservation "cfv3_pea_i1_2" 2 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "pea")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "i1")) + (eq_attr "type" "pea")) + (eq_attr "op_mem" "i1")) + (eq_attr "size" "1,2")) "cf_ib2+cfv3_pea_i1") -(define_insn_reservation "cfv3_pea_i1_3" 0 +(define_insn_reservation "cfv3_pea_i1_3" 2 (and (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "pea")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "i1")) + (eq_attr "type" "pea")) + (eq_attr "op_mem" "i1")) + (eq_attr "size" "3")) "cf_ib3+cfv3_pea_i1") (define_insn_reservation "cfv123_mul_l_00_1" 18 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") (eq_attr "mac" "no")) - (eq_attr "type2" "mul_l")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - (eq_attr "op_mem" "00")) + (eq_attr "type" "mul_l")) + (eq_attr "op_mem" "00,01,0i")) + (eq_attr "size" "1")) "cf_ib1+cfv123_mul_l_00") (define_insn_reservation "cfv123_mul_l_00_2" 18 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") (eq_attr "mac" "no")) - (eq_attr "type2" "mul_l")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "00")) + (eq_attr "type" "mul_l")) + (eq_attr "op_mem" "00,01,0i")) + (eq_attr "size" "2")) "cf_ib2+cfv123_mul_l_00") (define_insn_reservation "cfv123_mul_l_00_3" 18 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") (eq_attr "mac" "no")) - (eq_attr "type2" "mul_l")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "00")) + (eq_attr "type" "mul_l")) + (eq_attr "op_mem" "00,01,0i")) + (eq_attr "size" "3")) "cf_ib3+cfv123_mul_l_00") (define_insn_reservation "cfv123_mul_w_00_1" 9 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") (eq_attr "mac" "no")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - (eq_attr "op_mem" "00")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "00,01,0i")) + (eq_attr "size" "1")) "cf_ib1+cfv123_mul_w_00") (define_insn_reservation "cfv123_mul_w_00_2" 9 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") (eq_attr "mac" "no")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "00")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "00,01,0i")) + (eq_attr "size" "2")) "cf_ib2+cfv123_mul_w_00") (define_insn_reservation "cfv123_mul_w_00_3" 9 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") (eq_attr "mac" "no")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "00")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "00,01,0i")) + (eq_attr "size" "3")) "cf_ib3+cfv123_mul_w_00") (define_insn_reservation "cfv12_mul_l_10_1" 20 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") (eq_attr "mac" "no")) - (eq_attr "type2" "mul_l")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_l")) + (eq_attr "op_mem" "10,i0,i1,11,1i")) + (eq_attr "size" "1")) "cf_ib1+cfv12_mul_l_10") (define_insn_reservation "cfv12_mul_l_10_2" 20 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") (eq_attr "mac" "no")) - (eq_attr "type2" "mul_l")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_l")) + (eq_attr "op_mem" "10,i0,i1,11,1i")) + (eq_attr "size" "2")) "cf_ib2+cfv12_mul_l_10") (define_insn_reservation "cfv12_mul_l_10_3" 20 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") (eq_attr "mac" "no")) - (eq_attr "type2" "mul_l")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_l")) + (eq_attr "op_mem" "10,i0,i1,11,1i")) + (eq_attr "size" "3")) "cf_ib3+cfv12_mul_l_10") (define_insn_reservation "cfv3_mul_l_10_1" 21 (and (and (and (and (eq_attr "cpu" "cfv3") (eq_attr "mac" "no")) - (eq_attr "type2" "mul_l")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_l")) + (eq_attr "op_mem" "10,i0,i1,11,1i")) + (eq_attr "size" "1")) "cf_ib1+cfv3_mul_l_10") (define_insn_reservation "cfv3_mul_l_10_2" 21 (and (and (and (and (eq_attr "cpu" "cfv3") (eq_attr "mac" "no")) - (eq_attr "type2" "mul_l")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_l")) + (eq_attr "op_mem" "10,i0,i1,11,1i")) + (eq_attr "size" "2")) "cf_ib2+cfv3_mul_l_10") (define_insn_reservation "cfv3_mul_l_10_3" 21 (and (and (and (and (eq_attr "cpu" "cfv3") (eq_attr "mac" "no")) - (eq_attr "type2" "mul_l")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_l")) + (eq_attr "op_mem" "10,i0,i1,11,1i")) + (eq_attr "size" "3")) "cf_ib3+cfv3_mul_l_10") (define_insn_reservation "cfv12_mul_w_10_1" 11 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") (eq_attr "mac" "no")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "10,11,1i")) + (eq_attr "size" "1")) "cf_ib1+cfv12_mul_w_10") (define_insn_reservation "cfv12_mul_w_10_2" 11 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") (eq_attr "mac" "no")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "10,11,1i")) + (eq_attr "size" "2")) "cf_ib2+cfv12_mul_w_10") (define_insn_reservation "cfv12_mul_w_10_3" 11 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") (eq_attr "mac" "no")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "10,11,1i")) + (eq_attr "size" "3")) "cf_ib3+cfv12_mul_w_10") (define_insn_reservation "cfv3_mul_w_10_1" 12 (and (and (and (and (eq_attr "cpu" "cfv3") (eq_attr "mac" "no")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "10,11,1i")) + (eq_attr "size" "1")) "cf_ib1+cfv3_mul_w_10") (define_insn_reservation "cfv3_mul_w_10_2" 12 (and (and (and (and (eq_attr "cpu" "cfv3") (eq_attr "mac" "no")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "10,11,1i")) + (eq_attr "size" "2")) "cf_ib2+cfv3_mul_w_10") (define_insn_reservation "cfv3_mul_w_10_3" 12 (and (and (and (and (eq_attr "cpu" "cfv3") (eq_attr "mac" "no")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "10,11,1i")) + (eq_attr "size" "3")) "cf_ib3+cfv3_mul_w_10") (define_insn_reservation "cfv12_mul_w_i0_2" 12 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") (eq_attr "mac" "no")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "i0")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "i0,i1")) + (eq_attr "size" "1,2")) "cf_ib2+cfv12_mul_w_i0") (define_insn_reservation "cfv12_mul_w_i0_3" 12 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") (eq_attr "mac" "no")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "i0")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "i0,i1")) + (eq_attr "size" "3")) "cf_ib3+cfv12_mul_w_i0") - (define_insn_reservation "cfv3_mul_w_i0_2" 13 (and (and (and (and (eq_attr "cpu" "cfv3") (eq_attr "mac" "no")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "i0")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "i0,i1")) + (eq_attr "size" "1,2")) "cf_ib2+cfv3_mul_w_i0") (define_insn_reservation "cfv3_mul_w_i0_3" 13 (and (and (and (and (eq_attr "cpu" "cfv3") (eq_attr "mac" "no")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "i0")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "i0,i1")) + (eq_attr "size" "3")) "cf_ib3+cfv3_mul_w_i0") (define_insn_reservation "cfv123_mac_l_00_1" 5 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") (eq_attr "mac" "cf_mac")) - (eq_attr "type2" "mul_l")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - (eq_attr "op_mem" "00")) + (eq_attr "type" "mul_l")) + (eq_attr "op_mem" "00,01,0i")) + (eq_attr "size" "1")) "cf_ib1+cfv123_mac_l_00") (define_insn_reservation "cfv123_mac_l_00_2" 5 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") (eq_attr "mac" "cf_mac")) - (eq_attr "type2" "mul_l")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "00")) + (eq_attr "type" "mul_l")) + (eq_attr "op_mem" "00,01,0i")) + (eq_attr "size" "2")) "cf_ib2+cfv123_mac_l_00") (define_insn_reservation "cfv123_mac_l_00_3" 5 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") (eq_attr "mac" "cf_mac")) - (eq_attr "type2" "mul_l")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "00")) + (eq_attr "type" "mul_l")) + (eq_attr "op_mem" "00,01,0i")) + (eq_attr "size" "3")) "cf_ib3+cfv123_mac_l_00") (define_insn_reservation "cfv123_mac_w_00_1" 3 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") (eq_attr "mac" "cf_mac")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - (eq_attr "op_mem" "00")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "00,01,0i")) + (eq_attr "size" "1")) "cf_ib1+cfv123_mac_w_00") (define_insn_reservation "cfv123_mac_w_00_2" 3 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") (eq_attr "mac" "cf_mac")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "00")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "00,01,0i")) + (eq_attr "size" "2")) "cf_ib2+cfv123_mac_w_00") (define_insn_reservation "cfv123_mac_w_00_3" 3 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") (eq_attr "mac" "cf_mac")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "00")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "00,01,0i")) + (eq_attr "size" "3")) "cf_ib3+cfv123_mac_w_00") (define_insn_reservation "cfv12_mac_l_10_1" 7 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") (eq_attr "mac" "cf_mac")) - (eq_attr "type2" "mul_l")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_l")) + (eq_attr "op_mem" "10,i0,i1,11,1i")) + (eq_attr "size" "1")) "cf_ib1+cfv12_mac_l_10") (define_insn_reservation "cfv12_mac_l_10_2" 7 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") (eq_attr "mac" "cf_mac")) - (eq_attr "type2" "mul_l")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_l")) + (eq_attr "op_mem" "10,i0,i1,11,1i")) + (eq_attr "size" "2")) "cf_ib2+cfv12_mac_l_10") (define_insn_reservation "cfv12_mac_l_10_3" 7 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") (eq_attr "mac" "cf_mac")) - (eq_attr "type2" "mul_l")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_l")) + (eq_attr "op_mem" "10,i0,i1,11,1i")) + (eq_attr "size" "3")) "cf_ib3+cfv12_mac_l_10") (define_insn_reservation "cfv3_mac_l_10_1" 8 (and (and (and (and (eq_attr "cpu" "cfv3") (eq_attr "mac" "cf_mac")) - (eq_attr "type2" "mul_l")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_l")) + (eq_attr "op_mem" "10,i0,i1,11,1i")) + (eq_attr "size" "1")) "cf_ib1+cfv3_mac_l_10") (define_insn_reservation "cfv3_mac_l_10_2" 8 (and (and (and (and (eq_attr "cpu" "cfv3") (eq_attr "mac" "cf_mac")) - (eq_attr "type2" "mul_l")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_l")) + (eq_attr "op_mem" "10,i0,i1,11,1i")) + (eq_attr "size" "2")) "cf_ib2+cfv3_mac_l_10") (define_insn_reservation "cfv3_mac_l_10_3" 8 (and (and (and (and (eq_attr "cpu" "cfv3") (eq_attr "mac" "cf_mac")) - (eq_attr "type2" "mul_l")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_l")) + (eq_attr "op_mem" "10,i0,i1,11,1i")) + (eq_attr "size" "3")) "cf_ib3+cfv3_mac_l_10") (define_insn_reservation "cfv12_mac_w_10_1" 5 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") (eq_attr "mac" "cf_mac")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "10,11,1i")) + (eq_attr "size" "1")) "cf_ib1+cfv12_mac_w_10") (define_insn_reservation "cfv12_mac_w_10_2" 5 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") (eq_attr "mac" "cf_mac")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "10,11,1i")) + (eq_attr "size" "2")) "cf_ib2+cfv12_mac_w_10") (define_insn_reservation "cfv12_mac_w_10_3" 5 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") (eq_attr "mac" "cf_mac")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "10,11,1i")) + (eq_attr "size" "3")) "cf_ib3+cfv12_mac_w_10") (define_insn_reservation "cfv3_mac_w_10_1" 6 (and (and (and (and (eq_attr "cpu" "cfv3") (eq_attr "mac" "cf_mac")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "10,11,1i")) + (eq_attr "size" "1")) "cf_ib1+cfv3_mac_w_10") (define_insn_reservation "cfv3_mac_w_10_2" 6 (and (and (and (and (eq_attr "cpu" "cfv3") (eq_attr "mac" "cf_mac")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "10,11,1i")) + (eq_attr "size" "2")) "cf_ib2+cfv3_mac_w_10") (define_insn_reservation "cfv3_mac_w_10_3" 6 (and (and (and (and (eq_attr "cpu" "cfv3") (eq_attr "mac" "cf_mac")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "10,11,1i")) + (eq_attr "size" "3")) "cf_ib3+cfv3_mac_w_10") (define_insn_reservation "cfv12_mac_w_i0_2" 6 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") (eq_attr "mac" "cf_mac")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "i0")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "i0,i1")) + (eq_attr "size" "1,2")) "cf_ib2+cfv12_mac_w_i0") (define_insn_reservation "cfv12_mac_w_i0_3" 6 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") (eq_attr "mac" "cf_mac")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "i0")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "i0,i1")) + (eq_attr "size" "3")) "cf_ib3+cfv12_mac_w_i0") (define_insn_reservation "cfv3_mac_w_i0_2" 7 (and (and (and (and (eq_attr "cpu" "cfv3") (eq_attr "mac" "cf_mac")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "i0")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "i0,i1")) + (eq_attr "size" "1,2")) "cf_ib2+cfv3_mac_w_i0") (define_insn_reservation "cfv3_mac_w_i0_3" 7 (and (and (and (and (eq_attr "cpu" "cfv3") (eq_attr "mac" "cf_mac")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "i0")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "i0,i1")) + (eq_attr "size" "3")) "cf_ib3+cfv3_mac_w_i0") (define_insn_reservation "cfv123_emac_00_1" 4 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") (eq_attr "mac" "cf_emac")) - (eq_attr "type2" "mul_l,mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - (eq_attr "op_mem" "00")) + (eq_attr "type" "mul_l,mul_w")) + (eq_attr "op_mem" "00,01,0i")) + (eq_attr "size" "1")) "cf_ib1+cfv123_emac_00") (define_insn_reservation "cfv123_emac_00_2" 4 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") (eq_attr "mac" "cf_emac")) - (eq_attr "type2" "mul_l,mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "00")) + (eq_attr "type" "mul_l,mul_w")) + (eq_attr "op_mem" "00,01,0i")) + (eq_attr "size" "2")) "cf_ib2+cfv123_emac_00") (define_insn_reservation "cfv123_emac_00_3" 4 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") (eq_attr "mac" "cf_emac")) - (eq_attr "type2" "mul_l,mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "00")) + (eq_attr "type" "mul_l,mul_w")) + (eq_attr "op_mem" "00,01,0i")) + (eq_attr "size" "3")) "cf_ib3+cfv123_emac_00") -(define_insn_reservation "cfv12_emac_10_1" 6 +(define_insn_reservation "cfv12_emac_l_10_1" 6 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") (eq_attr "mac" "cf_emac")) - (eq_attr "type2" "mul_l,mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_l")) + (eq_attr "op_mem" "10,i0,i1,11,1i")) + (eq_attr "size" "1")) "cf_ib1+cfv12_emac_10") -(define_insn_reservation "cfv12_emac_10_2" 6 +(define_insn_reservation "cfv12_emac_l_10_2" 6 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") (eq_attr "mac" "cf_emac")) - (eq_attr "type2" "mul_l,mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_l")) + (eq_attr "op_mem" "10,i0,i1,11,1i")) + (eq_attr "size" "2")) "cf_ib2+cfv12_emac_10") -(define_insn_reservation "cfv12_emac_10_3" 6 +(define_insn_reservation "cfv12_emac_l_10_3" 6 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") (eq_attr "mac" "cf_emac")) - (eq_attr "type2" "mul_l,mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_l")) + (eq_attr "op_mem" "10,i0,i1,11,1i")) + (eq_attr "size" "3")) "cf_ib3+cfv12_emac_10") -(define_insn_reservation "cfv3_emac_10_1" 7 +(define_insn_reservation "cfv3_emac_l_10_1" 7 (and (and (and (and (eq_attr "cpu" "cfv3") (eq_attr "mac" "cf_emac")) - (eq_attr "type2" "mul_l,mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_l")) + (eq_attr "op_mem" "10,i0,i1,11,1i")) + (eq_attr "size" "1")) "cf_ib1+cfv3_emac_10") -(define_insn_reservation "cfv3_emac_10_2" 7 +(define_insn_reservation "cfv3_emac_l_10_2" 7 (and (and (and (and (eq_attr "cpu" "cfv3") (eq_attr "mac" "cf_emac")) - (eq_attr "type2" "mul_l,mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_l")) + (eq_attr "op_mem" "10,i0,i1,11,1i")) + (eq_attr "size" "2")) "cf_ib2+cfv3_emac_10") -(define_insn_reservation "cfv3_emac_10_3" 7 +(define_insn_reservation "cfv3_emac_l_10_3" 7 (and (and (and (and (eq_attr "cpu" "cfv3") (eq_attr "mac" "cf_emac")) - (eq_attr "type2" "mul_l,mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "10")) + (eq_attr "type" "mul_l")) + (eq_attr "op_mem" "10,i0,i1,11,1i")) + (eq_attr "size" "3")) + "cf_ib3+cfv3_emac_10") + +(define_insn_reservation "cfv12_emac_w_10_1" 6 + (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") + (eq_attr "mac" "cf_emac")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "10,11,1i")) + (eq_attr "size" "1")) + "cf_ib1+cfv12_emac_10") + +(define_insn_reservation "cfv12_emac_w_10_2" 6 + (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") + (eq_attr "mac" "cf_emac")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "10,11,1i")) + (eq_attr "size" "2")) + "cf_ib2+cfv12_emac_10") + +(define_insn_reservation "cfv12_emac_w_10_3" 6 + (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") + (eq_attr "mac" "cf_emac")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "10,11,1i")) + (eq_attr "size" "3")) + "cf_ib3+cfv12_emac_10") + +(define_insn_reservation "cfv3_emac_w_10_1" 7 + (and (and (and (and (eq_attr "cpu" "cfv3") + (eq_attr "mac" "cf_emac")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "10,11,1i")) + (eq_attr "size" "1")) + "cf_ib1+cfv3_emac_10") + +(define_insn_reservation "cfv3_emac_w_10_2" 7 + (and (and (and (and (eq_attr "cpu" "cfv3") + (eq_attr "mac" "cf_emac")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "10,11,1i")) + (eq_attr "size" "2")) + "cf_ib2+cfv3_emac_10") + +(define_insn_reservation "cfv3_emac_w_10_3" 7 + (and (and (and (and (eq_attr "cpu" "cfv3") + (eq_attr "mac" "cf_emac")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "10,11,1i")) + (eq_attr "size" "3")) "cf_ib3+cfv3_emac_10") (define_insn_reservation "cfv12_emac_w_i0_2" 7 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") (eq_attr "mac" "cf_emac")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "i0")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "i0,i1")) + (eq_attr "size" "1,2")) "cf_ib2+cfv12_emac_w_i0") (define_insn_reservation "cfv12_emac_w_i0_3" 7 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") (eq_attr "mac" "cf_emac")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "i0")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "i0,i1")) + (eq_attr "size" "3")) "cf_ib3+cfv12_emac_w_i0") (define_insn_reservation "cfv3_emac_w_i0_2" 8 (and (and (and (and (eq_attr "cpu" "cfv3") (eq_attr "mac" "cf_emac")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - (eq_attr "op_mem" "i0")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "i0,i1")) + (eq_attr "size" "1,2")) "cf_ib2+cfv3_emac_w_i0") (define_insn_reservation "cfv3_emac_w_i0_3" 8 (and (and (and (and (eq_attr "cpu" "cfv3") (eq_attr "mac" "cf_emac")) - (eq_attr "type2" "mul_w")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - (eq_attr "op_mem" "i0")) + (eq_attr "type" "mul_w")) + (eq_attr "op_mem" "i0,i1")) + (eq_attr "size" "3")) "cf_ib3+cfv3_emac_w_i0") -(define_insn_reservation "cfv12_rts_1" 5 - (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "rts")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) +(define_insn_reservation "cfv12_rts" 5 + (and (eq_attr "cpu" "cfv1,cfv2") + (eq_attr "type" "rts")) "cf_ib1+cfv12_rts") -(define_insn_reservation "cfv3_rts_1" 8 - (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "rts")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) +(define_insn_reservation "cfv3_rts" 8 + (and (eq_attr "cpu" "cfv3") + (eq_attr "type" "rts")) "cf_ib1+cfv3_rts") (define_insn_reservation "cfv12_call_1" 3 (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "call")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) + (eq_attr "type" "bsr,jsr")) + (eq_attr "size" "1")) "cf_ib1+cfv12_call") (define_insn_reservation "cfv12_call_2" 3 (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "call")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) + (eq_attr "type" "bsr,jsr")) + (eq_attr "size" "2")) "cf_ib2+cfv12_call") (define_insn_reservation "cfv12_call_3" 3 (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "call")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) + (eq_attr "type" "bsr,jsr")) + (eq_attr "size" "3")) "cf_ib3+cfv12_call") (define_insn_reservation "cfv3_call_1" 1 (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "call")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) + (eq_attr "type" "bsr,jsr")) + (eq_attr "size" "1")) "cf_ib1+cfv3_call") (define_insn_reservation "cfv3_call_2" 1 (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "call")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) + (eq_attr "type" "bsr,jsr")) + (eq_attr "size" "2")) "cf_ib2+cfv3_call") (define_insn_reservation "cfv3_call_3" 1 (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "call")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) + (eq_attr "type" "bsr,jsr")) + (eq_attr "size" "3")) "cf_ib3+cfv3_call") (define_insn_reservation "cfv12_bcc_1" 2 (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "bcc")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) + (eq_attr "type" "bcc")) + (eq_attr "size" "1")) "cf_ib1+cfv12_bcc") (define_insn_reservation "cfv12_bcc_2" 2 (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "bcc")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) + (eq_attr "type" "bcc")) + (eq_attr "size" "2")) "cf_ib2+cfv12_bcc") (define_insn_reservation "cfv12_bcc_3" 2 (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "bcc")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) + (eq_attr "type" "bcc")) + (eq_attr "size" "3")) "cf_ib3+cfv12_bcc") (define_insn_reservation "cfv3_bcc_1" 1 (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "bcc")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) + (eq_attr "type" "bcc")) + (eq_attr "size" "1")) "cf_ib1+cfv3_bcc") (define_insn_reservation "cfv3_bcc_2" 1 (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "bcc")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) + (eq_attr "type" "bcc")) + (eq_attr "size" "2")) "cf_ib2+cfv3_bcc") (define_insn_reservation "cfv3_bcc_3" 1 (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "bcc")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) + (eq_attr "type" "bcc")) + (eq_attr "size" "3")) "cf_ib3+cfv3_bcc") (define_insn_reservation "cfv12_bra_1" 2 (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "bra")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) + (eq_attr "type" "bra")) + (eq_attr "size" "1")) "cf_ib1+cfv12_bra") (define_insn_reservation "cfv12_bra_2" 2 (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "bra")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) + (eq_attr "type" "bra")) + (eq_attr "size" "2")) "cf_ib2+cfv12_bra") (define_insn_reservation "cfv12_bra_3" 2 (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "bra")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) + (eq_attr "type" "bra")) + (eq_attr "size" "3")) "cf_ib3+cfv12_bra") (define_insn_reservation "cfv3_bra_1" 1 (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "bra")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) + (eq_attr "type" "bra")) + (eq_attr "size" "1")) "cf_ib1+cfv3_bra") (define_insn_reservation "cfv3_bra_2" 1 (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "bra")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) + (eq_attr "type" "bra")) + (eq_attr "size" "2")) "cf_ib2+cfv3_bra") (define_insn_reservation "cfv3_bra_3" 1 (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "bra")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) + (eq_attr "type" "bra")) + (eq_attr "size" "3")) "cf_ib3+cfv3_bra") (define_insn_reservation "cfv12_jmp_1" 3 (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "jmp")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) + (eq_attr "type" "jmp")) + (eq_attr "size" "1")) "cf_ib1+cfv12_jmp") (define_insn_reservation "cfv12_jmp_2" 3 (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "jmp")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) + (eq_attr "type" "jmp")) + (eq_attr "size" "2")) "cf_ib2+cfv12_jmp") (define_insn_reservation "cfv12_jmp_3" 3 (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "jmp")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) + (eq_attr "type" "jmp")) + (eq_attr "size" "3")) "cf_ib3+cfv12_jmp") (define_insn_reservation "cfv3_jmp_1" 5 (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "jmp")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) + (eq_attr "type" "jmp")) + (eq_attr "size" "1")) "cf_ib1+cfv3_jmp") (define_insn_reservation "cfv3_jmp_2" 5 (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "jmp")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) + (eq_attr "type" "jmp")) + (eq_attr "size" "2")) "cf_ib2+cfv3_jmp") (define_insn_reservation "cfv3_jmp_3" 5 (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "jmp")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) + (eq_attr "type" "jmp")) + (eq_attr "size" "3")) "cf_ib3+cfv3_jmp") -;; Misc reservations. - -(define_insn_reservation "cfv12_unlk_1" 2 - (and (and (eq_attr "cpu" "cfv1,cfv2") - (eq_attr "type2" "unlk")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) +(define_insn_reservation "cfv12_unlk" 2 + (and (eq_attr "cpu" "cfv1,cfv2") + (eq_attr "type" "unlk")) "cf_ib1+cfv12_alu_10") -(define_insn_reservation "cfv3_unlk_1" 3 - (and (and (eq_attr "cpu" "cfv3") - (eq_attr "type2" "unlk")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) +(define_insn_reservation "cfv3_unlk" 3 + (and (eq_attr "cpu" "cfv3") + (eq_attr "type" "unlk")) "cf_ib1+cfv3_alu_10") -;; This automaton is used to gather statistics on insns that need reservations. -(define_automaton "cf_guess") +;; Dummy reservation for instructions that are not handled. +(define_insn_reservation "cfv123_guess" 3 + (and (eq_attr "cpu" "cfv1,cfv2,cfv3") + (eq_attr "type" "falu,fbcc,fcmp,fdiv,fmove,fmul,fneg,fsqrt,ftst, + div_w,div_l,link,mvsz,nop,trap,unknown")) + "cf_ib3+cfv123_guess+cf_dsoc+cf_agex+cf_mem") -(define_query_cpu_unit "cf_guess" "cf_guess") +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; Dummy reservation for instructions that are not handled yet. +;; Below is pipeline description of ColdFire V4 core. +;; It is substantially different from the description of V1, V2 or V3 cores, +;; primarily due to no need to model the instruction buffer. +;; +;; V4 pipeline model uses a completely separate set of cpu units. + +;; Operand Execution Pipeline. +(define_automaton "cfv4_oep") + +(define_cpu_unit "cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_da" + "cfv4_oep") + +;; This automaton is used to support CFv4 dual-issue. +(define_automaton "cfv4_ds") + +;; V4 has 3 cases of dual-issue. +;; After issuing a cfv4_pOEPx instruction, it'll be possible to issue +;; a cfv4_sOEPx instruction on the same cycle (see final_presence_sets below). +(define_cpu_unit "cfv4_pOEP1,cfv4_sOEP1, + cfv4_pOEP2,cfv4_sOEP2, + cfv4_pOEP3,cfv4_sOEP3" "cfv4_ds") + +(final_presence_set "cfv4_sOEP1" "cfv4_pOEP1") +(final_presence_set "cfv4_sOEP2" "cfv4_pOEP2") +(final_presence_set "cfv4_sOEP3" "cfv4_pOEP3") + +;; Reservation for instructions that don't allow dual-issue. +(define_reservation "cfv4_ds" "cfv4_pOEP1+cfv4_sOEP1+ + cfv4_pOEP2+cfv4_sOEP2+ + cfv4_pOEP3+cfv4_sOEP3") + +;; Memory access resource. +(define_automaton "cfv4_mem") + +(define_cpu_unit "cfv4_mem" "cfv4_mem") + +;; EMAC. +(define_automaton "cfv4_emac") + +(define_cpu_unit "cfv4_emac" "cfv4_emac") + +;; FPU. +(define_automaton "cfv4_fp") + +(define_cpu_unit "cfv4_fp" "cfv4_fp") + +;; Automaton for unknown instruction. +(define_automaton "cfv4_guess") + +(define_query_cpu_unit "cfv4_guess" "cfv4_guess") + +;; This bypass allows 1st case of dual-issue. +(define_bypass 0 "cfv4_00_oag_pOEP1,cfv4_10_pOEP1,cfv4_i0_pOEP1" + "cfv4_00_oag,cfv4_00_oag_pOEP3_sOEP12,cfv4_00_oag_pOEP1, + cfv4_00_oag_moveql,cfv4_00_ex_sOEP13") + +;; The following bypasses decrease the latency of producers if it modifies +;; a target register in the EX stage and the consumer also uses +;; that register in the EX stage. +(define_bypass 1 "cfv4_00_ex" "cfv4_00_ex,cfv4_00_ex_sOEP13") +(define_bypass 1 "cfv4_00_ex" "cfv4_10,cfv4_10_pOEP1,cfv4_i0,cfv4_i0_pOEP1" + "!m68k_sched_address_bypass_p") + +;; Indexed loads with scale factors 2 and 4 require an update of the index +;; register in the register file. Considering that the index register is +;; only needed at the second cycle of address generation, we get +;; a latency of 4. +;; Producers for indexed loads with scale factor 1 should have +;; a latency of 3. Since we're only allowed one bypass, we handle it +;; in the adjust_cost hook. +(define_bypass 4 + "cfv4_00_oag,cfv4_00_oag_pOEP3_sOEP12,cfv4_00_oag_lea,cfv4_00_oag_pOEP1, + cfv4_00_oag_moveql" + "cfv4_i0,cfv4_i0_pOEP1" + "m68k_sched_indexed_address_bypass_p") + +;; First part of cfv4_00. +;; If issued in pairs with cfv4_movel_?0, the cost should be increased. +;; ??? Is it possible that combined cfv4_movel_00 and cfv4_oag_00 instructions +;; have longer latency than the two instructions emitted sequentially? +;; Due to register renaming, the result of the sequence would be available +;; after 3 cycles, instead of 4 for combined instruction? +(define_insn_reservation "cfv4_00_oag" 1 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "alu_l,aluq_l,clr_l,cmp_l,mov3q_l,neg_l")) + (eq_attr "op_mem" "00")) + "cfv4_sOEP1|cfv4_sOEP3|(cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex)") + +(define_insn_reservation "cfv4_00_oag_pOEP3_sOEP12" 1 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "move_l,mov3q_l,clr_l")) + (and (eq_attr "op_mem" "00") + (and (eq_attr "opx_type" "Rn") + (eq_attr "opy_type" "none,imm_q,imm_w,imm_l")))) + "cfv4_sOEP1|cfv4_sOEP2|(cfv4_pOEP3,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex)") + +(define_insn_reservation "cfv4_00_oag_lea" 1 + (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "lea")) + "cfv4_pOEP3,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex") + +(define_insn_reservation "cfv4_00_oag_pOEP1" 1 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "move_l,mov3q_l,clr_l")) + (and (eq_attr "op_mem" "00") + (ior (eq_attr "opx_type" "!Rn") + (eq_attr "opy_type" "!none,imm_q,imm_w,imm_l")))) + "cfv4_sOEP1|(cfv4_pOEP1,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex)") + +(define_insn_reservation "cfv4_00_oag_moveql" 1 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "moveq_l")) + (eq_attr "op_mem" "00")) + "cfv4_sOEP1|cfv4_sOEP2|cfv4_sOEP3|(cfv4_pOEP3,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex)") -(define_insn_reservation "cf_guess_1" 1 - (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") - (eq_attr "guess" "yes")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 1))) - "cf_ib1+cf_guess+cf_dsoc+cf_agex") +;; Second part of cfv4_00. +;; Latency is either 1 or 4 depending on which stage the consumer +;; will need the data. -(define_insn_reservation "cf_guess_2" 1 - (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") - (eq_attr "guess" "yes")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 2))) - "cf_ib2+cf_guess+cf_dsoc+cf_agex") +(define_insn_reservation "cfv4_00_ex" 4 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "bitr,bitrw,clr,cmp,move,mvsz,scc,tst")) + (eq_attr "op_mem" "00")) + "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex") + +(define_insn_reservation "cfv4_00_ex_sOEP13" 4 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "alux_l,ext,shift,tst_l")) + (eq_attr "op_mem" "00")) + "cfv4_sOEP1|cfv4_sOEP3|(cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex)") + +;; Several types mentioned in this reservation (e.g., ext and shift) don't +;; support implicit load. But we handle them anyway due to first scheduling +;; pass, which handles non-strict rtl. +;; +;; Latency is either 1 or 4 depending in which stage the consumer +;; will need the data. +(define_insn_reservation "cfv4_10" 4 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "alu_l,aluq_l,alux_l,bitr,bitrw, + clr,clr_l,cmp,cmp_l,ext, + mov3q_l,move,moveq_l,mvsz,neg_l, + shift,tst,tst_l")) + (eq_attr "op_mem" "10")) + "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex") + +;; Specialization of cfv4_10. +;; move.l has OC2-to-DS forwarding path, that saves one cycle of latency. +(define_insn_reservation "cfv4_10_pOEP1" 3 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "move_l")) + (eq_attr "op_mem" "10")) + "cfv4_pOEP1,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex") + +;; Same here. But +1 to latency due to longer OAG. +(define_insn_reservation "cfv4_i0" 5 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "alu_l,aluq_l,alux_l,bitr,bitrw, + clr,clr_l,cmp,cmp_l,ext, + mov3q_l,move,moveq_l,mvsz,neg_l, + shift,tst,tst_l")) + (eq_attr "op_mem" "i0")) + "cfv4_ds,cfv4_oag,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex") -(define_insn_reservation "cf_guess_3" 1 - (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") - (eq_attr "guess" "yes")) - (eq (symbol_ref "get_attr_size (insn)") (const_int 3))) - "cf_ib3+cf_guess+cf_dsoc+cf_agex") +;; ??? Does indexed load trigger dual-issue? +;; ??? Does OC2-to-DS forwarding path saves a cycle? +(define_insn_reservation "cfv4_i0_pOEP1" 4 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "move_l")) + (eq_attr "op_mem" "i0")) + "cfv4_ds,cfv4_oag,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex") + +;; This reservation is for moves and clr. Arithmetic instructions +;; don't write to memory unless they also read from it. +;; But, before reload we can have all sorts of things. +;; With cfv4_pOEP2 allow dual-issue for type 2 cases. +(define_insn_reservation "cfv4_01" 1 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "alu_l,aluq_l,alux_l,bitr,bitrw, + clr,clr_l,cmp,cmp_l,ext, + mov3q_l,move,move_l,moveq_l,mvsz,neg_l, + shift")) + (eq_attr "op_mem" "01")) + "cfv4_pOEP2,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_da,cfv4_mem") + +;; ??? Does indexed store trigger dual-issue? +(define_insn_reservation "cfv4_0i" 2 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "alu_l,aluq_l,alux_l,bitr,bitrw, + clr,clr_l,cmp,cmp_l,ext, + mov3q_l,move,move_l,moveq_l,mvsz,neg_l, + shift")) + (eq_attr "op_mem" "0i")) + "cfv4_pOEP2,cfv4_oag,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_da,cfv4_mem") + +(define_insn_reservation "cfv4_11" 1 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "alu_l,aluq_l,alux_l,bitr,bitrw, + clr,clr_l,cmp,cmp_l,ext, + mov3q_l,move,move_l,moveq_l,mvsz,neg_l, + shift")) + (eq_attr "op_mem" "11")) + "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_da,cfv4_mem") + +;; Latency is 2 due to long OAG stage. +(define_insn_reservation "cfv4_i1" 2 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "alu_l,aluq_l,alux_l,bitr,bitrw, + clr,clr_l,cmp,cmp_l,ext, + mov3q_l,move,move_l,moveq_l,mvsz,neg_l, + shift")) + (eq_attr "op_mem" "i1")) + "cfv4_ds,cfv4_oag,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_da,cfv4_mem") + +;; This one is the same as cfv4_i1. +;; ??? Should it be different? +(define_insn_reservation "cfv4_1i" 2 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "alu_l,aluq_l,alux_l,bitr,bitrw, + clr,clr_l,cmp,cmp_l,ext, + mov3q_l,move,move_l,moveq_l,mvsz,neg_l, + shift")) + (eq_attr "op_mem" "1i")) + "cfv4_ds,cfv4_oag,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_da,cfv4_mem") + +;; ??? Does pea indeed support case 2 of dual-issue? +(define_insn_reservation "cfv4_11_pea" 1 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "pea")) + (eq_attr "op_mem" "11,00,01,0i,10")) + "cfv4_pOEP2,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_da,cfv4_mem") + +;; ??? Does pea indeed support case 2 of dual-issue? +;; ??? Does indexed store trigger dual-issue? +(define_insn_reservation "cfv4_i1_pea" 1 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "pea")) + (eq_attr "op_mem" "i1,1i")) + "cfv4_pOEP2,cfv4_oag,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_da,cfv4_mem") + +(define_insn_reservation "cfv4_link" 2 + (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "link")) + "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_ex,cfv4_da,cfv4_mem") + +(define_insn_reservation "cfv4_unlink" 2 + (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "unlk")) + "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex") + +(define_insn_reservation "cfv4_divw_00" 20 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "div_w")) + (eq_attr "op_mem" "00,01,0i")) + "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex*15") + +(define_insn_reservation "cfv4_divw_10" 20 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "div_w")) + (eq_attr "op_mem" "10,11,1i")) + "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex*15") + +(define_insn_reservation "cfv4_divw_i0" 21 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "div_w")) + (eq_attr "op_mem" "i0,i1")) + "cfv4_ds,cfv4_oag,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex*15") + +(define_insn_reservation "cfv4_divl_00" 35 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "div_l")) + (eq_attr "op_mem" "00,01,0i")) + "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex*30") + +(define_insn_reservation "cfv4_divl_10" 35 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "div_l")) + (eq_attr "op_mem" "10,11,1i,i0,i1")) + "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex*30") + +(define_insn_reservation "cfv4_emac_mul_00" 7 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "mul_w,mul_l")) + (eq_attr "op_mem" "00,01,0i")) + "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_emac") + +(define_insn_reservation "cfv4_emac_mul_10" 7 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "mul_w,mul_l")) + (eq_attr "op_mem" "10,11,1i")) + "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_emac") + +(define_insn_reservation "cfv4_emac_mul_i0" 8 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "mul_w,mul_l")) + (eq_attr "op_mem" "i0,i1")) + "cfv4_ds,cfv4_oag,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_emac") + +(define_insn_reservation "cfv4_falu_00" 7 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "falu,fcmp,fmul")) + (eq_attr "op_mem" "00,01,0i")) + "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_fp") + +(define_insn_reservation "cfv4_falu_10" 7 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "falu,fcmp,fmul")) + (eq_attr "op_mem" "10,i0,11,1i,i1")) + "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_fp") + +(define_insn_reservation "cfv4_fneg_00" 4 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "fmove,fneg,ftst")) + (eq_attr "op_mem" "00")) + "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_fp") + +(define_insn_reservation "cfv4_fmove_fneg_10" 4 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "fmove,fneg,ftst")) + (eq_attr "op_mem" "10,i0,11,1i,i1")) + "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_fp") + +(define_insn_reservation "cfv4_fmove_01" 1 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "fmove,fneg,ftst")) + (eq_attr "op_mem" "01,0i")) + "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_fp,cfv4_da,cfv4_mem") + +(define_insn_reservation "cfv4_fdiv_00" 23 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "fdiv")) + (eq_attr "op_mem" "00,01,0i")) + "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_fp*17") + +(define_insn_reservation "cfv4_fdiv_10" 23 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "fdiv")) + (eq_attr "op_mem" "10,i0,11,1i,i1")) + "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_fp*17") + +(define_insn_reservation "cfv4_fsqrt_00" 56 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "fsqrt")) + (eq_attr "op_mem" "00,01,0i")) + "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_fp*50") + +(define_insn_reservation "cfv4_fsqrt_10" 56 + (and (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "fsqrt")) + (eq_attr "op_mem" "10,i0,11,1i,i1")) + "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_fp*50") + +(define_insn_reservation "cfv4_bcc" 0 + (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "bcc")) + "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex") + +(define_insn_reservation "cfv4_fbcc" 2 + (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "fbcc")) + "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_fp") + +;; ??? Why is bra said to write to memory: 1(0/1) ? +(define_insn_reservation "cfv4_bra_bsr" 1 + (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "bra,bsr")) + "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex") + +(define_insn_reservation "cfv4_jmp_jsr" 5 + (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "jmp,jsr")) + "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex") + +(define_insn_reservation "cfv4_rts" 2 + (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "rts")) + "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex") + +(define_insn_reservation "cfv4_nop" 1 + (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "nop")) + "cfv4_ds+cfv4_oag+cfv4_oc1+cfv4_mem+cfv4_oc2+cfv4_ex") + +(define_insn_reservation "cfv4_guess" 10 + (and (eq_attr "cpu" "cfv4") + (eq_attr "type" "trap,unknown")) + "cfv4_guess+cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_emac+cfv4_fp") + +(define_insn_reservation "ignore" 0 + (eq_attr "type" "ignore") + "nothing") diff --git a/gcc/config/m68k/m68k-protos.h b/gcc/config/m68k/m68k-protos.h index 8948065..33025f8 100644 --- a/gcc/config/m68k/m68k-protos.h +++ b/gcc/config/m68k/m68k-protos.h @@ -71,10 +71,9 @@ extern enum attr_mac m68k_sched_mac; extern enum attr_opx_type m68k_sched_attr_opx_type (rtx, int); extern enum attr_opy_type m68k_sched_attr_opy_type (rtx, int); -extern int m68k_sched_attr_size (rtx); +extern enum attr_size m68k_sched_attr_size (rtx); extern enum attr_op_mem m68k_sched_attr_op_mem (rtx); extern enum attr_type m68k_sched_branch_type (rtx); -extern enum attr_type2 m68k_sched_attr_type2 (rtx); #endif /* HAVE_ATTR_cpu */ #endif /* RTX_CODE */ diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c index 3fdd756..52a60da 100644 --- a/gcc/config/m68k/m68k.c +++ b/gcc/config/m68k/m68k.c @@ -122,12 +122,14 @@ struct m68k_address { }; static int m68k_sched_adjust_cost (rtx, rtx, rtx, int); +static int m68k_sched_issue_rate (void); static int m68k_sched_variable_issue (FILE *, int, rtx, int); static void m68k_sched_md_init_global (FILE *, int, int); static void m68k_sched_md_finish_global (FILE *, int); static void m68k_sched_md_init (FILE *, int, int); static void m68k_sched_dfa_pre_advance_cycle (void); static void m68k_sched_dfa_post_advance_cycle (void); +static int m68k_sched_first_cycle_multipass_dfa_lookahead (void); static bool m68k_handle_option (size_t, const char *, int); static rtx find_addr_reg (rtx); @@ -199,6 +201,9 @@ int m68k_last_compare_had_fp_operands; #undef TARGET_SCHED_ADJUST_COST #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost +#undef TARGET_SCHED_ISSUE_RATE +#define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate + #undef TARGET_SCHED_VARIABLE_ISSUE #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue @@ -217,6 +222,10 @@ int m68k_last_compare_had_fp_operands; #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle +#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD +#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \ + m68k_sched_first_cycle_multipass_dfa_lookahead + #undef TARGET_HANDLE_OPTION #define TARGET_HANDLE_OPTION m68k_handle_option @@ -672,6 +681,8 @@ override_options (void) m68k_sched_cpu = CPU_CFV2; else if (TUNE_CFV3) m68k_sched_cpu = CPU_CFV3; + else if (TUNE_CFV4) + m68k_sched_cpu = CPU_CFV4; else { m68k_sched_cpu = CPU_UNKNOWN; @@ -1037,6 +1048,11 @@ m68k_expand_prologue (void) stack_pointer_rtx, GEN_INT (-fsize_with_regs)))); } + + /* If the frame pointer is needed, emit a special barrier that + will prevent the scheduler from moving stores to the frame + before the stack adjustment. */ + emit_insn (gen_stack_tie (stack_pointer_rtx, frame_pointer_rtx)); } else if (fsize_with_regs != 0) m68k_set_frame_related @@ -4579,8 +4595,11 @@ enum attr_op_type /* No operand. */ OP_TYPE_NONE, - /* Register. */ - OP_TYPE_REG, + /* Integer register. */ + OP_TYPE_RN, + + /* FP register. */ + OP_TYPE_FPN, /* Implicit mem reference (e.g. stack). */ OP_TYPE_MEM1, @@ -4607,19 +4626,19 @@ enum attr_op_type OP_TYPE_IMM_L }; -/* True if current insn doesn't have complete pipeline description. */ -static bool sched_guess_p; - /* Return type of memory ADDR_RTX refers to. */ static enum attr_op_type sched_address_type (enum machine_mode mode, rtx addr_rtx) { struct m68k_address address; + if (symbolic_operand (addr_rtx, VOIDmode)) + return OP_TYPE_MEM7; + if (!m68k_decompose_address (mode, addr_rtx, reload_completed, &address)) { - gcc_assert (sched_guess_p); + gcc_assert (!reload_completed); /* Reload will likely fix the address to be in the register. */ return OP_TYPE_MEM234; } @@ -4640,12 +4659,42 @@ sched_address_type (enum machine_mode mode, rtx addr_rtx) return OP_TYPE_MEM7; } -/* Return type of the operand OP. - If ADDRESS_P is true, return type of memory location OP refers to. */ +/* Return X or Y (depending on OPX_P) operand of INSN. */ +static rtx +sched_get_operand (rtx insn, bool opx_p) +{ + int i; + + if (recog_memoized (insn) < 0) + gcc_unreachable (); + + extract_constrain_insn_cached (insn); + + if (opx_p) + i = get_attr_opx (insn); + else + i = get_attr_opy (insn); + + if (i >= recog_data.n_operands) + return NULL; + + return recog_data.operand[i]; +} + +/* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P). + If ADDRESS_P is true, return type of memory location operand refers to. */ static enum attr_op_type -sched_operand_type (rtx op, bool address_p) +sched_attr_op_type (rtx insn, bool opx_p, bool address_p) { - gcc_assert (op != NULL_RTX); + rtx op; + + op = sched_get_operand (insn, opx_p); + + if (op == NULL) + { + gcc_assert (!reload_completed); + return OP_TYPE_RN; + } if (address_p) return sched_address_type (QImode, op); @@ -4654,13 +4703,49 @@ sched_operand_type (rtx op, bool address_p) return sched_address_type (GET_MODE (op), XEXP (op, 0)); if (register_operand (op, VOIDmode)) - return OP_TYPE_REG; + { + if ((!reload_completed && FLOAT_MODE_P (GET_MODE (op))) + || (reload_completed && FP_REG_P (op))) + return OP_TYPE_FPN; + + return OP_TYPE_RN; + } if (GET_CODE (op) == CONST_INT) { - /* ??? Below condition should probably check if the operation is - signed or unsigned. */ - if (IN_RANGE (INTVAL (op), -0x8000, 0x7fff)) + int ival; + + ival = INTVAL (op); + + /* Check for quick constants. */ + switch (get_attr_type (insn)) + { + case TYPE_ALUQ_L: + if (IN_RANGE (ival, 1, 8) || IN_RANGE (ival, -8, -1)) + return OP_TYPE_IMM_Q; + + gcc_assert (!reload_completed); + break; + + case TYPE_MOVEQ_L: + if (USE_MOVQ (ival)) + return OP_TYPE_IMM_Q; + + gcc_assert (!reload_completed); + break; + + case TYPE_MOV3Q_L: + if (valid_mov3q_const (ival)) + return OP_TYPE_IMM_Q; + + gcc_assert (!reload_completed); + break; + + default: + break; + } + + if (IN_RANGE (ival, -0x8000, 0x7fff)) return OP_TYPE_IMM_W; return OP_TYPE_IMM_L; @@ -4706,32 +4791,12 @@ sched_operand_type (rtx op, bool address_p) } } - gcc_assert (sched_guess_p); - - return OP_TYPE_REG; -} - -/* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P). - If ADDRESS_P is true, return type of memory location operand refers to. */ -static enum attr_op_type -sched_attr_op_type (rtx insn, bool opx_p, bool address_p) -{ - int i; - - extract_constrain_insn_cached (insn); + gcc_assert (!reload_completed); - if (opx_p) - i = get_attr_opx (insn); - else - i = get_attr_opy (insn); + if (FLOAT_MODE_P (GET_MODE (op))) + return OP_TYPE_FPN; - if (i >= recog_data.n_operands) - { - gcc_assert (sched_guess_p); - return OP_TYPE_REG; - } - - return sched_operand_type (recog_data.operand[i], address_p); + return OP_TYPE_RN; } /* Implement opx_type attribute. @@ -4740,12 +4805,13 @@ sched_attr_op_type (rtx insn, bool opx_p, bool address_p) enum attr_opx_type m68k_sched_attr_opx_type (rtx insn, int address_p) { - sched_guess_p = (get_attr_guess (insn) == GUESS_YES); - switch (sched_attr_op_type (insn, true, address_p != 0)) { - case OP_TYPE_REG: - return OPX_TYPE_REG; + case OP_TYPE_RN: + return OPX_TYPE_RN; + + case OP_TYPE_FPN: + return OPX_TYPE_FPN; case OP_TYPE_MEM1: return OPX_TYPE_MEM1; @@ -4783,12 +4849,13 @@ m68k_sched_attr_opx_type (rtx insn, int address_p) enum attr_opy_type m68k_sched_attr_opy_type (rtx insn, int address_p) { - sched_guess_p = (get_attr_guess (insn) == GUESS_YES); - switch (sched_attr_op_type (insn, false, address_p != 0)) { - case OP_TYPE_REG: - return OPY_TYPE_REG; + case OP_TYPE_RN: + return OPY_TYPE_RN; + + case OP_TYPE_FPN: + return OPY_TYPE_FPN; case OP_TYPE_MEM1: return OPY_TYPE_MEM1; @@ -4820,17 +4887,21 @@ m68k_sched_attr_opy_type (rtx insn, int address_p) } } -/* Return the size of INSN. */ -int -m68k_sched_attr_size (rtx insn) +/* Return size of INSN as int. */ +static int +sched_get_attr_size_int (rtx insn) { int size; - sched_guess_p = (get_attr_guess (insn) == GUESS_YES); - - switch (get_attr_type1 (insn)) + switch (get_attr_type (insn)) { - case TYPE1_MUL_L: + case TYPE_IGNORE: + /* There should be no references to m68k_sched_attr_size for 'ignore' + instructions. */ + gcc_unreachable (); + return 0; + + case TYPE_MUL_L: size = 2; break; @@ -4842,7 +4913,8 @@ m68k_sched_attr_size (rtx insn) switch (get_attr_opx_type (insn)) { case OPX_TYPE_NONE: - case OPX_TYPE_REG: + case OPX_TYPE_RN: + case OPX_TYPE_FPN: case OPX_TYPE_MEM1: case OPX_TYPE_MEM234: case OPY_TYPE_IMM_Q: @@ -4867,7 +4939,8 @@ m68k_sched_attr_size (rtx insn) switch (get_attr_opy_type (insn)) { case OPY_TYPE_NONE: - case OPY_TYPE_REG: + case OPY_TYPE_RN: + case OPY_TYPE_FPN: case OPY_TYPE_MEM1: case OPY_TYPE_MEM234: case OPY_TYPE_IMM_Q: @@ -4891,7 +4964,7 @@ m68k_sched_attr_size (rtx insn) if (size > 3) { - gcc_assert (sched_guess_p); + gcc_assert (!reload_completed); size = 3; } @@ -4899,22 +4972,100 @@ m68k_sched_attr_size (rtx insn) return size; } +/* Return size of INSN as attribute enum value. */ +enum attr_size +m68k_sched_attr_size (rtx insn) +{ + switch (sched_get_attr_size_int (insn)) + { + case 1: + return SIZE_1; + + case 2: + return SIZE_2; + + case 3: + return SIZE_3; + + default: + gcc_unreachable (); + return 0; + } +} + +/* Return operand X or Y (depending on OPX_P) of INSN, + if it is a MEM, or NULL overwise. */ +static enum attr_op_type +sched_get_opxy_mem_type (rtx insn, bool opx_p) +{ + if (opx_p) + { + switch (get_attr_opx_type (insn)) + { + case OPX_TYPE_NONE: + case OPX_TYPE_RN: + case OPX_TYPE_FPN: + case OPX_TYPE_IMM_Q: + case OPX_TYPE_IMM_W: + case OPX_TYPE_IMM_L: + return OP_TYPE_RN; + + case OPX_TYPE_MEM1: + case OPX_TYPE_MEM234: + case OPX_TYPE_MEM5: + case OPX_TYPE_MEM7: + return OP_TYPE_MEM1; + + case OPX_TYPE_MEM6: + return OP_TYPE_MEM6; + + default: + gcc_unreachable (); + return 0; + } + } + else + { + switch (get_attr_opy_type (insn)) + { + case OPY_TYPE_NONE: + case OPY_TYPE_RN: + case OPY_TYPE_FPN: + case OPY_TYPE_IMM_Q: + case OPY_TYPE_IMM_W: + case OPY_TYPE_IMM_L: + return OP_TYPE_RN; + + case OPY_TYPE_MEM1: + case OPY_TYPE_MEM234: + case OPY_TYPE_MEM5: + case OPY_TYPE_MEM7: + return OP_TYPE_MEM1; + + case OPY_TYPE_MEM6: + return OP_TYPE_MEM6; + + default: + gcc_unreachable (); + return 0; + } + } +} + /* Implement op_mem attribute. */ enum attr_op_mem m68k_sched_attr_op_mem (rtx insn) { - enum attr_opy_mem opy; - enum attr_opx_mem opx; + enum attr_op_type opx; + enum attr_op_type opy; - sched_guess_p = (get_attr_guess (insn) == GUESS_YES); + opx = sched_get_opxy_mem_type (insn, true); + opy = sched_get_opxy_mem_type (insn, false); - opy = get_attr_opy_mem (insn); - opx = get_attr_opx_mem (insn); - - if (opy == OPY_MEM_R && opx == OPX_MEM_R) + if (opy == OP_TYPE_RN && opx == OP_TYPE_RN) return OP_MEM_00; - if (opy == OPY_MEM_R && opx == OPX_MEM_M) + if (opy == OP_TYPE_RN && opx == OP_TYPE_MEM1) { switch (get_attr_opx_access (insn)) { @@ -4928,12 +5079,12 @@ m68k_sched_attr_op_mem (rtx insn) return OP_MEM_11; default: - gcc_assert (sched_guess_p); - return OP_MEM_UNKNOWN; + gcc_unreachable (); + return 0; } } - if (opy == OPY_MEM_R && opx == OPX_MEM_I) + if (opy == OP_TYPE_RN && opx == OP_TYPE_MEM6) { switch (get_attr_opx_access (insn)) { @@ -4947,15 +5098,15 @@ m68k_sched_attr_op_mem (rtx insn) return OP_MEM_I1; default: - gcc_assert (sched_guess_p); - return OP_MEM_UNKNOWN; + gcc_unreachable (); + return 0; } } - if (opy == OPY_MEM_M && opx == OPX_MEM_R) + if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_RN) return OP_MEM_10; - if (opy == OPY_MEM_M && opx == OPX_MEM_M) + if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_MEM1) { switch (get_attr_opx_access (insn)) { @@ -4963,12 +5114,12 @@ m68k_sched_attr_op_mem (rtx insn) return OP_MEM_11; default: - gcc_assert (sched_guess_p); - return OP_MEM_UNKNOWN; + gcc_assert (!reload_completed); + return OP_MEM_11; } } - if (opy == OPY_MEM_M && opx == OPX_MEM_I) + if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_MEM6) { switch (get_attr_opx_access (insn)) { @@ -4976,16 +5127,15 @@ m68k_sched_attr_op_mem (rtx insn) return OP_MEM_1I; default: - gcc_assert (sched_guess_p); - return OP_MEM_UNKNOWN; + gcc_assert (!reload_completed); + return OP_MEM_1I; } } - if (opy == OPY_MEM_I && opx == OPX_MEM_R) + if (opy == OP_TYPE_MEM6 && opx == OP_TYPE_RN) return OP_MEM_I0; - - if (opy == OPY_MEM_I && opx == OPX_MEM_M) + if (opy == OP_TYPE_MEM6 && opx == OP_TYPE_MEM1) { switch (get_attr_opx_access (insn)) { @@ -4993,13 +5143,14 @@ m68k_sched_attr_op_mem (rtx insn) return OP_MEM_I1; default: - gcc_assert (sched_guess_p); - return OP_MEM_UNKNOWN; + gcc_assert (!reload_completed); + return OP_MEM_I1; } } - gcc_assert (sched_guess_p); - return OP_MEM_UNKNOWN; + gcc_assert (opy == OP_TYPE_MEM6 && opx == OP_TYPE_MEM6); + gcc_assert (!reload_completed); + return OP_MEM_I1; } /* Jump instructions types. Indexed by INSN_UID. @@ -5022,80 +5173,21 @@ m68k_sched_branch_type (rtx insn) return type; } -/* Implement type2 attribute. */ -enum attr_type2 -m68k_sched_attr_type2 (rtx insn) +/* Data for ColdFire V4 index bypass. + Producer modifies register that is used as index in consumer with + specified scale. */ +static struct { - switch (get_attr_type1 (insn)) - { - case TYPE1_ALU_L: - case TYPE1_ALUQ_L: - case TYPE1_CMP_L: - return TYPE2_ALU; + /* Producer instruction. */ + rtx pro; - case TYPE1_ALU_REG1: - case TYPE1_ALU_REGX: - return TYPE2_ALU_REG; + /* Consumer instruction. */ + rtx con; - case TYPE1_BCC: - return TYPE2_BCC; - - case TYPE1_BRA: - return TYPE2_BRA; - - case TYPE1_BSR: - case TYPE1_JSR: - return TYPE2_CALL; - - case TYPE1_JMP: - return TYPE2_JMP; - - case TYPE1_LEA: - return TYPE2_LEA; - - case TYPE1_CLR: - case TYPE1_MOV3Q_L: - case TYPE1_MOVE: - case TYPE1_MOVEQ_L: - case TYPE1_TST: - switch (m68k_sched_cpu) - { - case CPU_CFV1: - return TYPE2_OMOVE; - - case CPU_CFV2: - case CPU_CFV3: - return TYPE2_ALU; - - default: - gcc_assert (get_attr_guess (insn) == GUESS_YES); - return TYPE2_UNKNOWN; - } - - case TYPE1_MUL_L: - return TYPE2_MUL_L; - - case TYPE1_MUL_W: - return TYPE2_MUL_W; - - case TYPE1_MOVE_L: - case TYPE1_TST_L: - return TYPE2_OMOVE; - - case TYPE1_PEA: - return TYPE2_PEA; - - case TYPE1_RTS: - return TYPE2_RTS; - - case TYPE1_UNLK: - return TYPE2_UNLK; - - default: - gcc_assert (get_attr_guess (insn) == GUESS_YES); - return TYPE2_UNKNOWN; - } -} + /* Scale of indexed memory access within consumer. + Or zero if bypass should not be effective at the moment. */ + int scale; +} sched_cfv4_bypass_data; /* An empty state that is used in m68k_sched_adjust_cost. */ static state_t sched_adjust_cost_state; @@ -5112,13 +5204,33 @@ m68k_sched_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx def_insn, || recog_memoized (insn) < 0) return cost; + if (sched_cfv4_bypass_data.scale == 1) + /* Handle ColdFire V4 bypass for indexed address with 1x scale. */ + { + /* haifa-sched.c: insn_cost () calls bypass_p () just before + targetm.sched.adjust_cost (). Hence, we can be relatively sure + that the data in sched_cfv4_bypass_data is up to date. */ + gcc_assert (sched_cfv4_bypass_data.pro == def_insn + && sched_cfv4_bypass_data.con == insn); + + if (cost < 3) + cost = 3; + + sched_cfv4_bypass_data.pro = NULL; + sched_cfv4_bypass_data.con = NULL; + sched_cfv4_bypass_data.scale = 0; + } + else + gcc_assert (sched_cfv4_bypass_data.pro == NULL + && sched_cfv4_bypass_data.con == NULL + && sched_cfv4_bypass_data.scale == 0); + /* Don't try to issue INSN earlier than DFA permits. This is especially useful for instructions that write to memory, as their true dependence (default) latency is better to be set to 0 to workaround alias analysis limitations. This is, in fact, a machine independent tweak, so, probably, it should be moved to haifa-sched.c: insn_cost (). */ - delay = min_insn_conflict_delay (sched_adjust_cost_state, def_insn, insn); if (delay > cost) cost = delay; @@ -5126,6 +5238,26 @@ m68k_sched_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx def_insn, return cost; } +/* Return maximal number of insns that can be scheduled on a single cycle. */ +static int +m68k_sched_issue_rate (void) +{ + switch (m68k_sched_cpu) + { + case CPU_CFV1: + case CPU_CFV2: + case CPU_CFV3: + return 1; + + case CPU_CFV4: + return 2; + + default: + gcc_unreachable (); + return 0; + } +} + /* Maximal length of instruction for current CPU. E.g. it is 3 for any ColdFire core. */ static int max_insn_size; @@ -5133,6 +5265,9 @@ static int max_insn_size; /* Data to model instruction buffer of CPU. */ struct _sched_ib { + /* True if instruction buffer model is modeled for current CPU. */ + bool enabled_p; + /* Size of the instruction buffer in words. */ int size; @@ -5175,17 +5310,17 @@ m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED, { int insn_size; - if (recog_memoized (insn) >= 0) + if (recog_memoized (insn) >= 0 && get_attr_type (insn) != TYPE_IGNORE) { switch (m68k_sched_cpu) { case CPU_CFV1: case CPU_CFV2: - insn_size = get_attr_size (insn); + insn_size = sched_get_attr_size_int (insn); break; case CPU_CFV3: - insn_size = get_attr_size (insn); + insn_size = sched_get_attr_size_int (insn); /* ColdFire V3 and V4 cores have instruction buffers that can accumulate up to 8 instructions regardless of instructions' @@ -5215,6 +5350,11 @@ m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED, break; + case CPU_CFV4: + gcc_assert (!sched_ib.enabled_p); + insn_size = 0; + break; + default: gcc_unreachable (); } @@ -5233,194 +5373,12 @@ m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED, return can_issue_more; } -/* Statistics gatherer. */ - -typedef enum - { - /* Something needs to be done for this insn. */ - SCHED_DUMP_TODO, - - /* Support for this insn is complete. */ - SCHED_DUMP_DONE, - - /* This insn didn't require much effort to support it. */ - SCHED_DUMP_NOTHING - } sched_dump_class_def; - -/* Pointer to functions that classifies insns into 3 above classes. */ -typedef sched_dump_class_def (*sched_dump_class_func_t) (rtx); - -/* Return statistical type of INSN regarding splits. */ -static sched_dump_class_def -sched_dump_split_class (rtx insn) -{ - int i; - - i = recog_memoized (insn); - gcc_assert (i >= 0); - - switch (get_attr_split (insn)) - { - case SPLIT_TODO: - return SCHED_DUMP_TODO; - - case SPLIT_DONE: - return SCHED_DUMP_DONE; - - case SPLIT_NOTHING: - return SCHED_DUMP_NOTHING; - - default: - gcc_unreachable (); - } -} - -/* ID of the guess unit. */ -static int sched_dump_dfa_guess_unit_code; - -/* DFA state for use in sched_dump_dfa_class (). */ -static state_t sched_dump_dfa_state; - -/* Return statistical type of INSN regarding DFA reservations. */ -static sched_dump_class_def -sched_dump_dfa_class (rtx insn) +/* Return how many instructions should scheduler lookahead to choose the + best one. */ +static int +m68k_sched_first_cycle_multipass_dfa_lookahead (void) { - int i; - - i = recog_memoized (insn); - gcc_assert (i >= 0 && insn_has_dfa_reservation_p (insn)); - - if (sched_dump_split_class (insn) == SCHED_DUMP_TODO) - /* Insn is not yet ready for reservations. */ - return SCHED_DUMP_NOTHING; - - state_reset (sched_dump_dfa_state); - - if (state_transition (sched_dump_dfa_state, insn) >= 0) - gcc_unreachable (); - - if (cpu_unit_reservation_p (sched_dump_dfa_state, - sched_dump_dfa_guess_unit_code)) - return SCHED_DUMP_TODO; - - return SCHED_DUMP_DONE; -} - -/* Dump statistics on current function into file DUMP_FILENAME and prefix - each entry with PREFIX. - Instructions are classified with DUMP_CLASS. */ -static void -m68k_sched_dump (sched_dump_class_func_t dump_class, - const char *prefix, FILE *dump) -{ - sbitmap present; - int *todos; - int *dones; - int *nothings; - rtx insn; - - gcc_assert (dump != NULL); - - present = sbitmap_alloc (CODE_FOR_nothing); - sbitmap_zero (present); - - todos = xcalloc (CODE_FOR_nothing, sizeof (*todos)); - dones = xcalloc (CODE_FOR_nothing, sizeof (*dones)); - nothings = xcalloc (CODE_FOR_nothing, sizeof (*nothings)); - - /* Gather statistics. */ - for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn)) - { - if (INSN_P (insn) && recog_memoized (insn) >= 0) - { - enum insn_code code; - - code = INSN_CODE (insn); - gcc_assert (code < CODE_FOR_nothing); - - SET_BIT (present, code); - - switch (dump_class (insn)) - { - case SCHED_DUMP_TODO: - ++todos[code]; - break; - - case SCHED_DUMP_DONE: - ++dones[code]; - break; - - case SCHED_DUMP_NOTHING: - ++nothings[code]; - break; - } - } - } - - /* Print statisctics. */ - { - unsigned int i; - sbitmap_iterator si; - int total_todo; - int total_done; - int total_nothing; - - total_todo = 0; - total_done = 0; - total_nothing = 0; - - EXECUTE_IF_SET_IN_SBITMAP (present, 0, i, si) - { - int todo; - int done; - int nothing; - enum insn_code code; - - code = (enum insn_code) i; - - todo = todos[code]; - done = dones[code]; - nothing = nothings[code]; - - total_todo += todo; - total_done += done; - total_nothing += nothing; - - if (todo != 0) - { - fprintf (dump, - "%s: %3d: %d / %d / %d ;", - prefix, code, todo, done, nothing); - - { - const char *name; - - name = get_insn_name (code); - - if (name != NULL) - fprintf (dump, " {%s}\n", name); - else - fprintf (dump, " {unknown}\n"); - } - } - } - - gcc_assert (CODE_FOR_nothing < 999); - - fprintf (dump, - "%s: 999: %d / %d / %d ; {total}\n", - prefix, total_todo, total_done, total_nothing); - } - - free (nothings); - nothings = NULL; - free (dones); - dones = NULL; - free (todos); - todos = NULL; - - sbitmap_free (present); - present = NULL; + return m68k_sched_issue_rate () - 1; } /* Implementation of targetm.sched.md_init_global () hook. @@ -5446,25 +5404,43 @@ m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED, } } - if (reload_completed && sched_verbose >= 8) - /* Dump statistics. */ - { - m68k_sched_dump (sched_dump_split_class, "m68k_sched_split", - sched_dump); +#ifdef ENABLE_CHECKING + /* Check that all instructions have DFA reservations and + that all instructions can be issued from a clean state. */ + { + rtx insn; + state_t state; - sched_dump_dfa_guess_unit_code = get_cpu_unit_code ("cf_guess"); - sched_dump_dfa_state = alloca (state_size ()); + state = alloca (state_size ()); - m68k_sched_dump (sched_dump_dfa_class, "m68k_sched_dfa", - sched_dump); + for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn)) + { + if (INSN_P (insn) && recog_memoized (insn) >= 0) + { + gcc_assert (insn_has_dfa_reservation_p (insn)); - sched_dump_dfa_state = NULL; - sched_dump_dfa_guess_unit_code = 0; - } + state_reset (state); + if (state_transition (state, insn) >= 0) + gcc_unreachable (); + } + } + } +#endif /* Setup target cpu. */ + + /* ColdFire V4 has a set of features to keep its instruction buffer full + (e.g., a separate memory bus for instructions) and, hence, we do not model + buffer for this CPU. */ + sched_ib.enabled_p = (m68k_sched_cpu != CPU_CFV4); + switch (m68k_sched_cpu) { + case CPU_CFV4: + sched_ib.filled = 0; + + /* FALLTHRU */ + case CPU_CFV1: case CPU_CFV2: max_insn_size = 3; @@ -5538,13 +5514,19 @@ m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED, sched_ib.records.adjust_index = 0; break; + case CPU_CFV4: + gcc_assert (!sched_ib.enabled_p); + sched_ib.size = 0; + break; + default: gcc_unreachable (); } - /* haifa-sched.c: schedule_block () calls advance_cycle () just before - the first cycle. Workaround that. */ - sched_ib.filled = -2; + if (sched_ib.enabled_p) + /* haifa-sched.c: schedule_block () calls advance_cycle () just before + the first cycle. Workaround that. */ + sched_ib.filled = -2; } /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook. @@ -5553,6 +5535,9 @@ m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED, static void m68k_sched_dfa_pre_advance_cycle (void) { + if (!sched_ib.enabled_p) + return; + if (!cpu_unit_reservation_p (curr_state, sched_mem_unit_code)) { sched_ib.filled += 2; @@ -5572,6 +5557,9 @@ m68k_sched_dfa_post_advance_cycle (void) { int i; + if (!sched_ib.enabled_p) + return; + /* Setup number of prefetched instruction words in the instruction buffer. */ i = max_insn_size - sched_ib.filled; @@ -5582,3 +5570,164 @@ m68k_sched_dfa_post_advance_cycle (void) gcc_unreachable (); } } + +/* Return X or Y (depending on OPX_P) operand of INSN, + if it is an integer register, or NULL overwise. */ +static rtx +sched_get_reg_operand (rtx insn, bool opx_p) +{ + rtx op = NULL; + + if (opx_p) + { + if (get_attr_opx_type (insn) == OPX_TYPE_RN) + { + op = sched_get_operand (insn, true); + gcc_assert (op != NULL); + + if (!reload_completed && !REG_P (op)) + return NULL; + } + } + else + { + if (get_attr_opy_type (insn) == OPY_TYPE_RN) + { + op = sched_get_operand (insn, false); + gcc_assert (op != NULL); + + if (!reload_completed && !REG_P (op)) + return NULL; + } + } + + return op; +} + +/* Return true, if X or Y (depending on OPX_P) operand of INSN + is a MEM. */ +static bool +sched_mem_operand_p (rtx insn, bool opx_p) +{ + switch (sched_get_opxy_mem_type (insn, opx_p)) + { + case OP_TYPE_MEM1: + case OP_TYPE_MEM6: + return true; + + default: + return false; + } +} + +/* Return X or Y (depending on OPX_P) operand of INSN, + if it is a MEM, or NULL overwise. */ +static rtx +sched_get_mem_operand (rtx insn, bool must_read_p, bool must_write_p) +{ + bool opx_p; + bool opy_p; + + opx_p = false; + opy_p = false; + + if (must_read_p) + { + opx_p = true; + opy_p = true; + } + + if (must_write_p) + { + opx_p = true; + opy_p = false; + } + + if (opy_p && sched_mem_operand_p (insn, false)) + return sched_get_operand (insn, false); + + if (opx_p && sched_mem_operand_p (insn, true)) + return sched_get_operand (insn, true); + + gcc_unreachable (); + return NULL; +} + +/* Return non-zero if PRO modifies register used as part of + address in CON. */ +int +m68k_sched_address_bypass_p (rtx pro, rtx con) +{ + rtx pro_x; + rtx con_mem_read; + + pro_x = sched_get_reg_operand (pro, true); + if (pro_x == NULL) + return 0; + + con_mem_read = sched_get_mem_operand (con, true, false); + gcc_assert (con_mem_read != NULL); + + if (reg_mentioned_p (pro_x, con_mem_read)) + return 1; + + return 0; +} + +/* Helper function for m68k_sched_indexed_address_bypass_p. + if PRO modifies register used as index in CON, + return scale of indexed memory access in CON. Return zero overwise. */ +static int +sched_get_indexed_address_scale (rtx pro, rtx con) +{ + rtx reg; + rtx mem; + struct m68k_address address; + + reg = sched_get_reg_operand (pro, true); + if (reg == NULL) + return 0; + + mem = sched_get_mem_operand (con, true, false); + gcc_assert (mem != NULL && MEM_P (mem)); + + if (!m68k_decompose_address (GET_MODE (mem), XEXP (mem, 0), reload_completed, + &address)) + gcc_unreachable (); + + if (REGNO (reg) == REGNO (address.index)) + { + gcc_assert (address.scale != 0); + return address.scale; + } + + return 0; +} + +/* Return non-zero if PRO modifies register used + as index with scale 2 or 4 in CON. */ +int +m68k_sched_indexed_address_bypass_p (rtx pro, rtx con) +{ + gcc_assert (sched_cfv4_bypass_data.pro == NULL + && sched_cfv4_bypass_data.con == NULL + && sched_cfv4_bypass_data.scale == 0); + + switch (sched_get_indexed_address_scale (pro, con)) + { + case 1: + /* We can't have a variable latency bypass, so + remember to adjust the insn cost in adjust_cost hook. */ + sched_cfv4_bypass_data.pro = pro; + sched_cfv4_bypass_data.con = con; + sched_cfv4_bypass_data.scale = 1; + return 0; + + case 2: + case 4: + return 1; + + default: + return 0; + } +} diff --git a/gcc/config/m68k/m68k.h b/gcc/config/m68k/m68k.h index 32b5c24..521ad84 100644 --- a/gcc/config/m68k/m68k.h +++ b/gcc/config/m68k/m68k.h @@ -267,6 +267,7 @@ along with GCC; see the file COPYING3. If not see #define TUNE_CFV1 (m68k_tune == ucfv1) #define TUNE_CFV2 (m68k_tune == ucfv2) #define TUNE_CFV3 (m68k_tune == ucfv3) +#define TUNE_CFV4 (m68k_tune == ucfv4 || m68k_tune == ucfv4e) #define OVERRIDE_OPTIONS override_options() @@ -1149,4 +1150,7 @@ extern M68K_CONST_METHOD m68k_const_method (HOST_WIDE_INT); extern void m68k_emit_move_double (rtx [2]); +extern int m68k_sched_address_bypass_p (rtx, rtx); +extern int m68k_sched_indexed_address_bypass_p (rtx, rtx); + #define CPU_UNITS_QUERY 1 diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md index abe363e..d142861 100644 --- a/gcc/config/m68k/m68k.md +++ b/gcc/config/m68k/m68k.md @@ -115,6 +115,7 @@ (UNSPEC_COS 2) (UNSPEC_GOT 3) (UNSPEC_IB 4) + (UNSPEC_TIE 5) ]) ;; UNSPEC_VOLATILE usage: @@ -144,202 +145,104 @@ ;; :::::::::::::::::::: ;; Processor type. -(define_attr "cpu" "cfv1, cfv2, cfv3, unknown" +(define_attr "cpu" "cfv1, cfv2, cfv3, cfv4, unknown" (const (symbol_ref "m68k_sched_cpu"))) ;; MAC type. (define_attr "mac" "no, cf_mac, cf_emac" (const (symbol_ref "m68k_sched_mac"))) -;; Instruction type. -;; Basically, an asm pattern. -(define_attr "type" - "add_l, addq_l, asr_l, bcc, bclr, bra, bset, bsr, - clr_b, clr_w, clr_l, cmp_l, - ext_w, extb_l, ext_l, - fadd, fcmp, fdiv, ff1, fintrz, fmove, fmul, fsqrt, fsub, ftst, jmp, jsr, - ib, - lea, lsr_l, - move_b, move_w, move_l, moveq_l, mov3q_l, mvs_b, mvs_w, mvz_b, mvz_w, - muls_w, muls_l, mulu_w, mulu_l, - neg_l, nop, not_l, - pea, rts, - scc, sub_l, subq_l, - trap, tst_b, tst_l, tst_w, - unlk, unknown" - (const_string "unknown")) - ;; Instruction type for use in scheduling description. ;; _l and _w suffixes indicate size of the operands of instruction. ;; alu - usual arithmetic or logic instruction. -;; alu_reg1 - arithmetic or logic instruction with one operand that is -;; a register. -;; alu_regx - arithmetic or logic instruction which has a register for its -;; X operand. ;; aluq - arithmetic or logic instruction which has a quick immediate (the one ;; that is encoded in the instruction word) for its Y operand. -;; <all other values> - corresponding asm instructions. -(define_attr "type1" - "alu_l, alu_reg1, alu_regx, aluq_l, bcc, bra, bsr, clr, cmp_l, jmp, jsr, lea, - mov3q_l, move, move_l, moveq_l, mul_l, mul_w, pea, rts, tst, tst_l, unlk, +;; alux - Arithmetic instruction that uses carry bit (e.g., addx and subx). +;; bcc - conditional branch. +;; bitr - bit operation that only updates flags. +;; bitrw - bit operation that updates flags and output operand. +;; bra, bsr, clr, cmp, div, ext - corresponding instruction. +;; falu, fbcc, fcmp, fdiv, fmove, fmul, fneg, fsqrt, ftst - corresponding +;; instruction. +;; ib - fake instruction to subscribe slots in ColdFire V1,V2,V3 instruction +;; buffer. +;; ignore - fake instruction. +;; jmp, jsr, lea, link, mov3q, move, moveq, mul - corresponding instruction. +;; mvsz - mvs or mvz instruction. +;; neg, nop, pea, rts, scc - corresponding instruction. +;; shift - arithmetic or logical shift instruction. +;; trap, tst, unlk - corresponding instruction. +(define_attr "type" + "alu_l,aluq_l,alux_l,bcc,bitr,bitrw,bra,bsr,clr,clr_l,cmp,cmp_l, + div_w,div_l,ext, + falu,fbcc,fcmp,fdiv,fmove,fmul,fneg,fsqrt,ftst, + ib,ignore, + jmp,jsr,lea,link,mov3q_l,move,move_l,moveq_l,mul_w,mul_l,mvsz,neg_l,nop, + pea,rts,scc,shift, + trap,tst,tst_l,unlk, unknown" - (cond [(eq_attr "type" "add_l,sub_l") (const_string "alu_l") - (eq_attr "type" "ext_w,extb_l,ext_l,neg_l,not_l") - (const_string "alu_reg1") - (eq_attr "type" "asr_l,lsr_l") (const_string "alu_regx") - (eq_attr "type" "addq_l,subq_l") (const_string "aluq_l") - (eq_attr "type" "bcc") (const_string "bcc") - (eq_attr "type" "bra") (const_string "bra") - (eq_attr "type" "bsr") (const_string "bsr") - (eq_attr "type" "clr_b,clr_l,clr_w") (const_string "clr") - (eq_attr "type" "cmp_l") (const_string "cmp_l") - (eq_attr "type" "jmp") (const_string "jmp") - (eq_attr "type" "jsr") (const_string "jsr") - (eq_attr "type" "lea") (const_string "lea") - (eq_attr "type" "mov3q_l") (const_string "mov3q_l") - (eq_attr "type" "move_b,move_w") (const_string "move") - (eq_attr "type" "move_l") (const_string "move_l") - (eq_attr "type" "moveq_l") (const_string "moveq_l") - (eq_attr "type" "muls_l,mulu_l") (const_string "mul_l") - (eq_attr "type" "muls_w,mulu_w") (const_string "mul_w") - (eq_attr "type" "pea") (const_string "pea") - (eq_attr "type" "rts") (const_string "rts") - (eq_attr "type" "tst_b,tst_w") (const_string "tst") - (eq_attr "type" "tst_l") (const_string "tst_l") - (eq_attr "type" "unlk") (const_string "unlk")] - (const_string "unknown"))) + (const_string "unknown")) ;; Index of the X or Y operand in recog_data.operand[]. ;; Should be used only within opx_type and opy_type. (define_attr "opx" "" (const_int 0)) (define_attr "opy" "" (const_int 1)) -;; Type of the X operand. -;; See m68k.c: enum attr_op_type. -(define_attr "opx_type" - "none, reg, mem1, mem234, mem5, mem6, mem7, imm_q, imm_w, imm_l" - (cond [(eq_attr "type1" "rts,unlk") (const_string "none") - (eq_attr "type1" "alu_reg1,alu_regx,lea,moveq_l,mul_l,mul_w") - (const_string "reg") - (eq_attr "type1" "pea") (const_string "mem1") - (eq_attr "type1" "bcc") (const_string "imm_q") - (eq_attr "type1" "bra,bsr") (const_string "imm_w") - (eq_attr "type1" "jmp,jsr") - (symbol_ref "m68k_sched_attr_opx_type (insn, 1)")] - (symbol_ref "m68k_sched_attr_opx_type (insn, 0)"))) - ;; Type of the Y operand. ;; See m68k.c: enum attr_op_type. (define_attr "opy_type" - "none, reg, mem1, mem234, mem5, mem6, mem7, imm_q, imm_w, imm_l" - (cond [(eq_attr "type1" "alu_reg1,bcc,bra,bsr,clr,jmp,jsr,rts,tst,tst_l, - unlk") (const_string "none") - (eq_attr "type1" "mov3q_l,moveq_l,aluq_l") (const_string "imm_q") - (eq_attr "type1" "lea,pea") + "none,Rn,FPn,mem1,mem234,mem5,mem6,mem7,imm_q,imm_w,imm_l" + (cond [(eq_attr "type" "ext,fbcc,ftst,neg_l,bcc,bra,bsr,clr,clr_l,ib,ignore, + jmp,jsr,nop,rts,scc,trap,tst,tst_l, + unlk,unknown") (const_string "none") + (eq_attr "type" "lea,pea") (symbol_ref "m68k_sched_attr_opy_type (insn, 1)")] (symbol_ref "m68k_sched_attr_opy_type (insn, 0)"))) -;; Instruction size in words. -(define_attr "size" "" - (cond [(eq_attr "type1" "alu_reg1,moveq_l,rts,unlk") (const_int 1)] - (symbol_ref "m68k_sched_attr_size (insn)"))) +;; Type of the X operand. +;; See m68k.c: enum attr_op_type. +(define_attr "opx_type" + "none,Rn,FPn,mem1,mem234,mem5,mem6,mem7,imm_q,imm_w,imm_l" + (cond [(eq_attr "type" "ib,ignore,nop,rts,trap,unlk, + unknown") (const_string "none") + (eq_attr "type" "pea") (const_string "mem1") + (eq_attr "type" "jmp,jsr") + (symbol_ref "m68k_sched_attr_opx_type (insn, 1)")] + (symbol_ref "m68k_sched_attr_opx_type (insn, 0)"))) ;; Access to the X operand: none, read, write, read/write, unknown. ;; Access to the Y operand is either none (if opy_type is none) ;; or read otherwise. -(define_attr "opx_access" "none, r, w, rw, unknown" - (cond [(eq_attr "type1" "rts,unlk") (const_string "none") - (eq_attr "type1" "bcc,bra,bsr,cmp_l,jmp,jsr,tst,tst_l") - (const_string "r") - (eq_attr "type1" "clr,lea,mov3q_l,move,move_l,moveq_l,pea") - (const_string "w") - (eq_attr "type1" "alu_l,alu_reg1,alu_regx,aluq_l") - (const_string "rw")] - (const_string "unknown"))) - -;; Memory relation of operands: -;; r - register or immediate operand -;; m - non-indexed memory location -;; i - indexed memory location - -(define_attr "opx_mem" "r, m, i, unknown" - (cond [(eq_attr "opx_type" "none,reg,imm_q,imm_w,imm_l") (const_string "r") - (eq_attr "opx_type" "mem1,mem234,mem5,mem7") (const_string "m") - (eq_attr "opx_type" "mem6") (const_string "i")] - (const_string "unknown"))) - -(define_attr "opy_mem" "r, m, i, unknown" - (cond [(eq_attr "opy_type" "none,reg,imm_q,imm_w,imm_l") (const_string "r") - (eq_attr "opy_type" "mem1,mem234,mem5,mem7") (const_string "m") - (eq_attr "opy_type" "mem6") (const_string "i")] - (const_string "unknown"))) +(define_attr "opx_access" "none, r, w, rw" + (cond [(eq_attr "type" "ib,ignore,nop,rts,trap,unlk, + unknown") (const_string "none") + (eq_attr "type" "bcc,bra,bsr,bitr,cmp,cmp_l,fbcc,fcmp,ftst, + jmp,jsr,tst,tst_l") (const_string "r") + (eq_attr "type" "clr,clr_l,fneg,fmove,lea, + mov3q_l,move,move_l,moveq_l,mvsz, + pea,scc") (const_string "w") + (eq_attr "type" "alu_l,aluq_l,alux_l,bitrw,div_w,div_l,ext, + falu,fdiv,fmul,fsqrt,link,mul_w,mul_l, + neg_l,shift") (const_string "rw")] + ;; Should never be used. + (symbol_ref "(gcc_unreachable (), OPX_ACCESS_NONE)"))) ;; Memory accesses of the insn. ;; 00 - no memory references ;; 10 - memory is read -;; i10 - indexed memory is read +;; i0 - indexed memory is read ;; 01 - memory is written -;; 0i1 - indexed memory is written +;; 0i - indexed memory is written ;; 11 - memory is read, memory is written -;; i11 - indexed memory is read, memory is written -;; 1i1 - memory is read, indexed memory is written -;; -;; unknown - should now occur on normal insn. -;; ??? This attribute is implemented in C to spare genattrtab from -;; ??? optimizing it. -(define_attr "op_mem" "00, 10, i0, 01, 0i, 11, i1, 1i, unknown" -; (cond [(and (eq_attr "opy_mem" "r") (eq_attr "opx_mem" "r")) -; (const_string "00") -; -; (and (eq_attr "opy_mem" "r") (eq_attr "opx_mem" "m")) -; (cond [(eq_attr "opx_access" "r") (const_string "10") -; (eq_attr "opx_access" "w") (const_string "01") -; (eq_attr "opx_access" "rw") (const_string "11")] -; (const_string "unknown")) -; -; (and (eq_attr "opy_mem" "r") (eq_attr "opx_mem" "i")) -; (cond [(eq_attr "opx_access" "r") (const_string "i0") -; (eq_attr "opx_access" "w") (const_string "0i") -; (eq_attr "opx_access" "rw") (const_string "i1")] -; (const_string "unknown")) -; -; (and (eq_attr "opy_mem" "m") (eq_attr "opx_mem" "r")) -; (const_string "10") -; -; (and (eq_attr "opy_mem" "m") (eq_attr "opx_mem" "m")) -; (cond [(eq_attr "opx_access" "w") (const_string "11")] -; (const_string "unknown")) -; -; (and (eq_attr "opy_mem" "m") (eq_attr "opx_mem" "i")) -; (cond [(eq_attr "opx_access" "w") (const_string "1i")] -; (const_string "unknown")) -; -; (and (eq_attr "opy_mem" "i") (eq_attr "opx_mem" "r")) -; (const_string "i0") -; -; (and (eq_attr "opy_mem" "i") (eq_attr "opx_mem" "m")) -; (cond [(eq_attr "opx_access" "w") (const_string "i1")] -; (const_string "unknown"))] -; (const_string "unknown")) +;; i1 - indexed memory is read, memory is written +;; 1i - memory is read, indexed memory is written +(define_attr "op_mem" "00, 10, i0, 01, 0i, 11, i1, 1i" (symbol_ref "m68k_sched_attr_op_mem (insn)")) -;; Attribute to support partial automata description. -;; This attribute has value 'yes' for instructions that are not -;; fully handled yet. -(define_attr "guess" "yes, no" - (cond [(ior (eq (symbol_ref "reload_completed") (const_int 0)) - (eq_attr "type1" "unknown")) - (const_string "yes")] - (const_string "no"))) - -;; Attribute to support statistics gathering. -;; Todo means that insn lacks something to get pipeline description. -;; Done means that insn was transformed to suit pipeline description. -;; Nothing means that insn was originally good enough for scheduling. -(define_attr "split" "todo, done, nothing" - (if_then_else (eq_attr "type" "unknown") - (const_string "todo") - (const_string "nothing"))) +;; Instruction size in words. +(define_attr "size" "1,2,3" + (symbol_ref "m68k_sched_attr_size (insn)")) + ;; Mode macros for floating point operations. ;; Valid floating point modes @@ -369,8 +272,7 @@ m68k_emit_move_double (operands); DONE; } - [(set_attr "type" "fmove,*") - (set_attr "split" "done,*")]) + [(set_attr "type" "fmove,*")]) (define_insn_and_split "pushdi" [(set (match_operand:DI 0 "push_operand" "=m") @@ -450,7 +352,7 @@ "@ tst%.l %0 cmp%.w #0,%0" - [(set_attr "type" "tst_l,*")]) + [(set_attr "type" "tst_l,cmp")]) ;; This can't use an address register, because comparisons ;; with address registers as second operand always test the whole word. @@ -465,7 +367,7 @@ (match_operand:HI 0 "nonimmediate_operand" "dm"))] "" "tst%.w %0" - [(set_attr "type" "tst_w")]) + [(set_attr "type" "tst")]) (define_expand "tstqi" [(set (cc0) @@ -478,7 +380,7 @@ (match_operand:QI 0 "nonimmediate_operand" "dm"))] "" "tst%.b %0" - [(set_attr "type" "tst_b")]) + [(set_attr "type" "tst")]) (define_expand "tst<mode>" [(set (cc0) @@ -497,7 +399,8 @@ if (FP_REG_P (operands[0])) return "ftst%.x %0"; return "ftst%.<FP:prec> %0"; -}) +} + [(set_attr "type" "ftst")]) (define_insn "tst<mode>_cf" [(set (cc0) @@ -605,7 +508,7 @@ if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1])) || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) { - cc_status.flags |= CC_REVERSED; + cc_status.flags |= CC_REVERSED; /*|*/ return "cmp%.w %d0,%d1"; } return "cmp%.w %d1,%d0"; @@ -797,8 +700,7 @@ clr%.l %0 mov3q%.l %1,%- pea %a1" - [(set_attr "type" "clr_l,mov3q_l,pea") - (set_attr "split" "done")]) + [(set_attr "type" "clr_l,mov3q_l,pea")]) ;This is never used. ;(define_insn "swapsi" @@ -818,9 +720,8 @@ moveq #0,%0 sub%.l %0,%0 clr%.l %0" - [(set_attr "type" "moveq_l,sub_l,clr_l") - (set_attr "opy_type" "imm_q,reg,*") - (set_attr "split" "done")]) + [(set_attr "type" "moveq_l,alu_l,clr_l") + (set_attr "opy" "*,0,*")]) ;; Special case of fullword move when source is zero for 68040_60. ;; On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 @@ -839,9 +740,7 @@ return ""; } } - [(set_attr "type" "lea,clr_l") - (set_attr "opy_type" "imm_w,*") - (set_attr "split" "done")]) + [(set_attr "type" "lea,clr_l")]) ;; Special case of fullword move when source is zero. (define_insn "*movsi_const0" @@ -851,9 +750,8 @@ "@ sub%.l %0,%0 clr%.l %0" - [(set_attr "type" "sub_l,clr_l") - (set_attr "opy_type" "reg,*") - (set_attr "split" "done")]) + [(set_attr "type" "alu_l,clr_l") + (set_attr "opy" "0,*")]) ;; General case of fullword move. ;; @@ -978,11 +876,7 @@ return ""; } } - [(set_attr "type" "mov3q_l, moveq_l,*, mvz_w, mvs_w, move_l, move_w, pea, lea, move_l, move_l, move_l") - (set (attr "split") - (if_then_else (eq_attr "alternative" "2") - (const_string "*") - (const_string "done")))]) + [(set_attr "type" "mov3q_l,moveq_l,*,mvsz,mvsz,move_l,move,pea,lea,move_l,move_l,move_l")]) ;; Special case of fullword move, where we need to get a non-GOT PIC ;; reference into an address register. @@ -1071,8 +965,7 @@ clr%.b %0 move%.b %1,%0 move%.b %1,%0" - [(set_attr "type" "clr_b,clr_b,move_b,move_b") - (set_attr "split" "done")]) + [(set_attr "type" "clr,clr,move,move")]) (define_expand "pushqi1" [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -2))) @@ -1693,7 +1586,7 @@ (zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))] "ISA_HAS_MVS_MVZ" "mvz%.w %1,%0" - [(set_attr "type" "mvz_w")]) + [(set_attr "type" "mvsz")]) (define_insn "zero_extendhisi2" [(set (match_operand:SI 0 "register_operand" "=d") @@ -1718,7 +1611,7 @@ (zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "dmS")))] "ISA_HAS_MVS_MVZ" "mvz%.b %1,%0" - [(set_attr "type" "mvz_b")]) + [(set_attr "type" "mvsz")]) (define_insn "zero_extendqisi2" [(set (match_operand:SI 0 "register_operand" "=d") @@ -1871,7 +1764,7 @@ (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))] "ISA_HAS_MVS_MVZ" "mvs%.w %1,%0" - [(set_attr "type" "mvs_w")]) + [(set_attr "type" "mvsz")]) (define_insn "*68k_extendhisi2" [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,a") @@ -1881,14 +1774,14 @@ "@ ext%.l %0 move%.w %1,%0" - [(set_attr "type" "ext_l,move_w")]) + [(set_attr "type" "ext,move")]) (define_insn "extendqihi2" [(set (match_operand:HI 0 "nonimmediate_operand" "=d") (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))] "" "ext%.w %0" - [(set_attr "type" "ext_w")]) + [(set_attr "type" "ext")]) (define_expand "extendqisi2" [(set (match_operand:SI 0 "nonimmediate_operand" "") @@ -1901,14 +1794,14 @@ (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rms")))] "ISA_HAS_MVS_MVZ" "mvs%.b %1,%0" - [(set_attr "type" "mvs_b")]) + [(set_attr "type" "mvsz")]) (define_insn "*68k_extendqisi2" [(set (match_operand:SI 0 "nonimmediate_operand" "=d") (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))] "TARGET_68020 || (TARGET_COLDFIRE && !ISA_HAS_MVS_MVZ)" "extb%.l %0" - [(set_attr "type" "extb_l")]) + [(set_attr "type" "ext")]) ;; Conversions between float and double. @@ -2026,7 +1919,8 @@ [(set (match_operand:FP 0 "nonimmediate_operand" "=f") (float:FP (match_operand:SI 1 "general_operand" "dmi")))] "TARGET_68881" - "f<FP:round>move%.l %1,%0") + "f<FP:round>move%.l %1,%0" + [(set_attr "type" "fmove")]) (define_insn "floatsi<mode>2_cf" [(set (match_operand:FP 0 "nonimmediate_operand" "=f") @@ -2133,7 +2027,8 @@ if (FP_REG_P (operands[1])) return "fintrz%.x %f1,%0"; return "fintrz%.<FP:prec> %f1,%0"; -}) +} + [(set_attr "type" "falu")]) (define_insn "ftrunc<mode>2_cf" [(set (match_operand:FP 0 "nonimmediate_operand" "=f") @@ -2144,7 +2039,7 @@ return "fintrz%.d %f1,%0"; return "fintrz%.<FP:prec> %f1,%0"; } - [(set_attr "type" "fintrz")]) + [(set_attr "type" "falu")]) ;; Convert a float whose value is an integer ;; to an actual integer. Second stage of converting float to integer type. @@ -2158,7 +2053,8 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=dm") (fix:QI (match_operand:FP 1 "general_operand" "f")))] "TARGET_68881" - "fmove%.b %1,%0") + "fmove%.b %1,%0" + [(set_attr "type" "fmove")]) (define_insn "fix<mode>qi2_cf" [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>U") @@ -2177,7 +2073,8 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "=dm") (fix:HI (match_operand:FP 1 "general_operand" "f")))] "TARGET_68881" - "fmove%.w %1,%0") + "fmove%.w %1,%0" + [(set_attr "type" "fmove")]) (define_insn "fix<mode>hi2_cf" [(set (match_operand:HI 0 "nonimmediate_operand" "=d<Q>U") @@ -2196,7 +2093,8 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=dm") (fix:SI (match_operand:FP 1 "general_operand" "f")))] "TARGET_68881" - "fmove%.l %1,%0") + "fmove%.l %1,%0" + [(set_attr "type" "fmove")]) (define_insn "fix<mode>si2_cf" [(set (match_operand:SI 0 "nonimmediate_operand" "=d<Q>U") @@ -2302,7 +2200,7 @@ operands[1] = adjust_address (operands[1], SImode, 4); return "add%.l %1,%0"; } - [(set_attr "type" "add_l")]) + [(set_attr "type" "alu_l")]) (define_insn "adddi3" [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,d,d,d") @@ -2469,10 +2367,9 @@ (plus:SI (match_dup 0) (match_dup 1)))] "" - [(set_attr "type" "addq_l,subq_l,add_l,add_l,*,lea,lea,lea") + [(set_attr "type" "aluq_l,aluq_l,alu_l,alu_l,*,lea,lea,lea") (set_attr "opy" "2,2,2,2,*,*,*,*") - (set_attr "opy_type" "*,*,*,*,*,mem6,mem6,mem5") - (set_attr "split" "done,done,done,done,*,done,done,done")]) + (set_attr "opy_type" "*,*,*,*,*,mem6,mem6,mem5")]) (define_insn "" [(set (match_operand:SI 0 "nonimmediate_operand" "=a") @@ -2716,21 +2613,27 @@ (plus:FP (float:FP (match_operand:SI 2 "general_operand" "dmi")) (match_operand:FP 1 "general_operand" "0")))] "TARGET_68881" - "f<FP:round>add%.l %2,%0") + "f<FP:round>add%.l %2,%0" + [(set_attr "type" "falu") + (set_attr "opy" "2")]) (define_insn "add<mode>3_floathi_68881" [(set (match_operand:FP 0 "nonimmediate_operand" "=f") (plus:FP (float:FP (match_operand:HI 2 "general_operand" "dmn")) (match_operand:FP 1 "general_operand" "0")))] "TARGET_68881" - "f<FP:round>add%.w %2,%0") + "f<FP:round>add%.w %2,%0" + [(set_attr "type" "falu") + (set_attr "opy" "2")]) (define_insn "add<mode>3_floatqi_68881" [(set (match_operand:FP 0 "nonimmediate_operand" "=f") (plus:FP (float:FP (match_operand:QI 2 "general_operand" "dmn")) (match_operand:FP 1 "general_operand" "0")))] "TARGET_68881" - "f<FP:round>add%.b %2,%0") + "f<FP:round>add%.b %2,%0" + [(set_attr "type" "falu") + (set_attr "opy" "2")]) (define_insn "add<mode>3_68881" [(set (match_operand:FP 0 "nonimmediate_operand" "=f") @@ -2741,7 +2644,9 @@ if (FP_REG_P (operands[2])) return "f<FP:round>add%.x %2,%0"; return "f<FP:round>add%.<FP:prec> %f2,%0"; -}) +} + [(set_attr "type" "falu") + (set_attr "opy" "2")]) (define_insn "add<mode>3_cf" [(set (match_operand:FP 0 "nonimmediate_operand" "=f") @@ -2753,7 +2658,8 @@ return "f<FP:prec>add%.d %2,%0"; return "f<FP:prec>add%.<FP:prec> %2,%0"; } - [(set_attr "type" "fadd")]) + [(set_attr "type" "falu") + (set_attr "opy" "2")]) ;; subtract instructions @@ -2788,7 +2694,7 @@ operands[1] = adjust_address (operands[1], SImode, 4); return "sub%.l %1,%0"; } - [(set_attr "type" "sub_l")]) + [(set_attr "type" "alu_l")]) (define_insn "subdi3" [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,d,d,d") @@ -2879,7 +2785,7 @@ sub%.l %2,%0 sub%.l %2,%0 sub%.l %2,%0" - [(set_attr "type" "subq_l,sub_l,sub_l,sub_l") + [(set_attr "type" "aluq_l,alu_l,alu_l,alu_l") (set_attr "opy" "2")]) (define_insn "" @@ -2930,21 +2836,27 @@ (minus:FP (match_operand:FP 1 "general_operand" "0") (float:FP (match_operand:SI 2 "general_operand" "dmi"))))] "TARGET_68881" - "f<FP:round>sub%.l %2,%0") + "f<FP:round>sub%.l %2,%0" + [(set_attr "type" "falu") + (set_attr "opy" "2")]) (define_insn "sub<mode>3_floathi_68881" [(set (match_operand:FP 0 "nonimmediate_operand" "=f") (minus:FP (match_operand:FP 1 "general_operand" "0") (float:FP (match_operand:HI 2 "general_operand" "dmn"))))] "TARGET_68881" - "f<FP:round>sub%.w %2,%0") + "f<FP:round>sub%.w %2,%0" + [(set_attr "type" "falu") + (set_attr "opy" "2")]) (define_insn "sub<mode>3_floatqi_68881" [(set (match_operand:FP 0 "nonimmediate_operand" "=f") (minus:FP (match_operand:FP 1 "general_operand" "0") (float:FP (match_operand:QI 2 "general_operand" "dmn"))))] "TARGET_68881" - "f<FP:round>sub%.b %2,%0") + "f<FP:round>sub%.b %2,%0" + [(set_attr "type" "falu") + (set_attr "opy" "2")]) (define_insn "sub<mode>3_68881" [(set (match_operand:FP 0 "nonimmediate_operand" "=f") @@ -2955,7 +2867,9 @@ if (FP_REG_P (operands[2])) return "f<FP:round>sub%.x %2,%0"; return "f<FP:round>sub%.<FP:prec> %f2,%0"; -}) +} + [(set_attr "type" "falu") + (set_attr "opy" "2")]) (define_insn "sub<mode>3_cf" [(set (match_operand:FP 0 "nonimmediate_operand" "=f") @@ -2967,7 +2881,8 @@ return "f<FP:prec>sub%.d %2,%0"; return "f<FP:prec>sub%.<FP:prec> %2,%0"; } - [(set_attr "type" "fsub")]) + [(set_attr "type" "falu") + (set_attr "opy" "2")]) ;; multiply instructions @@ -2979,7 +2894,7 @@ { return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0"; } - [(set_attr "type" "muls_w") + [(set_attr "type" "mul_w") (set_attr "opy" "2")]) (define_insn "mulhisi3" @@ -2992,7 +2907,7 @@ { return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0"; } - [(set_attr "type" "muls_w") + [(set_attr "type" "mul_w") (set_attr "opy" "2")]) (define_insn "*mulhisisi3_s" @@ -3004,7 +2919,7 @@ { return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0"; } - [(set_attr "type" "muls_w") + [(set_attr "type" "mul_w") (set_attr "opy" "2")]) (define_expand "mulsi3" @@ -3021,7 +2936,7 @@ "TARGET_68020" "muls%.l %2,%0" - [(set_attr "type" "muls_l") + [(set_attr "type" "mul_l") (set_attr "opy" "2")]) (define_insn "*mulsi3_cf" @@ -3030,7 +2945,7 @@ (match_operand:SI 2 "general_operand" "d<Q>")))] "TARGET_COLDFIRE" "muls%.l %2,%0" - [(set_attr "type" "muls_l") + [(set_attr "type" "mul_l") (set_attr "opy" "2")]) (define_insn "umulhisi3" @@ -3043,7 +2958,7 @@ { return MOTOROLA ? "mulu%.w %2,%0" : "mulu %2,%0"; } - [(set_attr "type" "mulu_w") + [(set_attr "type" "mul_w") (set_attr "opy" "2")]) (define_insn "*mulhisisi3_z" @@ -3055,7 +2970,7 @@ { return MOTOROLA ? "mulu%.w %2,%0" : "mulu %2,%0"; } - [(set_attr "type" "mulu_w") + [(set_attr "type" "mul_w") (set_attr "opy" "2")]) ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the @@ -3240,7 +3155,9 @@ return TARGET_68040 ? "f<FP:round>mul%.l %2,%0" : "f<FP:round_mul>mul%.l %2,%0"; -}) +} + [(set_attr "type" "fmul") + (set_attr "opy" "2")]) (define_insn "mul<mode>3_floathi_68881" [(set (match_operand:FP 0 "nonimmediate_operand" "=f") @@ -3251,7 +3168,9 @@ return TARGET_68040 ? "f<FP:round>mul%.w %2,%0" : "f<FP:round_mul>mul%.w %2,%0"; -}) +} + [(set_attr "type" "fmul") + (set_attr "opy" "2")]) (define_insn "mul<mode>3_floatqi_68881" [(set (match_operand:FP 0 "nonimmediate_operand" "=f") @@ -3262,7 +3181,9 @@ return TARGET_68040 ? "f<FP:round>mul%.b %2,%0" : "f<FP:round_mul>mul%.b %2,%0"; -}) +} + [(set_attr "type" "fmul") + (set_attr "opy" "2")]) (define_insn "muldf_68881" [(set (match_operand:DF 0 "nonimmediate_operand" "=f") @@ -3316,7 +3237,8 @@ return "f<FP:prec>mul%.d %2,%0"; return "f<FP:prec>mul%.<FP:prec> %2,%0"; } - [(set_attr "type" "fmul")]) + [(set_attr "type" "fmul") + (set_attr "opy" "2")]) ;; divide instructions @@ -3385,7 +3307,8 @@ return "f<FP:prec>div%.d %2,%0"; return "f<FP:prec>div%.<FP:prec> %2,%0"; } - [(set_attr "type" "fdiv")]) + [(set_attr "type" "fdiv") + (set_attr "opy" "2")]) ;; Remainder instructions. @@ -3413,7 +3336,9 @@ return "rems%.l %2,%3:%0"; else return "rems%.l %2,%3:%0\;divs%.l %2,%0"; -}) +} + [(set_attr "type" "div_l") + (set_attr "opy" "2")]) (define_insn "" [(set (match_operand:SI 0 "nonimmediate_operand" "=d") @@ -3453,7 +3378,9 @@ return "remu%.l %2,%3:%0"; else return "remu%.l %2,%3:%0\;divu%.l %2,%0"; -}) +} + [(set_attr "type" "div_l") + (set_attr "opy" "2")]) (define_insn "" [(set (match_operand:SI 0 "nonimmediate_operand" "=d") @@ -4261,7 +4188,8 @@ if (FP_REG_P (operands[1])) return "f<FP:prec>sqrt%.d %1,%0"; return "f<FP:prec>sqrt%.<FP:prec> %1,%0"; -}) +} + [(set_attr "type" "fsqrt")]) ;; Absolute value instructions ;; If using software floating point, just zero the sign bit. @@ -4384,7 +4312,8 @@ if (FP_REG_P (operands[1])) return "f<FP:prec>abs%.d %1,%0"; return "f<FP:prec>abs%.<FP:prec> %1,%0"; -}) +} + [(set_attr "type" "bitrw,fneg")]) ;; bit indexing instructions @@ -4394,7 +4323,7 @@ (clz:SI (match_operand:SI 1 "register_operand" "0")))] "ISA_HAS_FF1" "ff1 %0" - [(set_attr "type" "ff1")]) + [(set_attr "type" "ext")]) ;; one complement instructions @@ -4438,7 +4367,7 @@ (not:SI (match_operand:SI 1 "general_operand" "0")))] "TARGET_COLDFIRE" "not%.l %0" - [(set_attr "type" "not_l")]) + [(set_attr "type" "neg_l")]) (define_insn "one_cmplhi2" [(set (match_operand:HI 0 "nonimmediate_operand" "=dm") @@ -4790,7 +4719,7 @@ operands[1] = adjust_address (operands[1], HImode, 2); return "move%.w %1,%0"; } - [(set_attr "type" "move_w")]) + [(set_attr "type" "move")]) (define_insn "subregsi1ashrdi_const32" [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") @@ -4970,7 +4899,7 @@ (match_operand:SI 2 "general_operand" "dI")))] "" "asr%.l %2,%0" - [(set_attr "type" "asr_l") + [(set_attr "type" "shift") (set_attr "opy" "2")]) (define_insn "ashrhi3" @@ -5266,7 +5195,7 @@ (match_operand:SI 2 "general_operand" "dI")))] "" "lsr%.l %2,%0" - [(set_attr "type" "lsr_l") + [(set_attr "type" "shift") (set_attr "opy" "2")]) (define_insn "lshrhi3" @@ -5425,7 +5354,7 @@ CC_STATUS_INIT; return "bset %1,%0"; } - [(set_attr "type" "bset")]) + [(set_attr "type" "bitrw")]) ;; set bit, bit number is (sign/zero)_extended from HImode/QImode (define_insn "*bsetmemqi_ext" @@ -5439,7 +5368,7 @@ CC_STATUS_INIT; return "bset %1,%0"; } - [(set_attr "type" "bset")]) + [(set_attr "type" "bitrw")]) ;; clear bit, bit number is int (define_insn "bclrmemqi" @@ -5453,7 +5382,7 @@ CC_STATUS_INIT; return "bclr %1,%0"; } - [(set_attr "type" "bclr")]) + [(set_attr "type" "bitrw")]) ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode (define_insn "*bclrmemqi_ext" @@ -5468,7 +5397,7 @@ CC_STATUS_INIT; return "bclr %1,%0"; } - [(set_attr "type" "bclr")]) + [(set_attr "type" "bitrw")]) ;; Special cases of bit-field insns which we should ;; recognize in preference to the general case. @@ -6418,8 +6347,7 @@ { OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0"); } - [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)")) - (set_attr "split" "done")]) + [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))]) (define_insn "bne" [(set (pc) @@ -6431,8 +6359,7 @@ { OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0"); } - [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)")) - (set_attr "split" "done")]) + [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))]) (define_insn "bgt" [(set (pc) @@ -6444,8 +6371,7 @@ { OUTPUT_JUMP ("jgt %l0", "fjgt %l0", 0); } - [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)")) - (set_attr "split" "done")]) + [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))]) (define_insn "bgtu" [(set (pc) @@ -6467,8 +6393,7 @@ { OUTPUT_JUMP ("jlt %l0", "fjlt %l0", "jmi %l0"); } - [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)")) - (set_attr "split" "done")]) + [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))]) (define_insn "bltu" [(set (pc) @@ -6532,7 +6457,8 @@ { gcc_assert (cc_prev_status.flags & CC_IN_68881); return "fjor %l0"; -}) +} + [(set_attr "type" "fbcc")]) (define_insn "bunordered" [(set (pc) @@ -6543,7 +6469,8 @@ { gcc_assert (cc_prev_status.flags & CC_IN_68881); return "fjun %l0"; -}) +} + [(set_attr "type" "fbcc")]) (define_insn "buneq" [(set (pc) @@ -6554,7 +6481,8 @@ { gcc_assert (cc_prev_status.flags & CC_IN_68881); return "fjueq %l0"; -}) +} + [(set_attr "type" "fbcc")]) (define_insn "bunge" [(set (pc) @@ -6565,7 +6493,8 @@ { gcc_assert (cc_prev_status.flags & CC_IN_68881); return "fjuge %l0"; -}) +} + [(set_attr "type" "fbcc")]) (define_insn "bungt" [(set (pc) @@ -6576,7 +6505,8 @@ { gcc_assert (cc_prev_status.flags & CC_IN_68881); return "fjugt %l0"; -}) +} + [(set_attr "type" "fbcc")]) (define_insn "bunle" [(set (pc) @@ -6587,7 +6517,8 @@ { gcc_assert (cc_prev_status.flags & CC_IN_68881); return "fjule %l0"; -}) +} + [(set_attr "type" "fbcc")]) (define_insn "bunlt" [(set (pc) @@ -6598,7 +6529,8 @@ { gcc_assert (cc_prev_status.flags & CC_IN_68881); return "fjult %l0"; -}) +} + [(set_attr "type" "fbcc")]) (define_insn "bltgt" [(set (pc) @@ -6609,7 +6541,8 @@ { gcc_assert (cc_prev_status.flags & CC_IN_68881); return "fjogl %l0"; -}) +} + [(set_attr "type" "fbcc")]) ;; Negated conditional jump instructions. @@ -6734,7 +6667,8 @@ { gcc_assert (cc_prev_status.flags & CC_IN_68881); return "fjun %l0"; -}) +} + [(set_attr "type" "fbcc")]) (define_insn "*bunordered_rev" [(set (pc) @@ -6745,7 +6679,8 @@ { gcc_assert (cc_prev_status.flags & CC_IN_68881); return "fjor %l0"; -}) +} + [(set_attr "type" "fbcc")]) (define_insn "*buneq_rev" [(set (pc) @@ -6756,7 +6691,8 @@ { gcc_assert (cc_prev_status.flags & CC_IN_68881); return "fjogl %l0"; -}) +} + [(set_attr "type" "fbcc")]) (define_insn "*bunge_rev" [(set (pc) @@ -6767,7 +6703,8 @@ { gcc_assert (cc_prev_status.flags & CC_IN_68881); return "fjolt %l0"; -}) +} + [(set_attr "type" "fbcc")]) (define_insn "*bungt_rev" [(set (pc) @@ -6778,7 +6715,8 @@ { gcc_assert (cc_prev_status.flags & CC_IN_68881); return "fjole %l0"; -}) +} + [(set_attr "type" "fbcc")]) (define_insn "*bunle_rev" [(set (pc) @@ -6789,7 +6727,8 @@ { gcc_assert (cc_prev_status.flags & CC_IN_68881); return "fjogt %l0"; -}) +} + [(set_attr "type" "fbcc")]) (define_insn "*bunlt_rev" [(set (pc) @@ -6800,7 +6739,8 @@ { gcc_assert (cc_prev_status.flags & CC_IN_68881); return "fjoge %l0"; -}) +} + [(set_attr "type" "fbcc")]) (define_insn "*bltgt_rev" [(set (pc) @@ -6811,7 +6751,8 @@ { gcc_assert (cc_prev_status.flags & CC_IN_68881); return "fjueq %l0"; -}) +} + [(set_attr "type" "fbcc")]) ;; Unconditional and other jump instructions (define_insn "jump" @@ -6840,7 +6781,7 @@ { return MOTOROLA ? "jmp (%0)" : "jmp %0@"; } - [(set_attr "type" "bra")]) + [(set_attr "type" "jmp")]) ;; Jump to variable address from dispatch table of relative addresses. (define_insn "" @@ -7018,7 +6959,8 @@ "!SIBLING_CALL_P (insn)" { return output_call (operands[0]); -}) +} + [(set_attr "type" "jsr")]) ;; Call subroutine, returning value in operand 0 ;; (which must be a hard register). @@ -7040,7 +6982,6 @@ "!SIBLING_CALL_P (insn)" "jsr %a1" [(set_attr "type" "jsr") - (set_attr "split" "done") (set_attr "opx" "1")]) (define_insn "*symbolic_call_value_jsr" @@ -7054,7 +6995,6 @@ return m68k_symbolic_call; } [(set_attr "type" "jsr") - (set_attr "split" "done") (set_attr "opx" "1")]) (define_insn "*symbolic_call_value_bsr" @@ -7070,7 +7010,6 @@ return m68k_symbolic_call; } [(set_attr "type" "bsr") - (set_attr "split" "done") (set_attr "opx" "1")]) ;; Call subroutine returning any type. @@ -7236,7 +7175,8 @@ return "link.w %0,%1"; else return "link.l %0,%1"; -}) +} + [(set_attr "type" "link")]) (define_expand "unlink" [(parallel @@ -7726,6 +7666,17 @@ } }) +;; These are to prevent the scheduler from moving stores to the frame +;; before the stack adjustment. +(define_insn "stack_tie" + [(set (mem:BLK (scratch)) + (unspec:BLK [(match_operand:SI 0 "register_operand" "r") + (match_operand:SI 1 "register_operand" "r")] + UNSPEC_TIE))] + "" + "" + [(set_attr "type" "ignore")]) + ;; Instruction that subscribes one word in ColdFire instruction buffer. ;; This instruction is used within scheduler only and should not appear ;; in the instruction stream. |