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-rw-r--r--gcc/ChangeLog39
-rw-r--r--gcc/config/i386/i386.c5
-rw-r--r--gcc/config/i386/i386.h2
-rw-r--r--gcc/config/i386/i386.md78
-rw-r--r--gcc/config/i386/predicates.md4
5 files changed, 51 insertions, 77 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 50b9dc2..bb92e10 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,30 @@
+2009-11-13 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/41900
+ (*call_pop_1, *call_1, *call_value_pop_1, *call_value_1): Use "lsm"
+ as operand 1 constraint.
+ * config/i386/predicates.md (call_insn_operand): Depend on
+ index_register_operand to avoid %esp register.
+
+2009-11-13 Uros Bizjak <ubizjak@gmail.com>
+
+ Revert:
+ 2009-11-03 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/41900
+ * config/i386/i386.h (ix86_arch_indices) <X86_ARCH_CALL_ESP>: New.
+ (TARGET_CALL_ESP): New define.
+ * config/i386/i386.c (initial_ix86_tune_features): Initialize
+ X86_ARCH_CALL_ESP.
+ * config/i386/i386.md (*call_pop_1_esp, *call_1_esp,
+ *call_value_pop_1_esp, *call_value_1_esp): Rename from *call_pop_1,
+ *call_1, *call_value_pop_1 and *call_value_1. Depend on
+ TARGET_CALL_ESP.
+ (*call_pop_1, *call_1, *call_value_pop_1, *call_value_1):
+ New patterns, use "lsm" as operand 1 constraint.
+ * config/i386/predicates.md (call_insn_operand): Depend on
+ index_register_operand for !TARGET_CALL_ESP to avoid %esp register.
+
2009-11-13 Jason Merrill <jason@redhat.com>
PR debug/26965
@@ -6,9 +33,9 @@
2009-11-13 Andrey Belevantsev <abel@ispras.ru>
- PR rtl-optimization/41697
- * sel-sched-ir.c (fallthru_bb_of_jump): Bail out when a block with
- a conditional jump has a single successor.
+ PR rtl-optimization/41697
+ * sel-sched-ir.c (fallthru_bb_of_jump): Bail out when a block with
+ a conditional jump has a single successor.
2009-11-13 Andrey Belevantsev <abel@ispras.ru>
@@ -31,8 +58,8 @@
per-insn data in smaller chunks.
* sel-sched-ir.h (free_data_for_scheduled_insn): Export.
* sel-sched.c (update_seqnos_and_stage): Free INSN_DEPS_CONTEXT
- in scheduled insn.
-
+ in scheduled insn.
+
2009-11-13 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (call_value): Fix comment.
@@ -101,7 +128,7 @@
PR middle-end/41440
* cfgexpand.c (expand_gimple_basic_block): Append NOP to a fallthru,
single successor block, ending with jump created by RTL expander.
-
+
2009-11-11 Jan Hubicka <jh@suse.cz>
PR middle-end/41729
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 8630640..69e4e61 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -1553,11 +1553,6 @@ static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
/* X86_ARCH_BSWAP: Byteswap was added for 80486. */
~m_386,
-
- /* X86_ARCH_CALL_ESP: P6 processors will jump to the address after
- the decrement (so they will execute return address as code). See
- Pentium Pro errata 70, Pentium 2 errata A33, Pentium 3 errata E17. */
- ~(m_386 | m_486 | m_PENT | m_PPRO),
};
static const unsigned int x86_accumulate_outgoing_args
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 4bc8ef1..eb1c86f 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -402,7 +402,6 @@ enum ix86_arch_indices {
X86_ARCH_CMPXCHG8B,
X86_ARCH_XADD,
X86_ARCH_BSWAP,
- X86_ARCH_CALL_ESP,
X86_ARCH_LAST
};
@@ -414,7 +413,6 @@ extern unsigned char ix86_arch_features[X86_ARCH_LAST];
#define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B]
#define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
#define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
-#define TARGET_CALL_ESP ix86_arch_features[X86_ARCH_CALL_ESP]
#define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 2a31366..d896205 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -14562,6 +14562,10 @@
;; checked for calls. This is a bug in the generic code, but it isn't that
;; easy to fix. Ignore it for now and be prepared to fix things up.
+;; P6 processors will jump to the address after the decrement when %esp
+;; is used as a call operand, so they will execute return address as a code.
+;; See Pentium Pro errata 70, Pentium 2 errata A33 and Pentium 3 errata E17.
+
;; Call subroutine returning no value.
(define_expand "call_pop"
@@ -14592,27 +14596,13 @@
}
[(set_attr "type" "call")])
-(define_insn "*call_pop_1_esp"
- [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
- (match_operand:SI 1 "" ""))
- (set (reg:SI SP_REG)
- (plus:SI (reg:SI SP_REG)
- (match_operand:SI 2 "immediate_operand" "i")))]
- "!TARGET_64BIT && TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
-{
- if (constant_call_address_operand (operands[0], Pmode))
- return "call\t%P0";
- return "call\t%A0";
-}
- [(set_attr "type" "call")])
-
(define_insn "*call_pop_1"
[(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lsm"))
(match_operand:SI 1 "" ""))
(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG)
(match_operand:SI 2 "immediate_operand" "i")))]
- "!TARGET_64BIT && !TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
+ "!TARGET_64BIT && !SIBLING_CALL_P (insn)"
{
if (constant_call_address_operand (operands[0], Pmode))
return "call\t%P0";
@@ -14664,21 +14654,10 @@
}
[(set_attr "type" "call")])
-(define_insn "*call_1_esp"
- [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
- (match_operand 1 "" ""))]
- "!TARGET_64BIT && TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
-{
- if (constant_call_address_operand (operands[0], Pmode))
- return "call\t%P0";
- return "call\t%A0";
-}
- [(set_attr "type" "call")])
-
(define_insn "*call_1"
[(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lsm"))
(match_operand 1 "" ""))]
- "!TARGET_64BIT && !TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
+ "!TARGET_64BIT && !SIBLING_CALL_P (insn)"
{
if (constant_call_address_operand (operands[0], Pmode))
return "call\t%P0";
@@ -21158,8 +21137,9 @@
[(set (match_operand 0 "" "")
(call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
(match_operand:SI 2 "" "")))
- (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
- (match_operand:SI 3 "immediate_operand" "")))]
+ (set (reg:SI SP_REG)
+ (plus:SI (reg:SI SP_REG)
+ (match_operand:SI 3 "immediate_operand" "")))]
"!TARGET_64BIT"
{
if (SIBLING_CALL_P (insn))
@@ -21169,27 +21149,14 @@
}
[(set_attr "type" "callv")])
-(define_insn "*call_value_pop_1_esp"
- [(set (match_operand 0 "" "")
- (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
- (match_operand:SI 2 "" "")))
- (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
- (match_operand:SI 3 "immediate_operand" "i")))]
- "!TARGET_64BIT && TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
-{
- if (constant_call_address_operand (operands[1], Pmode))
- return "call\t%P1";
- return "call\t%A1";
-}
- [(set_attr "type" "callv")])
-
(define_insn "*call_value_pop_1"
[(set (match_operand 0 "" "")
(call (mem:QI (match_operand:SI 1 "call_insn_operand" "lsm"))
(match_operand:SI 2 "" "")))
- (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
- (match_operand:SI 3 "immediate_operand" "i")))]
- "!TARGET_64BIT && !TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
+ (set (reg:SI SP_REG)
+ (plus:SI (reg:SI SP_REG)
+ (match_operand:SI 3 "immediate_operand" "i")))]
+ "!TARGET_64BIT && !SIBLING_CALL_P (insn)"
{
if (constant_call_address_operand (operands[1], Pmode))
return "call\t%P1";
@@ -21201,8 +21168,9 @@
[(set (match_operand 0 "" "")
(call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "s,U"))
(match_operand:SI 2 "" "")))
- (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
- (match_operand:SI 3 "immediate_operand" "i,i")))]
+ (set (reg:SI SP_REG)
+ (plus:SI (reg:SI SP_REG)
+ (match_operand:SI 3 "immediate_operand" "i,i")))]
"!TARGET_64BIT && SIBLING_CALL_P (insn)"
"@
jmp\t%P1
@@ -21261,23 +21229,11 @@
}
[(set_attr "type" "callv")])
-(define_insn "*call_value_1_esp"
- [(set (match_operand 0 "" "")
- (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
- (match_operand:SI 2 "" "")))]
- "!TARGET_64BIT && TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
-{
- if (constant_call_address_operand (operands[1], Pmode))
- return "call\t%P1";
- return "call\t%A1";
-}
- [(set_attr "type" "callv")])
-
(define_insn "*call_value_1"
[(set (match_operand 0 "" "")
(call (mem:QI (match_operand:SI 1 "call_insn_operand" "lsm"))
(match_operand:SI 2 "" "")))]
- "!TARGET_64BIT && !TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
+ "!TARGET_64BIT && !SIBLING_CALL_P (insn)"
{
if (constant_call_address_operand (operands[1], Pmode))
return "call\t%P1";
diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index dee6df9..b21e895 100644
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -561,9 +561,7 @@
;; Test for a valid operand for a call instruction.
(define_predicate "call_insn_operand"
(ior (match_operand 0 "constant_call_address_operand")
- (ior (and (match_operand 0 "register_no_elim_operand")
- (ior (match_test "TARGET_CALL_ESP")
- (match_operand 0 "index_register_operand")))
+ (ior (match_operand 0 "index_register_operand")
(match_operand 0 "memory_operand"))))
;; Similarly, but for tail calls, in which we cannot allow memory references.
generated by cgit v1.1 at 2024-11-02 13:53:18 +0000