diff options
-rw-r--r-- | gcc/ChangeLog | 7 | ||||
-rw-r--r-- | gcc/config/sh/lib1funcs.asm | 2 | ||||
-rw-r--r-- | gcc/config/sh/linux.h | 4 | ||||
-rw-r--r-- | gcc/config/sh/sh.c | 6 | ||||
-rw-r--r-- | gcc/config/sh/sh.md | 14 |
5 files changed, 20 insertions, 13 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2ef4965..d4a863a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2003-01-30 Kazu Hirata <kazu@cs.umass.edu> + + * config/sh/lib1funcs.asm: Fix comment typos. + * config/sh/linux.h: Likewise. + * config/sh/sh.c: Likewise. + * config/sh/sh.md: Likewise. + 2003-01-30 Loren James Rittle <ljrittle@acm.org> * objc/Make-lang.in (objc-parse.y): Find c-parse.in in $(srcdir). diff --git a/gcc/config/sh/lib1funcs.asm b/gcc/config/sh/lib1funcs.asm index d9e6512..74e9839 100644 --- a/gcc/config/sh/lib1funcs.asm +++ b/gcc/config/sh/lib1funcs.asm @@ -2520,7 +2520,7 @@ LOCAL(ia_main_table): Its execution time is linear on the number of registers that actually have to be copied, and it is optimized for structures larger than 64 bits, as opposed to - invidivual `long long' arguments. See sh.h for details on the + individual `long long' arguments. See sh.h for details on the actual bit pattern. */ .global GLOBAL(GCC_shcompact_incoming_args) diff --git a/gcc/config/sh/linux.h b/gcc/config/sh/linux.h index 186bc9a..4fa432b 100644 --- a/gcc/config/sh/linux.h +++ b/gcc/config/sh/linux.h @@ -1,5 +1,5 @@ /* Definitions for SH running Linux-based GNU systems using ELF - Copyright (C) 1999, 2000, 2002 Free Software Foundation, Inc. + Copyright (C) 1999, 2000, 2002, 2003 Free Software Foundation, Inc. Contributed by Kazumoto Kojima <kkojima@rr.iij4u.or.jp> This file is part of GNU CC. @@ -162,7 +162,7 @@ do { \ #endif /* defined (__SH5__) */ #if defined (__SH5__) && __SH5__ != 32 -/* MD_FALLBACK_FRAME_STATE_FOR is not yet defiened for SHMEDIA. */ +/* MD_FALLBACK_FRAME_STATE_FOR is not yet defined for SHMEDIA. */ #else /* defined (__SH5__) && __SH5__ != 32 */ #if defined (__SH3E__) || defined (__SH4__) || defined (__SH5__) diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c index dadc1c9..0d83910 100644 --- a/gcc/config/sh/sh.c +++ b/gcc/config/sh/sh.c @@ -6663,7 +6663,7 @@ sh_1el_vec (v, mode) if (GET_CODE (v) != CONST_VECTOR || (GET_MODE (v) != mode && mode != VOIDmode)) return 0; - /* Determine numbers of last and of least significat elements. */ + /* Determine numbers of last and of least significant elements. */ last = XVECLEN (v, 0) - 1; least = TARGET_LITTLE_ENDIAN ? 0 : last; if (GET_CODE (XVECEXP (v, 0, least)) != CONST_INT) @@ -6878,7 +6878,7 @@ expand_df_binop (fun, operands) } /* ??? gcc does flow analysis strictly after common subexpression - elimination. As a result, common subespression elimination fails + elimination. As a result, common subexpression elimination fails when there are some intervening statements setting the same register. If we did nothing about this, this would hurt the precision switching for SH4 badly. There is some cse after reload, but it is unable to @@ -7619,7 +7619,7 @@ sh_initialize_trampoline (tramp, fnaddr, cxt) rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode); rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode); /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated, - rotated 10 right, and higer 16 bit of every 32 selected. */ + rotated 10 right, and higher 16 bit of every 32 selected. */ rtx movishori = force_reg (V2HImode, (simplify_gen_subreg (V2HImode, GEN_INT (0x4330432), SImode, 0))); diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md index 45f6610..7c4c7ae 100644 --- a/gcc/config/sh/sh.md +++ b/gcc/config/sh/sh.md @@ -227,7 +227,7 @@ ;; fpconv_media SHmedia single precision floating point conversions ;; fstore_media SHmedia floating point register store instructions ;; gettr_media SHmedia gettr instruction -;; invalidate_line_media SHmedia invaldiate_line sequence +;; invalidate_line_media SHmedia invalidate_line sequence ;; jump_media SHmedia unconditional branch instructions ;; load_media SHmedia general register load instructions ;; pt_media SHmedia pt instruction (expanded by assembler) @@ -236,7 +236,7 @@ ;; mcmp_media SHmedia multimedia compare, absolute, saturating ops ;; mac_media SHmedia mac-style fixed point operations ;; d2mpy_media SHmedia: two 32 bit integer multiplies -;; atrans SHmedia approximate transcendential functions +;; atrans SHmedia approximate transcendental functions ;; ustore_media SHmedia unaligned stores ;; nil no-op move, will be deleted. @@ -1252,7 +1252,7 @@ ; the udivsi3 libcall has the same name, we must consider all registers ; clobbered that are in the union of the registers clobbered by the ; shmedia and the shcompact implementation. Note, if the shcompact -; implemenation actually used shcompact code, we'd need to clobber +; implementation actually used shcompact code, we'd need to clobber ; also r23 and fr23. (define_insn "udivsi3_i1_media" [(set (match_operand:SI 0 "register_operand" "=z") @@ -1418,7 +1418,7 @@ ; the sdivsi3 libcall has the same name, we must consider all registers ; clobbered that are in the union of the registers clobbered by the ; shmedia and the shcompact implementation. Note, if the shcompact -; implemenation actually used shcompact code, we'd need to clobber +; implementation actually used shcompact code, we'd need to clobber ; also r22, r23 and fr23. (define_insn "divsi3_i1_media" [(set (match_operand:SI 0 "register_operand" "=z") @@ -10596,8 +10596,8 @@ "issue+load_store") ;; We don't model all pipeline stages; we model the issue ('D') stage -;; inasmuch as we allow only two instructions to issue simultanously, -;; and CO instructions prevent any simultanous issue of another instruction. +;; inasmuch as we allow only two instructions to issue simultaneously, +;; and CO instructions prevent any simultaneous issue of another instruction. ;; (This uses pipe_01 and pipe_02). ;; Double issue of EX insns is prevented by using the int unit in the EX stage. ;; Double issue of EX / BR insns is prevented by using the int unit / @@ -10610,7 +10610,7 @@ ;; (except in the cases outlined above), nor to describe the FS stage after ;; the F2 stage. -;; Other MT group intructions(1 step operations) +;; Other MT group instructions(1 step operations) ;; Group: MT ;; Latency: 1 ;; Issue Rate: 1 |