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-rw-r--r--gcc/config/i386/i386-expand.c16
-rw-r--r--gcc/config/i386/mmx.md54
-rw-r--r--gcc/testsuite/g++.target/i386/pr100637-1b.C2
-rw-r--r--gcc/testsuite/g++.target/i386/pr100637-1w.C2
-rw-r--r--gcc/testsuite/g++.target/i386/pr103861-1.C17
-rw-r--r--gcc/testsuite/gcc.target/i386/pr100637-4b.c2
-rw-r--r--gcc/testsuite/gcc.target/i386/pr103861-4.c19
7 files changed, 78 insertions, 34 deletions
diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c
index add748b..8b1266f 100644
--- a/gcc/config/i386/i386-expand.c
+++ b/gcc/config/i386/i386-expand.c
@@ -3899,7 +3899,7 @@ ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
{
op_true = force_reg (mode, op_true);
- gen = gen_mmx_pblendvb64;
+ gen = gen_mmx_pblendvb_v8qi;
if (mode != V8QImode)
d = gen_reg_rtx (V8QImode);
op_false = gen_lowpart (V8QImode, op_false);
@@ -3913,7 +3913,7 @@ ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
{
op_true = force_reg (mode, op_true);
- gen = gen_mmx_pblendvb32;
+ gen = gen_mmx_pblendvb_v4qi;
if (mode != V4QImode)
d = gen_reg_rtx (V4QImode);
op_false = gen_lowpart (V4QImode, op_false);
@@ -3921,6 +3921,14 @@ ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
cmp = gen_lowpart (V4QImode, cmp);
}
break;
+ case E_V2QImode:
+ if (TARGET_SSE4_1)
+ {
+ op_true = force_reg (mode, op_true);
+
+ gen = gen_mmx_pblendvb_v2qi;
+ }
+ break;
case E_V16QImode:
case E_V8HImode:
case E_V8HFmode:
@@ -18462,9 +18470,9 @@ expand_vec_perm_blend (struct expand_vec_perm_d *d)
vperm = force_reg (vmode, vperm);
if (GET_MODE_SIZE (vmode) == 4)
- emit_insn (gen_mmx_pblendvb32 (target, op0, op1, vperm));
+ emit_insn (gen_mmx_pblendvb_v4qi (target, op0, op1, vperm));
else if (GET_MODE_SIZE (vmode) == 8)
- emit_insn (gen_mmx_pblendvb64 (target, op0, op1, vperm));
+ emit_insn (gen_mmx_pblendvb_v8qi (target, op0, op1, vperm));
else if (GET_MODE_SIZE (vmode) == 16)
emit_insn (gen_sse4_1_pblendvb (target, op0, op1, vperm));
else
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 91d6421..fa67278 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -2580,14 +2580,14 @@
})
(define_expand "vcond<mode><mode>"
- [(set (match_operand:VI_32 0 "register_operand")
- (if_then_else:VI_32
+ [(set (match_operand:VI_16_32 0 "register_operand")
+ (if_then_else:VI_16_32
(match_operator 3 ""
- [(match_operand:VI_32 4 "register_operand")
- (match_operand:VI_32 5 "register_operand")])
- (match_operand:VI_32 1)
- (match_operand:VI_32 2)))]
- "TARGET_SSE2"
+ [(match_operand:VI_16_32 4 "register_operand")
+ (match_operand:VI_16_32 5 "register_operand")])
+ (match_operand:VI_16_32 1)
+ (match_operand:VI_16_32 2)))]
+ "TARGET_SSE4_1"
{
bool ok = ix86_expand_int_vcond (operands);
gcc_assert (ok);
@@ -2612,14 +2612,14 @@
})
(define_expand "vcondu<mode><mode>"
- [(set (match_operand:VI_32 0 "register_operand")
- (if_then_else:VI_32
+ [(set (match_operand:VI_16_32 0 "register_operand")
+ (if_then_else:VI_16_32
(match_operator 3 ""
- [(match_operand:VI_32 4 "register_operand")
- (match_operand:VI_32 5 "register_operand")])
- (match_operand:VI_32 1)
- (match_operand:VI_32 2)))]
- "TARGET_SSE2"
+ [(match_operand:VI_16_32 4 "register_operand")
+ (match_operand:VI_16_32 5 "register_operand")])
+ (match_operand:VI_16_32 1)
+ (match_operand:VI_16_32 2)))]
+ "TARGET_SSE4_1"
{
bool ok = ix86_expand_int_vcond (operands);
gcc_assert (ok);
@@ -2640,19 +2640,19 @@
})
(define_expand "vcond_mask_<mode><mode>"
- [(set (match_operand:VI_32 0 "register_operand")
- (vec_merge:VI_32
- (match_operand:VI_32 1 "register_operand")
- (match_operand:VI_32 2 "register_operand")
- (match_operand:VI_32 3 "register_operand")))]
- "TARGET_SSE2"
+ [(set (match_operand:VI_16_32 0 "register_operand")
+ (vec_merge:VI_16_32
+ (match_operand:VI_16_32 1 "register_operand")
+ (match_operand:VI_16_32 2 "register_operand")
+ (match_operand:VI_16_32 3 "register_operand")))]
+ "TARGET_SSE4_1"
{
ix86_expand_sse_movcc (operands[0], operands[3],
operands[1], operands[2]);
DONE;
})
-(define_insn "mmx_pblendvb64"
+(define_insn "mmx_pblendvb_v8qi"
[(set (match_operand:V8QI 0 "register_operand" "=Yr,*x,x")
(unspec:V8QI
[(match_operand:V8QI 1 "register_operand" "0,0,x")
@@ -2672,12 +2672,12 @@
(set_attr "btver2_decode" "vector")
(set_attr "mode" "TI")])
-(define_insn "mmx_pblendvb32"
- [(set (match_operand:V4QI 0 "register_operand" "=Yr,*x,x")
- (unspec:V4QI
- [(match_operand:V4QI 1 "register_operand" "0,0,x")
- (match_operand:V4QI 2 "register_operand" "Yr,*x,x")
- (match_operand:V4QI 3 "register_operand" "Yz,Yz,x")]
+(define_insn "mmx_pblendvb_<mode>"
+ [(set (match_operand:VI_16_32 0 "register_operand" "=Yr,*x,x")
+ (unspec:VI_16_32
+ [(match_operand:VI_16_32 1 "register_operand" "0,0,x")
+ (match_operand:VI_16_32 2 "register_operand" "Yr,*x,x")
+ (match_operand:VI_16_32 3 "register_operand" "Yz,Yz,x")]
UNSPEC_BLENDV))]
"TARGET_SSE4_1"
"@
diff --git a/gcc/testsuite/g++.target/i386/pr100637-1b.C b/gcc/testsuite/g++.target/i386/pr100637-1b.C
index 35b5df7c..d602ac0 100644
--- a/gcc/testsuite/g++.target/i386/pr100637-1b.C
+++ b/gcc/testsuite/g++.target/i386/pr100637-1b.C
@@ -1,6 +1,6 @@
/* PR target/100637 */
/* { dg-do compile } */
-/* { dg-options "-O2 -msse2" } */
+/* { dg-options "-O2 -msse4" } */
typedef unsigned char __attribute__((__vector_size__ (4))) __v4qu;
typedef char __attribute__((__vector_size__ (4))) __v4qi;
diff --git a/gcc/testsuite/g++.target/i386/pr100637-1w.C b/gcc/testsuite/g++.target/i386/pr100637-1w.C
index a3ed06f..c605645 100644
--- a/gcc/testsuite/g++.target/i386/pr100637-1w.C
+++ b/gcc/testsuite/g++.target/i386/pr100637-1w.C
@@ -1,6 +1,6 @@
/* PR target/100637 */
/* { dg-do compile } */
-/* { dg-options "-O2 -msse2" } */
+/* { dg-options "-O2 -msse4" } */
typedef unsigned short __attribute__((__vector_size__ (4))) __v2hu;
typedef short __attribute__((__vector_size__ (4))) __v2hi;
diff --git a/gcc/testsuite/g++.target/i386/pr103861-1.C b/gcc/testsuite/g++.target/i386/pr103861-1.C
new file mode 100644
index 0000000..940c939
--- /dev/null
+++ b/gcc/testsuite/g++.target/i386/pr103861-1.C
@@ -0,0 +1,17 @@
+/* PR target/103861 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse4" } */
+
+typedef unsigned char __attribute__((__vector_size__ (2))) __v2qu;
+typedef char __attribute__((__vector_size__ (2))) __v2qi;
+
+__v2qu au, bu;
+__v2qi as, bs;
+
+__v2qu uu (__v2qu a, __v2qu b) { return (a > b) ? au : bu; }
+__v2qu us (__v2qi a, __v2qi b) { return (a > b) ? au : bu; }
+__v2qi su (__v2qu a, __v2qu b) { return (a > b) ? as : bs; }
+__v2qi ss (__v2qi a, __v2qi b) { return (a > b) ? as : bs; }
+
+/* { dg-final { scan-assembler-times "pcmpeqb" 2 } } */
+/* { dg-final { scan-assembler-times "pcmpgtb" 2 } } */
diff --git a/gcc/testsuite/gcc.target/i386/pr100637-4b.c b/gcc/testsuite/gcc.target/i386/pr100637-4b.c
index 198e3dd..add4506 100644
--- a/gcc/testsuite/gcc.target/i386/pr100637-4b.c
+++ b/gcc/testsuite/gcc.target/i386/pr100637-4b.c
@@ -1,6 +1,6 @@
/* PR target/100637 */
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize -msse2" } */
+/* { dg-options "-O2 -ftree-vectorize -msse4" } */
typedef char T;
diff --git a/gcc/testsuite/gcc.target/i386/pr103861-4.c b/gcc/testsuite/gcc.target/i386/pr103861-4.c
new file mode 100644
index 0000000..54c1859
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr103861-4.c
@@ -0,0 +1,19 @@
+/* PR target/100637 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize -msse4" } */
+
+typedef char T;
+
+#define M 2
+
+extern T a[M], b[M], s1[M], s2[M], r[M];
+
+void foo (void)
+{
+ int j;
+
+ for (j = 0; j < M; j++)
+ r[j] = (a[j] < b[j]) ? s1[j] : s2[j];
+}
+
+/* { dg-final { scan-assembler "pcmpgtb" { xfail *-*-* } } } */
generated by cgit v1.1 at 2025-04-17 04:06:56 +0000