diff options
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/arc/arc.md | 22 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arc/delay-slot-limm.c | 52 |
4 files changed, 72 insertions, 11 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ff62a22..0148acc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2019-11-11 Claudiu Zissulescu <claziss@gmail.com> + * config/arc/arc.md (movsi_ne): Reorder instruction variants and + use new register constraint letters. + +2019-11-11 Claudiu Zissulescu <claziss@gmail.com> + * config/arc/arc.c (arc_legitimize_pic_address): Consider UNSPECs as well, if interesting recover the symbol and re-legitimize the pic address. diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index e3043b5..98e9623 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -3787,20 +3787,20 @@ core_3, archs4x, archs4xd, archs4xd_slow" ; cond_exec patterns (define_insn "*movsi_ne" [(cond_exec - (ne (match_operand:CC_Z 2 "cc_use_register" "Rcc, Rcc, Rcc,Rcc,Rcc") (const_int 0)) - (set (match_operand:SI 0 "dest_reg_operand" "=Rcq#q,Rcq#q,Rcq#q, w,w") - (match_operand:SI 1 "nonmemory_operand" "C_0, h, ?Cal, Lc,?Cal")))] + (ne (match_operand:CC_Z 2 "cc_use_register" "Rcc,Rcc,Rcc,Rcc,Rcc") (const_int 0)) + (set (match_operand:SI 0 "dest_reg_operand" "=q, q, r, q, r") + (match_operand:SI 1 "nonmemory_operand" "C_0, h, Lr,Cal,Cal")))] "" "@ - * current_insn_predicate = 0; return \"sub%?.ne %0,%0,%0%&\"; - * current_insn_predicate = 0; return \"mov%?.ne %0,%1\"; - * current_insn_predicate = 0; return \"mov%?.ne %0,%1\"; - mov.ne %0,%1 - mov.ne %0,%1" + * current_insn_predicate = 0; return \"sub%?.ne\\t%0,%0,%0\"; + * current_insn_predicate = 0; return \"mov%?.ne\\t%0,%1\"; + mov.ne\\t%0,%1 + * current_insn_predicate = 0; return \"mov%?.ne\\t%0,%1\"; + mov.ne\\t%0,%1" [(set_attr "type" "cmove") - (set_attr "iscompact" "true,true,true_limm,false,false") - (set_attr "length" "2,2,6,4,8") - (set_attr "cpu_facility" "*,av2,av2,*,*")]) + (set_attr "iscompact" "true,true,false,true_limm,false") + (set_attr "length" "2,2,4,6,8") + (set_attr "cpu_facility" "*,av2,*,av2,*")]) (define_insn "*movsi_cond_exec" [(cond_exec diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 06d9851..e734954 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2019-11-11 Claudiu Zissulescu <claziss@gmail.com> + * gcc.target/arc/delay-slot-limm.c: New test. + +2019-11-11 Claudiu Zissulescu <claziss@gmail.com> + * gcc.target/arc/pic-2.c: New file. 2019-11-11 Tobias Burnus <tobias@codesourcery.com> diff --git a/gcc/testsuite/gcc.target/arc/delay-slot-limm.c b/gcc/testsuite/gcc.target/arc/delay-slot-limm.c new file mode 100644 index 0000000..e5de3c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/delay-slot-limm.c @@ -0,0 +1,52 @@ +/* We have encountered an issue that a "mov_s.ne" instruction * + * with an immediate value was put in the delay slot of a * + * branch: * + * * + * bne.d @.L1 # 33 [c=20 l=4] *branch_insn * + * mov_s.ne r0,7 # 35 [c=0 l=6] *movsi_ne/2 * + * * + * This is not sanctioned and must not happen. The test below * + * is a reduced version of the source code leading to the * + * problem. */ + +/* { dg-do compile } */ +/* { dg-skip-if "" { ! { clmcpu } } } */ +/* { dg-options "-mcpu=archs -Og" } */ +typedef struct +{ + struct + { + int length; + } table; +} room; + +struct house +{ + room *r; +}; + +int glob; + +_Bool bar(); + +int func(struct house *h, int i, int whatever) +{ + for (;;) + { + _Bool a; + if (h && h->r[i].table.length == glob) + { + if (whatever) + { + a = bar(); + if (__builtin_expect(!a, 0)) + return 7; + } + break; + } + } + return 0; +} + +/* no 'mov_s.ne r,limm' in a delay slot */ +/* { dg-final { scan-assembler-not "bne.d\.*\n\\s\+mov_s.ne\\s+r\[0-9\]+,7" } } */ |