diff options
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/rs6000/predicates.md | 11 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 12 |
3 files changed, 13 insertions, 17 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7e8425c..9fba87f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2005-06-13 David Edelsohn <edelsohn@gnu.org> + + Revert scc_operand patch. + * config/rs6000/predicates.md (scc_operand): Delete. + * config/rs6000/rs6000.md (scc_operand): Change to scc_eq_operand. + 2005-06-13 Jakub Jelinek <jakub@redhat.com> * trans-expr.c (gfc_conv_function_call): Return int instead of @@ -164,6 +170,7 @@ tag if VAR has just one in its may_aliases list. 2005-06-10 Fariborz Jahanian <fjahanian@apple.com> + * rs6000/predicates.md (scc_operand): New. * rs6000/rs6000.md : Use scc_operand for eq:SI compares. diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index cba7337..664c7f0 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -132,17 +132,6 @@ (ior (match_code "const_int") (match_operand 0 "gpc_reg_operand"))) -;; Return 1 if op is an integer meeting one of 'I','J','O','L'(TARGET_32BIT) -;; or 'J'(TARGET_64BIT) constraints or if it is a non-special register. -(define_predicate "scc_operand" - (if_then_else (match_code "const_int") - (match_test "CONST_OK_FOR_LETTER_P (INTVAL (op), 'I') - || CONST_OK_FOR_LETTER_P (INTVAL (op), 'K') - || CONST_OK_FOR_LETTER_P (INTVAL (op), 'O') - || CONST_OK_FOR_LETTER_P (INTVAL (op), - (TARGET_32BIT ? 'L' : 'J'))") - (match_operand 0 "gpc_reg_operand"))) - ;; Return 1 if op is a constant integer valid for addition ;; or non-special register. (define_predicate "reg_or_add_cint_operand" diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 8e4fd35..eee2410 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -11246,7 +11246,7 @@ (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r") (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") - (match_operand:SI 2 "scc_operand" "r,O,K,L,I")) + (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I")) (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))] "TARGET_32BIT" "@ @@ -11263,7 +11263,7 @@ (compare:CC (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") - (match_operand:SI 2 "scc_operand" "r,O,K,L,I,r,O,K,L,I")) + (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I")) (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) (const_int 0))) (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] @@ -11287,7 +11287,7 @@ (compare:CC (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "scc_operand" "")) + (match_operand:SI 2 "scc_eq_operand" "")) (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (clobber (match_scratch:SI 4 ""))] @@ -11306,7 +11306,7 @@ (compare:CC (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") - (match_operand:SI 2 "scc_operand" "r,O,K,L,I,r,O,K,L,I")) + (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I")) (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r") @@ -11331,7 +11331,7 @@ (compare:CC (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "scc_operand" "")) + (match_operand:SI 2 "scc_eq_operand" "")) (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") @@ -11347,7 +11347,7 @@ (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") - (match_operand:SI 2 "scc_operand" "r,O,K,L,I"))))] + (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))))] "TARGET_32BIT" "@ xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |