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-rw-r--r--gcc/ChangeLog22
-rw-r--r--gcc/config/sparc/cypress.md2
-rw-r--r--gcc/config/sparc/freebsd.h4
-rw-r--r--gcc/config/sparc/gmon-sol2.c4
-rw-r--r--gcc/config/sparc/hypersparc.md4
-rw-r--r--gcc/config/sparc/lb1spc.asm8
-rw-r--r--gcc/config/sparc/lb1spl.asm2
-rw-r--r--gcc/config/sparc/linux.h2
-rw-r--r--gcc/config/sparc/linux64.h6
-rw-r--r--gcc/config/sparc/lynx.h2
-rw-r--r--gcc/config/sparc/sol2.h2
-rw-r--r--gcc/config/sparc/sparc-modes.def2
-rw-r--r--gcc/config/sparc/sparc.c4
-rw-r--r--gcc/config/sparc/sparc.h20
-rw-r--r--gcc/config/sparc/sparc.md12
-rw-r--r--gcc/config/sparc/sparclet.md4
-rw-r--r--gcc/config/sparc/supersparc.md4
-rw-r--r--gcc/config/sparc/sysv4.h18
-rw-r--r--gcc/config/sparc/vxsim.h2
-rw-r--r--gcc/config/sparc/vxsparc64.h2
20 files changed, 74 insertions, 52 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5e496f8..bf3c533 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,25 @@
+2002-09-15 Kazu Hirata <kazu@cs.umass.edu>
+
+ * config/sparc/cypress.md: Replace Sparc with SPARC.
+ * config/sparc/freebsd.h: Likewise.
+ * config/sparc/gmon-sol2.c: Likewise.
+ * config/sparc/hypersparc.md: Likewise.
+ * config/sparc/lb1spc.asm: Likewise.
+ * config/sparc/lb1spl.asm: Likewise.
+ * config/sparc/linux.h: Likewise.
+ * config/sparc/linux64.h: Likewise.
+ * config/sparc/lynx.h: Likewise.
+ * config/sparc/sol2.h: Likewise.
+ * config/sparc/sparc-modes.def: Likewise.
+ * config/sparc/sparc.c: Likewise.
+ * config/sparc/sparc.h: Likewise.
+ * config/sparc/sparc.md: Likewise.
+ * config/sparc/sparclet.md: Likewise.
+ * config/sparc/supersparc.md: Likewise.
+ * config/sparc/sysv4.h: Likewise.
+ * config/sparc/vxsim.h: Likewise.
+ * config/sparc/vxsparc64.h: Likewise.
+
2002-09-14 Marek Michalkiewicz <marekm@amelek.gda.pl>
* config/avr/avr.c (output.h): Move after inclusion of tree.h.
diff --git a/gcc/config/sparc/cypress.md b/gcc/config/sparc/cypress.md
index f871b1e..e9bff6d 100644
--- a/gcc/config/sparc/cypress.md
+++ b/gcc/config/sparc/cypress.md
@@ -1,4 +1,4 @@
-;; Scheduling description for Sparc Cypress.
+;; Scheduling description for SPARC Cypress.
;; Copyright (C) 2002 Free Software Foundation, Inc.
;;
;; This file is part of GNU CC.
diff --git a/gcc/config/sparc/freebsd.h b/gcc/config/sparc/freebsd.h
index e966090..8149923 100644
--- a/gcc/config/sparc/freebsd.h
+++ b/gcc/config/sparc/freebsd.h
@@ -1,4 +1,4 @@
-/* Definitions for Sun Sparc64 running FreeBSD using the ELF format
+/* Definitions for Sun SPARC64 running FreeBSD using the ELF format
Copyright (C) 2001, 2002 Free Software Foundation, Inc.
Contributed by David E. O'Brien <obrien@FreeBSD.org> and BSDi.
@@ -54,7 +54,7 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
#define WCHAR_TYPE_SIZE 32
/* Define for support of TFmode long double.
- Sparc ABI says that long double is 4 words. */
+ SPARC ABI says that long double is 4 words. */
#undef LONG_DOUBLE_TYPE_SIZE
#define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64)
diff --git a/gcc/config/sparc/gmon-sol2.c b/gcc/config/sparc/gmon-sol2.c
index bcb0c06..c577666 100644
--- a/gcc/config/sparc/gmon-sol2.c
+++ b/gcc/config/sparc/gmon-sol2.c
@@ -28,7 +28,7 @@
* SUCH DAMAGE.
*/
-/* Mangled into a form that works on Sparc Solaris 2 by Mark Eichin
+/* Mangled into a form that works on SPARC Solaris 2 by Mark Eichin
* for Cygnus Support, July 1992.
*/
@@ -232,7 +232,7 @@ _mcleanup()
}
/*
- * The Sparc stack frame is only held together by the frame pointers
+ * The SPARC stack frame is only held together by the frame pointers
* in the register windows. According to the SVR4 SPARC ABI
* Supplement, Low Level System Information/Operating System
* Interface/Software Trap Types, a type 3 trap will flush all of the
diff --git a/gcc/config/sparc/hypersparc.md b/gcc/config/sparc/hypersparc.md
index 741f163..d80e51e 100644
--- a/gcc/config/sparc/hypersparc.md
+++ b/gcc/config/sparc/hypersparc.md
@@ -1,4 +1,4 @@
-;; Scheduling description for HyperSparc.
+;; Scheduling description for HyperSPARC.
;; Copyright (C) 2002 Free Software Foundation, Inc.
;;
;; This file is part of GNU CC.
@@ -18,7 +18,7 @@
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.
-;; The HyperSparc is a dual-issue processor. It is not all that fancy.
+;; The HyperSPARC is a dual-issue processor. It is not all that fancy.
;; ??? There are some things not modelled. For example, sethi+or
;; ??? coming right after each other are specifically identified and
diff --git a/gcc/config/sparc/lb1spc.asm b/gcc/config/sparc/lb1spc.asm
index b31f82c..b60bd57 100644
--- a/gcc/config/sparc/lb1spc.asm
+++ b/gcc/config/sparc/lb1spc.asm
@@ -1,7 +1,7 @@
/* This is an assembly language implementation of mulsi3, divsi3, and modsi3
for the sparc processor.
- These routines are derived from the Sparc Architecture Manual, version 8,
+ These routines are derived from the SPARC Architecture Manual, version 8,
slightly edited to match the desired calling convention, and also to
optimize them for our purposes. */
@@ -81,7 +81,7 @@ mul_shortway:
#ifdef L_divsi3
/*
- * Division and remainder, from Appendix E of the Sparc Version 8
+ * Division and remainder, from Appendix E of the SPARC Version 8
* Architecture Manual, with fixes from Gordon Irlam.
*/
@@ -197,7 +197,7 @@ ready_to_divide:
nop
be do_single_div
nop
- /* NB: these are commented out in the V8-Sparc manual as well */
+ /* NB: these are commented out in the V8-SPARC manual as well */
/* (I do not understand this) */
! %o5 > %o3: went too far: back up 1 step
! srl %o5, 1, %o5
@@ -544,7 +544,7 @@ divide:
nop
be do_single_div
nop
- /* NB: these are commented out in the V8-Sparc manual as well */
+ /* NB: these are commented out in the V8-SPARC manual as well */
/* (I do not understand this) */
! %o5 > %o3: went too far: back up 1 step
! srl %o5, 1, %o5
diff --git a/gcc/config/sparc/lb1spl.asm b/gcc/config/sparc/lb1spl.asm
index 9dda675..973401f 100644
--- a/gcc/config/sparc/lb1spl.asm
+++ b/gcc/config/sparc/lb1spl.asm
@@ -1,7 +1,7 @@
/* This is an assembly language implementation of mulsi3, divsi3, and modsi3
for the sparclite processor.
- These routines are all from the Sparclite User's Guide, slightly edited
+ These routines are all from the SPARClite User's Guide, slightly edited
to match the desired calling convention, and also to optimize them. */
#ifdef L_udivsi3
diff --git a/gcc/config/sparc/linux.h b/gcc/config/sparc/linux.h
index dc4b50a..dcf79e8 100644
--- a/gcc/config/sparc/linux.h
+++ b/gcc/config/sparc/linux.h
@@ -231,7 +231,7 @@ do { \
/* Define for support of TFmode long double.
- Sparc ABI says that long double is 4 words. */
+ SPARC ABI says that long double is 4 words. */
#define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64)
/* Constant which presents upper bound of the above value. */
diff --git a/gcc/config/sparc/linux64.h b/gcc/config/sparc/linux64.h
index a70cd24..51eca16 100644
--- a/gcc/config/sparc/linux64.h
+++ b/gcc/config/sparc/linux64.h
@@ -149,7 +149,7 @@ ENDFILE_SPEC_COMMON
#define WCHAR_TYPE_SIZE 32
/* Define for support of TFmode long double.
- Sparc ABI says that long double is 4 words. */
+ SPARC ABI says that long double is 4 words. */
#undef LONG_DOUBLE_TYPE_SIZE
#define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64)
@@ -378,7 +378,7 @@ do { \
/* Handle multilib correctly. */
#if defined(__arch64__)
-/* 64-bit Sparc version */
+/* 64-bit SPARC version */
#define MD_FALLBACK_FRAME_STATE_FOR(CONTEXT, FS, SUCCESS) \
do { \
unsigned int *pc_ = (CONTEXT)->ra; \
@@ -429,7 +429,7 @@ do { \
goto SUCCESS; \
} while (0)
#else
-/* 32-bit Sparc version */
+/* 32-bit SPARC version */
#define MD_FALLBACK_FRAME_STATE_FOR(CONTEXT, FS, SUCCESS) \
do { \
unsigned int *pc_ = (CONTEXT)->ra; \
diff --git a/gcc/config/sparc/lynx.h b/gcc/config/sparc/lynx.h
index db72a92..805f65f 100644
--- a/gcc/config/sparc/lynx.h
+++ b/gcc/config/sparc/lynx.h
@@ -38,7 +38,7 @@ Boston, MA 02111-1307, USA. */
#undef LINK_SPEC
-/* Sparc version of libc.a has references to libm.a (printf calls pow for
+/* SPARC version of libc.a has references to libm.a (printf calls pow for
instance), so we must always link both. */
#undef LIB_SPEC
diff --git a/gcc/config/sparc/sol2.h b/gcc/config/sparc/sol2.h
index e343e3e..3026e40 100644
--- a/gcc/config/sparc/sol2.h
+++ b/gcc/config/sparc/sol2.h
@@ -112,7 +112,7 @@ Boston, MA 02111-1307, USA. */
/* ??? This does not work in SunOS 4.x, so it is not enabled in sparc.h.
Instead, it is enabled here, because it does work under Solaris. */
/* Define for support of TFmode long double.
- Sparc ABI says that long double is 4 words. */
+ SPARC ABI says that long double is 4 words. */
#define LONG_DOUBLE_TYPE_SIZE 128
/* But indicate that it isn't supported by the hardware. */
diff --git a/gcc/config/sparc/sparc-modes.def b/gcc/config/sparc/sparc-modes.def
index e301755..3ebf9c8 100644
--- a/gcc/config/sparc/sparc-modes.def
+++ b/gcc/config/sparc/sparc-modes.def
@@ -23,7 +23,7 @@ Boston, MA 02111-1307, USA. */
/* Add any extra modes needed to represent the condition code.
- On the Sparc, we have a "no-overflow" mode which is used when an add or
+ On the SPARC, we have a "no-overflow" mode which is used when an add or
subtract insn is used to set the condition code. Different branches are
used in this case for some operations.
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 37061be..0730ffd 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -1410,7 +1410,7 @@ sparc_emit_set_const32 (op0, op1)
}
-/* Sparc-v9 code-model support. */
+/* SPARC-v9 code-model support. */
void
sparc_emit_set_symbolic_const64 (op0, op1, temp1)
rtx op0;
@@ -4757,7 +4757,7 @@ function_arg_record_value_2 (type, startbitpos, parms)
}
/* Used by function_arg and function_value to implement the complex
- Sparc64 structure calling conventions. */
+ SPARC64 structure calling conventions. */
static rtx
function_arg_record_value (type, mode, slotno, named, regbase)
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index e14c4f2..d294a07 100644
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -434,7 +434,7 @@ extern int target_flags;
#define MASK_FLAT 0x200
#define TARGET_FLAT (target_flags & MASK_FLAT)
-/* Nonzero means use the registers that the Sparc ABI reserves for
+/* Nonzero means use the registers that the SPARC ABI reserves for
application software. This must be the default to coincide with the
setting in FIXED_REGISTERS. */
#define MASK_APP_REGS 0x400
@@ -560,15 +560,15 @@ extern int target_flags;
{"cypress", 0, \
N_("Optimize for Cypress processors") }, \
{"sparclite", 0, \
- N_("Optimize for SparcLite processors") }, \
+ N_("Optimize for SPARCLite processors") }, \
{"f930", 0, \
N_("Optimize for F930 processors") }, \
{"f934", 0, \
N_("Optimize for F934 processors") }, \
{"v8", 0, \
- N_("Use V8 Sparc ISA") }, \
+ N_("Use V8 SPARC ISA") }, \
{"supersparc", 0, \
- N_("Optimize for SuperSparc processors") }, \
+ N_("Optimize for SuperSPARC processors") }, \
/* End of deprecated options. */ \
{"ptr64", MASK_PTR64, \
N_("Pointers are 64-bit") }, \
@@ -634,7 +634,7 @@ extern enum processor_type sparc_cpu;
{ "tune=", &sparc_select[2].string, \
N_("Schedule code for given CPU") }, \
{ "cmodel=", &sparc_cmodel_string, \
- N_("Use given Sparc code model") }, \
+ N_("Use given SPARC code model") }, \
SUBTARGET_OPTIONS \
}
@@ -700,7 +700,7 @@ extern struct sparc_cpu_select sparc_select[];
/* ??? This does not work in SunOS 4.x, so it is not enabled here.
Instead, it is enabled in sol2.h, because it does work under Solaris. */
/* Define for support of TFmode long double.
- Sparc ABI says that long double is 4 words. */
+ SPARC ABI says that long double is 4 words. */
#define LONG_DOUBLE_TYPE_SIZE 128
#endif
@@ -1118,7 +1118,7 @@ extern int sparc_mode_class[];
#define DEFAULT_PCC_STRUCT_RETURN -1
-/* Sparc ABI says that quad-precision floats and all structures are returned
+/* SPARC ABI says that quad-precision floats and all structures are returned
in memory.
For v9: unions <= 32 bytes in size are returned in int regs,
structures up to 32 bytes are returned in int and fp regs. */
@@ -1817,7 +1817,7 @@ extern GTY(()) rtx sparc_compare_op1;
/* Generate the special assembly code needed to tell the assembler whatever
it might need to know about the return value of a function.
- For Sparc assemblers, we need to output a .proc pseudo-op which conveys
+ For SPARC assemblers, we need to output a .proc pseudo-op which conveys
information to the assembler relating to peephole optimization (done in
the assembler). */
@@ -2373,7 +2373,7 @@ do { \
operand. If we find one, push the reload and jump to WIN. This
macro is used in only one place: `find_reloads_address' in reload.c.
- For Sparc 32, we wish to handle addresses by splitting them into
+ For SPARC 32, we wish to handle addresses by splitting them into
HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
This cuts the number of extra insns by one.
@@ -2494,7 +2494,7 @@ do { \
#define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y))
/* Return non-zero if MODE implies a floating point inequality can be
- reversed. For Sparc this is always true because we have a full
+ reversed. For SPARC this is always true because we have a full
compliment of ordered and unordered comparisons, but until generic
code knows how to reverse it correctly we keep the old definition. */
#define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode)
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index a7318c9..b439413 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -1602,7 +1602,7 @@
[(set_attr "type" "branch")
(set_attr "branch_type" "fcc")])
-;; Sparc V9-specific jump insns. None of these are guaranteed to be
+;; SPARC V9-specific jump insns. None of these are guaranteed to be
;; in the architecture.
;; There are no 32 bit brreg insns.
@@ -2202,7 +2202,7 @@
"TARGET_ARCH64 && flag_pic"
"or\t%1, %%lo(%a3-(%a2-.)), %0")
-;; Sparc-v9 code model support insns. See sparc_emit_set_symbolic_const64
+;; SPARC-v9 code model support insns. See sparc_emit_set_symbolic_const64
;; in sparc.c to see what is going on here... PIC stuff comes first.
(define_insn "movdi_lo_sum_pic"
@@ -3459,7 +3459,7 @@
DONE;
})
-;; Sparc V9 conditional move instructions.
+;; SPARC V9 conditional move instructions.
;; We can handle larger constants here for some flavors, but for now we keep
;; it simple and only allow those constants supported by all flavours.
@@ -7216,14 +7216,14 @@
[(set_attr "type" "shift")])
;; Unconditional and other jump instructions
-;; On the Sparc, by setting the annul bit on an unconditional branch, the
+;; On the SPARC, by setting the annul bit on an unconditional branch, the
;; following insn is never executed. This saves us a nop. Dbx does not
;; handle such branches though, so we only use them when optimizing.
(define_insn "jump"
[(set (pc) (label_ref (match_operand 0 "" "")))]
""
{
- /* TurboSparc is reported to have problems with
+ /* TurboSPARC is reported to have problems with
with
foo: b,a foo
i.e. an empty loop with the annul bit set. The workaround is to use
@@ -7909,7 +7909,7 @@
;; ??? This should be a define expand, so that the extra instruction have
;; a chance of being optimized away.
-;; Disabled because none of the UltraSparcs implement popc. The HAL R1
+;; Disabled because none of the UltraSPARCs implement popc. The HAL R1
;; does, but no one uses that and we don't have a switch for it.
;
;(define_insn "ffsdi2"
diff --git a/gcc/config/sparc/sparclet.md b/gcc/config/sparc/sparclet.md
index 805bd29..080090c 100644
--- a/gcc/config/sparc/sparclet.md
+++ b/gcc/config/sparc/sparclet.md
@@ -1,4 +1,4 @@
-;; Scheduling description for Sparclet.
+;; Scheduling description for SPARClet.
;; Copyright (C) 2002 Free Software Foundation, Inc.
;;
;; This file is part of GNU CC.
@@ -18,7 +18,7 @@
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.
-;; The Sparclet is a single-issue processor.
+;; The SPARClet is a single-issue processor.
(define_automaton "sparclet")
diff --git a/gcc/config/sparc/supersparc.md b/gcc/config/sparc/supersparc.md
index 21eadf4..ea32886 100644
--- a/gcc/config/sparc/supersparc.md
+++ b/gcc/config/sparc/supersparc.md
@@ -1,4 +1,4 @@
-;; Scheduling description for SuperSparc.
+;; Scheduling description for SuperSPARC.
;; Copyright (C) 2002 Free Software Foundation, Inc.
;;
;; This file is part of GNU CC.
@@ -18,7 +18,7 @@
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.
-;; The SuperSparc is a tri-issue, which was considered quite parallel
+;; The SuperSPARC is a tri-issue, which was considered quite parallel
;; at the time it was released. Much like UltraSPARC-I and UltraSPARC-II
;; there are two integer units but only one of them may take shifts.
;;
diff --git a/gcc/config/sparc/sysv4.h b/gcc/config/sparc/sysv4.h
index 666ee62..f304d6b 100644
--- a/gcc/config/sparc/sysv4.h
+++ b/gcc/config/sparc/sysv4.h
@@ -1,4 +1,4 @@
-/* Target definitions for GNU compiler for Sparc running System V.4
+/* Target definitions for GNU compiler for SPARC running System V.4
Copyright (C) 1991, 1992, 1995, 1996, 1997, 1998, 2000, 2002
Free Software Foundation, Inc.
Contributed by Ron Guilmette (rfg@monkeys.com).
@@ -36,7 +36,7 @@ Boston, MA 02111-1307, USA. */
/* Undefined some symbols which are defined in "svr4.h" but which are
appropriate only for typical svr4 systems, but not for the specific
- case of svr4 running on a Sparc. */
+ case of svr4 running on a SPARC. */
#undef INIT_SECTION_ASM_OP
#undef FINI_SECTION_ASM_OP
@@ -49,7 +49,7 @@ Boston, MA 02111-1307, USA. */
#undef SET_ASM_OP /* Has no equivalent. See ASM_OUTPUT_DEF below. */
/* Provide a set of pre-definitions and pre-assertions appropriate for
- the Sparc running svr4. __svr4__ is our extension. */
+ the SPARC running svr4. __svr4__ is our extension. */
#undef CPP_PREDEFINES
#define CPP_PREDEFINES \
@@ -68,10 +68,10 @@ Boston, MA 02111-1307, USA. */
"%{v:-V} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*} \
%{fpic:-K PIC} %{fPIC:-K PIC} %(asm_cpu)"
-/* Define the names of various pseudo-op used by the Sparc/svr4 assembler.
+/* Define the names of various pseudo-op used by the SPARC/svr4 assembler.
Note that many of these are different from the typical pseudo-ops used
by most svr4 assemblers. That is probably due to a (misguided?) attempt
- to keep the Sparc/svr4 assembler somewhat compatible with the Sparc/SunOS
+ to keep the SPARC/svr4 assembler somewhat compatible with the SPARC/SunOS
assembler. */
#define STRING_ASM_OP "\t.asciz\t"
@@ -81,12 +81,12 @@ Boston, MA 02111-1307, USA. */
#define POPSECTION_ASM_OP "\t.popsection"
/* This is the format used to print the second operand of a .type pseudo-op
- for the Sparc/svr4 assembler. */
+ for the SPARC/svr4 assembler. */
#define TYPE_OPERAND_FMT "#%s"
/* This is the format used to print a .pushsection pseudo-op (and its operand)
- for the Sparc/svr4 assembler. */
+ for the SPARC/svr4 assembler. */
#define PUSHSECTION_FORMAT "%s\"%s\"\n"
@@ -108,9 +108,9 @@ do { ASM_OUTPUT_ALIGN ((FILE), Pmode == SImode ? 2 : 3); \
fprintf (FILE, "\n"); \
} while (0)
-/* Define how the Sparc registers should be numbered for Dwarf output.
+/* Define how the SPARC registers should be numbered for Dwarf output.
The numbering provided here should be compatible with the native
- svr4 SDB debugger in the Sparc/svr4 reference port. The numbering
+ svr4 SDB debugger in the SPARC/svr4 reference port. The numbering
is as follows:
Assembly name gcc internal regno Dwarf regno
diff --git a/gcc/config/sparc/vxsim.h b/gcc/config/sparc/vxsim.h
index 09e1f16..c9c3569 100644
--- a/gcc/config/sparc/vxsim.h
+++ b/gcc/config/sparc/vxsim.h
@@ -132,5 +132,5 @@ do { \
/* ??? This does not work in SunOS 4.x, so it is not enabled in sparc.h.
Instead, it is enabled here, because it does work under Solaris. */
/* Define for support of TFmode long double.
- Sparc ABI says that long double is 4 words. */
+ SPARC ABI says that long double is 4 words. */
#define LONG_DOUBLE_TYPE_SIZE 64
diff --git a/gcc/config/sparc/vxsparc64.h b/gcc/config/sparc/vxsparc64.h
index 358f2c0..d37bd54 100644
--- a/gcc/config/sparc/vxsparc64.h
+++ b/gcc/config/sparc/vxsparc64.h
@@ -1,5 +1,5 @@
/* Definitions of target machine for GNU compiler.
- 64-bit VxWorks Sparc version.
+ 64-bit VxWorks SPARC version.
Copyright (C) 2001 Free Software Foundation, Inc.
This file is part of GNU CC.
generated by cgit v1.1 at 2024-11-06 11:23:17 +0000