aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--gcc/ChangeLog8
-rw-r--r--gcc/config/arc/arc.c16
-rw-r--r--gcc/config/arc/arc.md13
-rw-r--r--gcc/testsuite/ChangeLog6
-rw-r--r--gcc/testsuite/gcc.target/arc/or-cnst-size2.c12
5 files changed, 47 insertions, 8 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c0eca80..1ff3d4b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,13 @@
2019-11-06 Claudiu Zissulescu <claziss@synopsys.com>
+ * config/arc/arc.c (arc_split_ior): Add asserts.
+ (arc_split_mov_const): Likewise.
+ (arc_check_ior_const): Do not match known short immediate values.
+ * config/arc/arc.md (movsi): Don't split predicated instructions
+ (iorsi): Likewise.
+
+2019-11-06 Claudiu Zissulescu <claziss@synopsys.com>
+
* config/arc/arc.opt (mea): Update help string.
* doc/invoke.texi(ARC): Update mea option info.
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 138c84e..e8f4133 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -11495,8 +11495,10 @@ arc_split_ior (rtx *operands)
emit_insn (gen_rtx_SET (operands[0],
gen_rtx_IOR (SImode, op1, GEN_INT (maskx))));
break;
- default:
+ case 0:
break;
+ default:
+ gcc_unreachable ();
}
}
@@ -11506,6 +11508,10 @@ bool
arc_check_ior_const (HOST_WIDE_INT ival)
{
unsigned int mask = (unsigned int) (ival & 0xffffffff);
+
+ if (UNSIGNED_INT6 (ival)
+ || IS_POWEROF2_P (mask))
+ return false;
if (__builtin_popcount (mask) <= 3)
return true;
if (__builtin_popcount (mask & ~0x3f) <= 1)
@@ -11527,9 +11533,6 @@ arc_split_mov_const (rtx *operands)
gcc_assert (CONST_INT_P (operands[1]));
ival = INTVAL (operands[1]) & 0xffffffff;
- if (SIGNED_INT12 (ival))
- return false;
-
/* 1. Check if we can just rotate limm by 8 but using ROR8. */
if (TARGET_BARREL_SHIFTER && TARGET_V2
&& ((ival & ~0x3f000000) == 0))
@@ -11596,7 +11599,7 @@ arc_split_mov_const (rtx *operands)
return true;
}
- return false;
+ gcc_unreachable ();
}
/* Helper to check Cax constraint. */
@@ -11606,6 +11609,9 @@ arc_check_mov_const (HOST_WIDE_INT ival)
{
ival = ival & 0xffffffff;
+ if (SIGNED_INT12 (ival))
+ return false;
+
if ((ival & ~0x8000001f) == 0)
return true;
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 67932c4..e3043b5 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -816,8 +816,11 @@ core_3, archs4x, archs4xd, archs4xd_slow"
st%U0%V0\\t%1,%0 ;26
st%U0%V0\\t%1,%0 ;37
st%U0%V0\\t%1,%0 ;28"
- "reload_completed && satisfies_constraint_Cax (operands[1])
- && register_operand (operands[0], SImode)"
+ "reload_completed
+ && GET_CODE (PATTERN (insn)) != COND_EXEC
+ && register_operand (operands[0], SImode)
+ && IN_RANGE (REGNO (operands[0]) ^ 4, 4, 11)
+ && satisfies_constraint_Cax (operands[1])"
[(const_int 0)]
"
arc_split_mov_const (operands);
@@ -3370,7 +3373,11 @@ core_3, archs4x, archs4xd, archs4xd_slow"
#
or%?\\t%0,%1,%2
or%?\\t%0,%1,%2"
- "reload_completed && satisfies_constraint_C0x (operands[2])"
+ "reload_completed
+ && GET_CODE (PATTERN (insn)) != COND_EXEC
+ && register_operand (operands[0], SImode)
+ && IN_RANGE (REGNO (operands[0]) ^ 4, 4, 11)
+ && satisfies_constraint_C0x (operands[2])"
[(const_int 0)]
"
arc_split_ior (operands);
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 2abf6f0..ca76559 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2019-11-06 Claudiu Zissulescu <claziss@synopsys.com>
+ Sahahb Vahedi <shahab@synopsys.com>
+ Cupertino Miranda <cmiranda@synopsys.com
+
+ * gcc.target/arc/or-cnst-size2.c: New test.
+
2019-11-06 Richard Sandiford <richard.sandiford@arm.com>
* gcc.dg/vect/slp-9.c: Use scan-tree-dump rather than
diff --git a/gcc/testsuite/gcc.target/arc/or-cnst-size2.c b/gcc/testsuite/gcc.target/arc/or-cnst-size2.c
new file mode 100644
index 0000000..33af97b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arc/or-cnst-size2.c
@@ -0,0 +1,12 @@
+/* Check if we optimize the immediate of a predicated instruction. */
+/* { dg-options "-Os -fif-conversion -fif-conversion2" } */
+
+int a;
+int foo (void)
+{
+ if ((a & 60) == 0)
+ return a | 64;
+}
+
+/* { dg-final { scan-assembler "tst" } } */
+/* { dg-final { scan-assembler "bset.eq" } } */