diff options
-rw-r--r-- | gcc/ChangeLog | 16 | ||||
-rw-r--r-- | gcc/config/aarch64/aarch64.md | 50 | ||||
-rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/vfp-1.c | 8 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/vmov_n_1.c | 8 |
5 files changed, 54 insertions, 33 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 879fdbb..553c21e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,19 @@ +2018-05-14 Wilco Dijkstra <wdijkstr@arm.com> + + * config/aarch64/aarch64.md (mov<mode>): Remove '*' in alternatives. + (movsi_aarch64): Likewise. + (load_pairsi): Likewise. + (load_pairdi): Likewise. + (store_pairsi): Likewise. + (store_pairdi): Likewise. + (load_pairsf): Likewise. + (load_pairdf): Likewise. + (store_pairsf): Likewise. + (store_pairdf): Likewise. + (zero_extend): Likewise. + (trunc): Swap alternatives. + (fcvt_target): Add '?' to prefer w over r. + 2018-05-14 Jakub Jelinek <jakub@redhat.com> PR target/85756 diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 32a0e1f..68ea718 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -928,8 +928,8 @@ ) (define_insn "*mov<mode>_aarch64" - [(set (match_operand:SHORT 0 "nonimmediate_operand" "=r,r, *w,r ,r,*w, m, m, r,*w,*w") - (match_operand:SHORT 1 "aarch64_mov_operand" " r,M,D<hq>,Usv,m, m,rZ,*w,*w, r,*w"))] + [(set (match_operand:SHORT 0 "nonimmediate_operand" "=r,r, w,r ,r,w, m,m,r,w,w") + (match_operand:SHORT 1 "aarch64_mov_operand" " r,M,D<hq>,Usv,m,m,rZ,w,w,r,w"))] "(register_operand (operands[0], <MODE>mode) || aarch64_reg_or_zero (operands[1], <MODE>mode))" { @@ -995,7 +995,7 @@ (define_insn_and_split "*movsi_aarch64" [(set (match_operand:SI 0 "nonimmediate_operand" "=r,k,r,r,r,r, r,w, m, m, r, r, w,r,w, w") - (match_operand:SI 1 "aarch64_mov_operand" " r,r,k,M,n,Usv,m,m,rZ,*w,Usa,Ush,rZ,w,w,Ds"))] + (match_operand:SI 1 "aarch64_mov_operand" " r,r,k,M,n,Usv,m,m,rZ,w,Usa,Ush,rZ,w,w,Ds"))] "(register_operand (operands[0], SImode) || aarch64_reg_or_zero (operands[1], SImode))" "@ @@ -1302,9 +1302,9 @@ ;; Operands 1 and 3 are tied together by the final condition; so we allow ;; fairly lax checking on the second memory operation. (define_insn "load_pairsi" - [(set (match_operand:SI 0 "register_operand" "=r,*w") + [(set (match_operand:SI 0 "register_operand" "=r,w") (match_operand:SI 1 "aarch64_mem_pair_operand" "Ump,Ump")) - (set (match_operand:SI 2 "register_operand" "=r,*w") + (set (match_operand:SI 2 "register_operand" "=r,w") (match_operand:SI 3 "memory_operand" "m,m"))] "rtx_equal_p (XEXP (operands[3], 0), plus_constant (Pmode, @@ -1318,9 +1318,9 @@ ) (define_insn "load_pairdi" - [(set (match_operand:DI 0 "register_operand" "=r,*w") + [(set (match_operand:DI 0 "register_operand" "=r,w") (match_operand:DI 1 "aarch64_mem_pair_operand" "Ump,Ump")) - (set (match_operand:DI 2 "register_operand" "=r,*w") + (set (match_operand:DI 2 "register_operand" "=r,w") (match_operand:DI 3 "memory_operand" "m,m"))] "rtx_equal_p (XEXP (operands[3], 0), plus_constant (Pmode, @@ -1338,9 +1338,9 @@ ;; fairly lax checking on the second memory operation. (define_insn "store_pairsi" [(set (match_operand:SI 0 "aarch64_mem_pair_operand" "=Ump,Ump") - (match_operand:SI 1 "aarch64_reg_or_zero" "rZ,*w")) + (match_operand:SI 1 "aarch64_reg_or_zero" "rZ,w")) (set (match_operand:SI 2 "memory_operand" "=m,m") - (match_operand:SI 3 "aarch64_reg_or_zero" "rZ,*w"))] + (match_operand:SI 3 "aarch64_reg_or_zero" "rZ,w"))] "rtx_equal_p (XEXP (operands[2], 0), plus_constant (Pmode, XEXP (operands[0], 0), @@ -1354,9 +1354,9 @@ (define_insn "store_pairdi" [(set (match_operand:DI 0 "aarch64_mem_pair_operand" "=Ump,Ump") - (match_operand:DI 1 "aarch64_reg_or_zero" "rZ,*w")) + (match_operand:DI 1 "aarch64_reg_or_zero" "rZ,w")) (set (match_operand:DI 2 "memory_operand" "=m,m") - (match_operand:DI 3 "aarch64_reg_or_zero" "rZ,*w"))] + (match_operand:DI 3 "aarch64_reg_or_zero" "rZ,w"))] "rtx_equal_p (XEXP (operands[2], 0), plus_constant (Pmode, XEXP (operands[0], 0), @@ -1371,9 +1371,9 @@ ;; Operands 1 and 3 are tied together by the final condition; so we allow ;; fairly lax checking on the second memory operation. (define_insn "load_pairsf" - [(set (match_operand:SF 0 "register_operand" "=w,*r") + [(set (match_operand:SF 0 "register_operand" "=w,r") (match_operand:SF 1 "aarch64_mem_pair_operand" "Ump,Ump")) - (set (match_operand:SF 2 "register_operand" "=w,*r") + (set (match_operand:SF 2 "register_operand" "=w,r") (match_operand:SF 3 "memory_operand" "m,m"))] "rtx_equal_p (XEXP (operands[3], 0), plus_constant (Pmode, @@ -1387,9 +1387,9 @@ ) (define_insn "load_pairdf" - [(set (match_operand:DF 0 "register_operand" "=w,*r") + [(set (match_operand:DF 0 "register_operand" "=w,r") (match_operand:DF 1 "aarch64_mem_pair_operand" "Ump,Ump")) - (set (match_operand:DF 2 "register_operand" "=w,*r") + (set (match_operand:DF 2 "register_operand" "=w,r") (match_operand:DF 3 "memory_operand" "m,m"))] "rtx_equal_p (XEXP (operands[3], 0), plus_constant (Pmode, @@ -1406,9 +1406,9 @@ ;; fairly lax checking on the second memory operation. (define_insn "store_pairsf" [(set (match_operand:SF 0 "aarch64_mem_pair_operand" "=Ump,Ump") - (match_operand:SF 1 "aarch64_reg_or_fp_zero" "w,*rY")) + (match_operand:SF 1 "aarch64_reg_or_fp_zero" "w,rY")) (set (match_operand:SF 2 "memory_operand" "=m,m") - (match_operand:SF 3 "aarch64_reg_or_fp_zero" "w,*rY"))] + (match_operand:SF 3 "aarch64_reg_or_fp_zero" "w,rY"))] "rtx_equal_p (XEXP (operands[2], 0), plus_constant (Pmode, XEXP (operands[0], 0), @@ -1422,9 +1422,9 @@ (define_insn "store_pairdf" [(set (match_operand:DF 0 "aarch64_mem_pair_operand" "=Ump,Ump") - (match_operand:DF 1 "aarch64_reg_or_fp_zero" "w,*rY")) + (match_operand:DF 1 "aarch64_reg_or_fp_zero" "w,rY")) (set (match_operand:DF 2 "memory_operand" "=m,m") - (match_operand:DF 3 "aarch64_reg_or_fp_zero" "w,*rY"))] + (match_operand:DF 3 "aarch64_reg_or_fp_zero" "w,rY"))] "rtx_equal_p (XEXP (operands[2], 0), plus_constant (Pmode, XEXP (operands[0], 0), @@ -1575,7 +1575,7 @@ ) (define_insn "*zero_extend<SHORT:mode><GPI:mode>2_aarch64" - [(set (match_operand:GPI 0 "register_operand" "=r,r,*w") + [(set (match_operand:GPI 0 "register_operand" "=r,r,w") (zero_extend:GPI (match_operand:SHORT 1 "nonimmediate_operand" "r,m,m")))] "" "@ @@ -5083,13 +5083,13 @@ ;; and making r = w more expensive (define_insn "<optab>_trunc<fcvt_target><GPI:mode>2" - [(set (match_operand:GPI 0 "register_operand" "=?r,w") + [(set (match_operand:GPI 0 "register_operand" "=w,?r") (FIXUORS:GPI (match_operand:<FCVT_TARGET> 1 "register_operand" "w,w")))] "TARGET_FLOAT" "@ - fcvtz<su>\t%<w>0, %<s>1 - fcvtz<su>\t%<s>0, %<s>1" - [(set_attr "type" "f_cvtf2i,neon_fp_to_int_s")] + fcvtz<su>\t%<s>0, %<s>1 + fcvtz<su>\t%<w>0, %<s>1" + [(set_attr "type" "neon_fp_to_int_s,f_cvtf2i")] ) ;; Convert HF -> SI or DI @@ -5115,7 +5115,7 @@ (define_insn "<optab><fcvt_target><GPF:mode>2" [(set (match_operand:GPF 0 "register_operand" "=w,w") - (FLOATUORS:GPF (match_operand:<FCVT_TARGET> 1 "register_operand" "w,r")))] + (FLOATUORS:GPF (match_operand:<FCVT_TARGET> 1 "register_operand" "w,?r")))] "TARGET_FLOAT" "@ <su_optab>cvtf\t%<GPF:s>0, %<s>1 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 6858e75..259d578 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-05-14 Wilco Dijkstra <wdijkstr@arm.com> + + * gcc.target/aarch64/vmov_n_1.c: Update test. + * gcc.target/aarch64/vfp-1.c: Update test. + 2018-05-14 Jakub Jelinek <jakub@redhat.com> PR target/85756 diff --git a/gcc/testsuite/gcc.target/aarch64/vfp-1.c b/gcc/testsuite/gcc.target/aarch64/vfp-1.c index 79c5714..02609bb 100644 --- a/gcc/testsuite/gcc.target/aarch64/vfp-1.c +++ b/gcc/testsuite/gcc.target/aarch64/vfp-1.c @@ -32,7 +32,7 @@ void test_sf() { /* { dg-final { scan-assembler "fsqrt\ts\[0-9\]*" } } */ f1 = sqrtf (f1); /* cmpsf */ - /* { dg-final { scan-assembler "fcmp\ts\[0-9\]*" } } */ + /* { dg-final { scan-assembler "fcmpe\ts\[0-9\]*" } } */ if (f1 < f2) cond1 = 1; else @@ -64,7 +64,7 @@ void test_df() { /* { dg-final { scan-assembler "fsqrt\td\[0-9\]*" } } */ d1 = sqrt (d1); /* cmpdf */ - /* { dg-final { scan-assembler "fcmp\td\[0-9\]*" } } */ + /* { dg-final { scan-assembler "fcmpe\td\[0-9\]*" } } */ if (d1 < d2) cond1 = 1; else @@ -82,13 +82,13 @@ void test_convert () { /* { dg-final { scan-assembler "fcvt\ts\[0-9\]*" } } */ f1 = d1; /* fixsfsi2 */ - /* { dg-final { scan-assembler "fcvtzs\tw\[0-9\], s\[0-9\]*" } } */ + /* { dg-final { scan-assembler "fcvtzs\ts\[0-9\], s\[0-9\]*" } } */ i1 = f1; /* fixdfsi2 */ /* { dg-final { scan-assembler "fcvtzs\tw\[0-9\], d\[0-9\]*" } } */ i1 = d1; /* fixunsfsi2 */ - /* { dg-final { scan-assembler "fcvtzu\tw\[0-9\], s\[0-9\]*" } } */ + /* { dg-final { scan-assembler "fcvtzu\ts\[0-9\], s\[0-9\]*" } } */ u1 = f1; /* fixunsdfsi2 */ /* { dg-final { scan-assembler "fcvtzu\tw\[0-9\], d\[0-9\]*" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vmov_n_1.c b/gcc/testsuite/gcc.target/aarch64/vmov_n_1.c index d0c2842..528cb84 100644 --- a/gcc/testsuite/gcc.target/aarch64/vmov_n_1.c +++ b/gcc/testsuite/gcc.target/aarch64/vmov_n_1.c @@ -209,11 +209,11 @@ TESTFUNC (64, 16, p) OBSCURE_FUNC (64, 8, s) TESTFUNC (64, 8, s) -/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.8b, w\[0-9\]+" 3 } } */ +/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.8b, w\[0-9\]+" 1 } } */ OBSCURE_FUNC (64, 16, s) TESTFUNC (64, 16, s) -/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.4h, w\[0-9\]+" 3 } } */ +/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.4h, w\[0-9\]+" 1 } } */ OBSCURE_FUNC (64, 32, s) TESTFUNC (64, 32, s) @@ -265,11 +265,11 @@ TESTFUNC (128, 16, p) OBSCURE_FUNC (128, 8, s) TESTFUNC (128, 8, s) -/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.16b, w\[0-9\]+" 3 } } */ +/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.16b, w\[0-9\]+" 1 } } */ OBSCURE_FUNC (128, 16, s) TESTFUNC (128, 16, s) -/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.8h, w\[0-9\]+" 3 } } */ +/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.8h, w\[0-9\]+" 1 } } */ OBSCURE_FUNC (128, 32, s) TESTFUNC (128, 32, s) |