diff options
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 120 |
2 files changed, 72 insertions, 55 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d7f9913..4e90317 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2002-05-08 Richard Sandiford <rsandifo@redhat.com> + + * config/mips/mips.md: Name the unspecs with define_constant. + (*HILO_delay): Rename to 'hilo_delay' (no star). + (reload_indi): Replace gen_rtx_UNSPEC with gen_hilo_delay. + (reload_outdi, reload_outsi): Likewise. + 2002-05-07 Kazu Hirata <kazu@cs.umass.edu> * toplev.c: Fix formatting. diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 2229f55..bbce30e 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -26,29 +26,28 @@ ;; ??? Currently does not have define_function_unit support for the R8000. ;; Must include new entries for fmadd in addition to existing entries. -;; UNSPEC values used in mips.md -;; Number USE -;; 0 movsi_ul -;; 1 movsi_usw, get_fnaddr -;; 2 reload_in*, reload_out* : sets delay on HILO register -;; 3 eh_set_return -;; 20 builtin_setjmp_setup -;; 111 movdi_usd -;; -;; UNSPEC_VOLATILE values -;; 0 blockage -;; 2 loadgp -;; 3 builtin_longjmp -;; 4 exception_receiver -;; 10 consttable_qi -;; 11 consttable_hi -;; 12 consttable_si -;; 13 consttable_di -;; 14 consttable_sf -;; 15 consttable_df -;; 16 align_2 -;; 17 align_4 -;; 18 align_8 +(define_constants + [(UNSPEC_ULW 0) + (UNSPEC_USW 1) + (UNSPEC_ULD 2) + (UNSPEC_USD 3) + (UNSPEC_GET_FNADDR 4) + (UNSPEC_HILO_DELAY 5) + (UNSPEC_BLOCKAGE 6) + (UNSPEC_LOADGP 7) + (UNSPEC_SETJMP 8) + (UNSPEC_LONGJMP 9) + (UNSPEC_EH_RECEIVER 10) + (UNSPEC_EH_RETURN 11) + (UNSPEC_CONSTTABLE_QI 12) + (UNSPEC_CONSTTABLE_HI 13) + (UNSPEC_CONSTTABLE_SI 14) + (UNSPEC_CONSTTABLE_DI 15) + (UNSPEC_CONSTTABLE_SF 16) + (UNSPEC_CONSTTABLE_DF 17) + (UNSPEC_ALIGN_2 18) + (UNSPEC_ALIGN_4 19) + (UNSPEC_ALIGN_8 20)]) ;; .................... @@ -4831,7 +4830,8 @@ move\\t%0,%z4\\n\\ (define_insn "movsi_ulw" [(set (match_operand:SI 0 "register_operand" "=&d,&d") - (unspec:SI [(match_operand:BLK 1 "general_operand" "R,o")] 0))] + (unspec:SI [(match_operand:BLK 1 "general_operand" "R,o")] + UNSPEC_ULW))] "!TARGET_MIPS16" "* { @@ -4860,7 +4860,8 @@ move\\t%0,%z4\\n\\ (define_insn "movsi_usw" [(set (match_operand:BLK 0 "memory_operand" "=R,o") - (unspec:BLK [(match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")] 1))] + (unspec:BLK [(match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")] + UNSPEC_USW))] "!TARGET_MIPS16" "* { @@ -4890,7 +4891,8 @@ move\\t%0,%z4\\n\\ (define_insn "movdi_uld" [(set (match_operand:DI 0 "register_operand" "=&d,&d") - (unspec:DI [(match_operand:BLK 1 "general_operand" "R,o")] 0))] + (unspec:DI [(match_operand:BLK 1 "general_operand" "R,o")] + UNSPEC_ULD))] "" "* { @@ -4919,7 +4921,8 @@ move\\t%0,%z4\\n\\ (define_insn "movdi_usd" [(set (match_operand:BLK 0 "memory_operand" "=R,o") - (unspec:BLK [(match_operand:DI 1 "reg_or_0_operand" "dJ,dJ")] 111))] + (unspec:BLK [(match_operand:DI 1 "reg_or_0_operand" "dJ,dJ")] + UNSPEC_USD))] "" "* { @@ -5259,7 +5262,7 @@ move\\t%0,%z4\\n\\ emit_move_insn (gen_rtx_REG (SImode, 64), scratch); emit_move_insn (scratch, lo_word); emit_move_insn (gen_rtx (REG, SImode, 65), scratch); - emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[0]), 2)); + emit_insn (gen_hilo_delay (operands[0])); } else { @@ -5268,7 +5271,7 @@ move\\t%0,%z4\\n\\ emit_insn (gen_ashldi3 (scratch, operands[1], GEN_INT (32))); emit_insn (gen_ashrdi3 (scratch, scratch, GEN_INT (32))); emit_insn (gen_movdi (gen_rtx (REG, DImode, 65), scratch)); - emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[0]), 2)); + emit_insn (gen_hilo_delay (operands[0])); } DONE; } @@ -5280,7 +5283,7 @@ move\\t%0,%z4\\n\\ emit_insn (gen_movdi (operands[0], gen_rtx_REG (DImode, 64))); emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32))); emit_insn (gen_iordi3 (operands[0], operands[0], scratch)); - emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[1]), 2)); + emit_insn (gen_hilo_delay (operands[1])); DONE; } /* This handles moves between a float register and HI/LO. */ @@ -5310,7 +5313,7 @@ move\\t%0,%z4\\n\\ emit_insn (gen_ashldi3 (scratch, operands[1], GEN_INT (32))); emit_insn (gen_ashrdi3 (scratch, scratch, GEN_INT (32))); emit_insn (gen_movdi (gen_rtx (REG, DImode, 65), scratch)); - emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[0]), 2)); + emit_insn (gen_hilo_delay (operands[0])); DONE; } if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == HILO_REGNUM) @@ -5339,7 +5342,7 @@ move\\t%0,%z4\\n\\ emit_move_insn (hi_word, scratch); emit_move_insn (scratch, gen_rtx_REG (SImode, 65)); emit_move_insn (lo_word, scratch); - emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[1]), 2)); + emit_insn (gen_hilo_delay (operands[1])); } else if (TARGET_MIPS16 && ! M16_REG_P (REGNO (operands[0]))) { @@ -5354,7 +5357,7 @@ move\\t%0,%z4\\n\\ emit_insn (gen_ashldi3 (scratch2, scratch2, GEN_INT (32))); emit_insn (gen_iordi3 (scratch, scratch, scratch2)); emit_insn (gen_movdi (operands[0], scratch)); - emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[1]), 2)); + emit_insn (gen_hilo_delay (operands[1])); } else { @@ -5364,7 +5367,7 @@ move\\t%0,%z4\\n\\ emit_insn (gen_movdi (operands[0], gen_rtx (REG, DImode, 64))); emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32))); emit_insn (gen_iordi3 (operands[0], operands[0], scratch)); - emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[1]), 2)); + emit_insn (gen_hilo_delay (operands[1])); } DONE; } @@ -5693,7 +5696,7 @@ move\\t%0,%z4\\n\\ emit_insn (gen_movsi (gen_rtx_REG (SImode, 65), operands[1])); emit_insn (gen_ashrsi3 (operands[2], operands[1], GEN_INT (31))); emit_insn (gen_movsi (gen_rtx (REG, SImode, 64), operands[2])); - emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[0]), 2)); + emit_insn (gen_hilo_delay (operands[0])); DONE; } /* Use a mult to reload LO on mips16. ??? This is hideous. */ @@ -5820,8 +5823,8 @@ move\\t%0,%z4\\n\\ ;; This insn is for the unspec delay for HILO. -(define_insn "*HILO_delay" - [(unspec [(match_operand 0 "register_operand" "=b")] 2 )] +(define_insn "hilo_delay" + [(unspec [(match_operand 0 "register_operand" "=b")] UNSPEC_HILO_DELAY)] "" "" [(set_attr "type" "nop") @@ -6386,7 +6389,8 @@ move\\t%0,%z4\\n\\ (define_insn "loadgp" [(set (reg:DI 28) (unspec_volatile:DI [(match_operand:DI 0 "address_operand" "") - (match_operand:DI 1 "register_operand" "")] 2)) + (match_operand:DI 1 "register_operand" "")] + UNSPEC_LOADGP)) (clobber (reg:DI 1))] "" "%[lui\\t$1,%%hi(%%neg(%%gp_rel(%a0)))\\n\\taddiu\\t$1,$1,%%lo(%%neg(%%gp_rel(%a0)))\\n\\tdaddu\\t$gp,$1,%1%]" @@ -9563,7 +9567,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2" ;; this is easy. (define_expand "builtin_setjmp_setup" - [(unspec [(match_operand 0 "register_operand" "r")] 20)] + [(unspec [(match_operand 0 "register_operand" "r")] UNSPEC_SETJMP)] "TARGET_ABICALLS" " { @@ -9592,7 +9596,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2" ;; target address in t9 so that we can use it for loading $gp. (define_expand "builtin_longjmp" - [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)] + [(unspec_volatile [(match_operand 0 "register_operand" "r")] UNSPEC_LONGJMP)] "TARGET_ABICALLS" " { @@ -9642,7 +9646,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2" ;; saved or used to pass arguments. (define_insn "blockage" - [(unspec_volatile [(const_int 0)] 0)] + [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)] "" "" [(set_attr "type" "unknown") @@ -9688,7 +9692,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2" (define_insn "get_fnaddr" [(set (match_operand 0 "register_operand" "=d") - (unspec [(match_operand 1 "" "")] 1)) + (unspec [(match_operand 1 "" "")] UNSPEC_GET_FNADDR)) (clobber (reg:SI 31))] "TARGET_EMBEDDED_PIC && GET_CODE (operands[1]) == SYMBOL_REF" @@ -9721,19 +9725,19 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2" ;; until we know where it will be put in the stack frame. (define_insn "eh_set_lr_si" - [(unspec [(match_operand:SI 0 "register_operand" "r")] 3) + [(unspec [(match_operand:SI 0 "register_operand" "r")] UNSPEC_EH_RETURN) (clobber (match_scratch:SI 1 "=&r"))] "! TARGET_64BIT" "#") (define_insn "eh_set_lr_di" - [(unspec [(match_operand:DI 0 "register_operand" "r")] 3) + [(unspec [(match_operand:DI 0 "register_operand" "r")] UNSPEC_EH_RETURN) (clobber (match_scratch:DI 1 "=&r"))] "TARGET_64BIT" "#") (define_split - [(unspec [(match_operand 0 "register_operand" "")] 3) + [(unspec [(match_operand 0 "register_operand" "")] UNSPEC_EH_RETURN) (clobber (match_scratch 1 ""))] "reload_completed && !TARGET_DEBUG_D_MODE" [(const_int 0)] @@ -9766,7 +9770,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2" }") (define_insn "exception_receiver" - [(unspec_volatile [(const_int 0)] 4)] + [(unspec_volatile [(const_int 0)] UNSPEC_EH_RECEIVER)] "TARGET_ABICALLS && (mips_abi == ABI_32 || mips_abi == ABI_O64)" "* { @@ -10567,7 +10571,8 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2" ;; (define_insn "consttable_qi" - [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "=g")] 10)] + [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "=g")] + UNSPEC_CONSTTABLE_QI)] "TARGET_MIPS16" "* { @@ -10579,7 +10584,8 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2" (set_attr "length" "8")]) (define_insn "consttable_hi" - [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "=g")] 11)] + [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "=g")] + UNSPEC_CONSTTABLE_HI)] "TARGET_MIPS16" "* { @@ -10591,7 +10597,8 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2" (set_attr "length" "8")]) (define_insn "consttable_si" - [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "=g")] 12)] + [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "=g")] + UNSPEC_CONSTTABLE_SI)] "TARGET_MIPS16" "* { @@ -10603,7 +10610,8 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2" (set_attr "length" "8")]) (define_insn "consttable_di" - [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "=g")] 13)] + [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "=g")] + UNSPEC_CONSTTABLE_DI)] "TARGET_MIPS16" "* { @@ -10615,7 +10623,8 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2" (set_attr "length" "16")]) (define_insn "consttable_sf" - [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "=g")] 14)] + [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "=g")] + UNSPEC_CONSTTABLE_SF)] "TARGET_MIPS16" "* { @@ -10632,7 +10641,8 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2" (set_attr "length" "8")]) (define_insn "consttable_df" - [(unspec_volatile [(match_operand:DF 0 "consttable_operand" "=g")] 15)] + [(unspec_volatile [(match_operand:DF 0 "consttable_operand" "=g")] + UNSPEC_CONSTTABLE_DF)] "TARGET_MIPS16" "* { @@ -10649,7 +10659,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2" (set_attr "length" "16")]) (define_insn "align_2" - [(unspec_volatile [(const_int 0)] 16)] + [(unspec_volatile [(const_int 0)] UNSPEC_ALIGN_2)] "TARGET_MIPS16" ".align 1" [(set_attr "type" "unknown") @@ -10657,7 +10667,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2" (set_attr "length" "8")]) (define_insn "align_4" - [(unspec_volatile [(const_int 0)] 17)] + [(unspec_volatile [(const_int 0)] UNSPEC_ALIGN_4)] "TARGET_MIPS16" ".align 2" [(set_attr "type" "unknown") @@ -10665,7 +10675,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2" (set_attr "length" "8")]) (define_insn "align_8" - [(unspec_volatile [(const_int 0)] 18)] + [(unspec_volatile [(const_int 0)] UNSPEC_ALIGN_8)] "TARGET_MIPS16" ".align 3" [(set_attr "type" "unknown") |