diff options
| -rw-r--r-- | gcc/ChangeLog | 12 | ||||
| -rw-r--r-- | gcc/config/sparc/sparc.md | 323 |
2 files changed, 161 insertions, 174 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 54ae922..659e6ba 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,15 @@ +2015-11-20 Eric Botcazou <ebotcazou@adacore.com> + + * config/sparc/sparc.md (umulxhi_vis): Move around. + (*umulxhi_sp64): Likewise. + (umulxhi_v8plus): Likewise. + (xmulx_vis): Likewise. + (*xmulx_sp64): Likewise. + (xmulx_v8plus): Likewise. + (xmulxhi_vis): Likewise. + (*xmulxhi_sp64): Likewise. + (xmulxhi_v8plus): Likewise. + 2015-11-20 David Malcolm <dmalcolm@redhat.com> PR 62314 diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index de65cc6..9cc74f1 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -609,7 +609,7 @@ return "fcmpq\t%1, %2"; } [(set_attr "type" "fpcmp")]) - + ;; Next come the scc insns. ;; Note that the boolean result (operand 0) takes on DImode @@ -647,8 +647,6 @@ "TARGET_FPU" { if (emit_scc_insn (operands)) DONE; else FAIL; }) - - ;; Seq_special[_xxx] and sne_special[_xxx] clobber the CC reg, because they ;; generate addcc/subcc instructions. @@ -1137,7 +1135,7 @@ (match_dup 0)))] "") - + ;; These control RTL generation for conditional jump insns (define_expand "cbranchcc4" @@ -1318,7 +1316,6 @@ ;; There are no 32 bit brreg insns. -;; XXX (define_insn "*normal_int_branch_sp64" [(set (pc) (if_then_else (match_operator 0 "v9_register_compare_operator" @@ -1335,7 +1332,6 @@ [(set_attr "type" "branch") (set_attr "branch_type" "reg")]) -;; XXX (define_insn "*inverted_int_branch_sp64" [(set (pc) (if_then_else (match_operator 0 "v9_register_compare_operator" @@ -2730,8 +2726,6 @@ DONE; }) -;; Conditional move define_insns - (define_insn "*mov<I:mode>_cc_v9" [(set (match_operand:I 0 "register_operand" "=r") (if_then_else:I (match_operator 1 "comparison_operator" @@ -2896,7 +2890,7 @@ } [(set_attr "length" "2")]) - + ;; Zero-extension instructions ;; These patterns originally accepted general_operands, however, slightly @@ -4043,7 +4037,6 @@ [(set_attr "type" "imul")]) ;; V8plus wide multiply. -;; XXX (define_insn "muldi3_v8plus" [(set (match_operand:DI 0 "register_operand" "=r,h") (mult:DI (match_operand:DI 1 "arith_operand" "%r,0") @@ -4094,7 +4087,6 @@ ;; V9 puts the 64-bit product in a 64-bit register. Only out or global ;; registers can hold 64-bit values in the V8plus environment. -;; XXX (define_insn "mulsidi3_v8plus" [(set (match_operand:DI 0 "register_operand" "=h,r") (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r")) @@ -4107,7 +4099,6 @@ [(set_attr "type" "multi") (set_attr "length" "2,3")]) -;; XXX (define_insn "const_mulsidi3_v8plus" [(set (match_operand:DI 0 "register_operand" "=h,r") (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r")) @@ -4120,7 +4111,6 @@ [(set_attr "type" "multi") (set_attr "length" "2,3")]) -;; XXX (define_insn "*mulsidi3_sp32" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) @@ -4148,7 +4138,6 @@ ;; Extra pattern, because sign_extend of a constant isn't valid. -;; XXX (define_insn "const_mulsidi3_sp32" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) @@ -4203,7 +4192,6 @@ } }) -;; XXX (define_insn "smulsi3_highpart_v8plus" [(set (match_operand:SI 0 "register_operand" "=h,r") (truncate:SI @@ -4219,7 +4207,6 @@ (set_attr "length" "2")]) ;; The combiner changes TRUNCATE in the previous pattern to SUBREG. -;; XXX (define_insn "" [(set (match_operand:SI 0 "register_operand" "=h,r") (subreg:SI @@ -4236,7 +4223,6 @@ [(set_attr "type" "multi") (set_attr "length" "2")]) -;; XXX (define_insn "const_smulsi3_highpart_v8plus" [(set (match_operand:SI 0 "register_operand" "=h,r") (truncate:SI @@ -4251,7 +4237,6 @@ [(set_attr "type" "multi") (set_attr "length" "2")]) -;; XXX (define_insn "*smulsi3_highpart_sp32" [(set (match_operand:SI 0 "register_operand" "=r") (truncate:SI @@ -4263,7 +4248,6 @@ [(set_attr "type" "multi") (set_attr "length" "2")]) -;; XXX (define_insn "const_smulsi3_highpart" [(set (match_operand:SI 0 "register_operand" "=r") (truncate:SI @@ -4301,7 +4285,6 @@ } }) -;; XXX (define_insn "umulsidi3_v8plus" [(set (match_operand:DI 0 "register_operand" "=h,r") (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r")) @@ -4314,7 +4297,6 @@ [(set_attr "type" "multi") (set_attr "length" "2,3")]) -;; XXX (define_insn "*umulsidi3_sp32" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) @@ -4342,7 +4324,6 @@ ;; Extra pattern, because sign_extend of a constant isn't valid. -;; XXX (define_insn "const_umulsidi3_sp32" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) @@ -4368,7 +4349,6 @@ "umul\t%1, %s2, %0" [(set_attr "type" "imul")]) -;; XXX (define_insn "const_umulsidi3_v8plus" [(set (match_operand:DI 0 "register_operand" "=h,r") (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r")) @@ -4410,7 +4390,6 @@ } }) -;; XXX (define_insn "umulsi3_highpart_v8plus" [(set (match_operand:SI 0 "register_operand" "=h,r") (truncate:SI @@ -4425,7 +4404,6 @@ [(set_attr "type" "multi") (set_attr "length" "2")]) -;; XXX (define_insn "const_umulsi3_highpart_v8plus" [(set (match_operand:SI 0 "register_operand" "=h,r") (truncate:SI @@ -4440,7 +4418,6 @@ [(set_attr "type" "multi") (set_attr "length" "2")]) -;; XXX (define_insn "*umulsi3_highpart_sp32" [(set (match_operand:SI 0 "register_operand" "=r") (truncate:SI @@ -4452,7 +4429,6 @@ [(set_attr "type" "multi") (set_attr "length" "2")]) -;; XXX (define_insn "const_umulsi3_highpart" [(set (match_operand:SI 0 "register_operand" "=r") (truncate:SI @@ -4464,6 +4440,148 @@ [(set_attr "type" "multi") (set_attr "length" "2")]) + +(define_expand "umulxhi_vis" + [(set (match_operand:DI 0 "register_operand" "") + (truncate:DI + (lshiftrt:TI + (mult:TI (zero_extend:TI + (match_operand:DI 1 "arith_operand" "")) + (zero_extend:TI + (match_operand:DI 2 "arith_operand" ""))) + (const_int 64))))] + "TARGET_VIS3" +{ + if (! TARGET_ARCH64) + { + emit_insn (gen_umulxhi_v8plus (operands[0], operands[1], operands[2])); + DONE; + } +}) + +(define_insn "*umulxhi_sp64" + [(set (match_operand:DI 0 "register_operand" "=r") + (truncate:DI + (lshiftrt:TI + (mult:TI (zero_extend:TI + (match_operand:DI 1 "arith_operand" "%r")) + (zero_extend:TI + (match_operand:DI 2 "arith_operand" "rI"))) + (const_int 64))))] + "TARGET_VIS3 && TARGET_ARCH64" + "umulxhi\t%1, %2, %0" + [(set_attr "type" "imul")]) + +(define_insn "umulxhi_v8plus" + [(set (match_operand:DI 0 "register_operand" "=r,h") + (truncate:DI + (lshiftrt:TI + (mult:TI (zero_extend:TI + (match_operand:DI 1 "arith_operand" "%r,0")) + (zero_extend:TI + (match_operand:DI 2 "arith_operand" "rI,rI"))) + (const_int 64)))) + (clobber (match_scratch:SI 3 "=&h,X")) + (clobber (match_scratch:SI 4 "=&h,X"))] + "TARGET_VIS3 && ! TARGET_ARCH64" + "* return output_v8plus_mult (insn, operands, \"umulxhi\");" + [(set_attr "type" "imul") + (set_attr "length" "9,8")]) + +(define_expand "xmulx_vis" + [(set (match_operand:DI 0 "register_operand" "") + (truncate:DI + (unspec:TI [(zero_extend:TI + (match_operand:DI 1 "arith_operand" "")) + (zero_extend:TI + (match_operand:DI 2 "arith_operand" ""))] + UNSPEC_XMUL)))] + "TARGET_VIS3" +{ + if (! TARGET_ARCH64) + { + emit_insn (gen_xmulx_v8plus (operands[0], operands[1], operands[2])); + DONE; + } +}) + +(define_insn "*xmulx_sp64" + [(set (match_operand:DI 0 "register_operand" "=r") + (truncate:DI + (unspec:TI [(zero_extend:TI + (match_operand:DI 1 "arith_operand" "%r")) + (zero_extend:TI + (match_operand:DI 2 "arith_operand" "rI"))] + UNSPEC_XMUL)))] + "TARGET_VIS3 && TARGET_ARCH64" + "xmulx\t%1, %2, %0" + [(set_attr "type" "imul")]) + +(define_insn "xmulx_v8plus" + [(set (match_operand:DI 0 "register_operand" "=r,h") + (truncate:DI + (unspec:TI [(zero_extend:TI + (match_operand:DI 1 "arith_operand" "%r,0")) + (zero_extend:TI + (match_operand:DI 2 "arith_operand" "rI,rI"))] + UNSPEC_XMUL))) + (clobber (match_scratch:SI 3 "=&h,X")) + (clobber (match_scratch:SI 4 "=&h,X"))] + "TARGET_VIS3 && ! TARGET_ARCH64" + "* return output_v8plus_mult (insn, operands, \"xmulx\");" + [(set_attr "type" "imul") + (set_attr "length" "9,8")]) + +(define_expand "xmulxhi_vis" + [(set (match_operand:DI 0 "register_operand" "") + (truncate:DI + (lshiftrt:TI + (unspec:TI [(zero_extend:TI + (match_operand:DI 1 "arith_operand" "")) + (zero_extend:TI + (match_operand:DI 2 "arith_operand" ""))] + UNSPEC_XMUL) + (const_int 64))))] + "TARGET_VIS3" +{ + if (! TARGET_ARCH64) + { + emit_insn (gen_xmulxhi_v8plus (operands[0], operands[1], operands[2])); + DONE; + } +}) + +(define_insn "*xmulxhi_sp64" + [(set (match_operand:DI 0 "register_operand" "=r") + (truncate:DI + (lshiftrt:TI + (unspec:TI [(zero_extend:TI + (match_operand:DI 1 "arith_operand" "%r")) + (zero_extend:TI + (match_operand:DI 2 "arith_operand" "rI"))] + UNSPEC_XMUL) + (const_int 64))))] + "TARGET_VIS3 && TARGET_ARCH64" + "xmulxhi\t%1, %2, %0" + [(set_attr "type" "imul")]) + +(define_insn "xmulxhi_v8plus" + [(set (match_operand:DI 0 "register_operand" "=r,h") + (truncate:DI + (lshiftrt:TI + (unspec:TI [(zero_extend:TI + (match_operand:DI 1 "arith_operand" "%r,0")) + (zero_extend:TI + (match_operand:DI 2 "arith_operand" "rI,rI"))] + UNSPEC_XMUL) + (const_int 64)))) + (clobber (match_scratch:SI 3 "=&h,X")) + (clobber (match_scratch:SI 4 "=&h,X"))] + "TARGET_VIS3 && !TARGET_ARCH64" + "* return output_v8plus_mult (insn, operands, \"xmulxhi\");" + [(set_attr "type" "imul") + (set_attr "length" "9,8")]) + (define_expand "divsi3" [(parallel [(set (match_operand:SI 0 "register_operand" "") (div:SI (match_operand:SI 1 "register_operand" "") @@ -4562,7 +4680,6 @@ (if_then_else (eq_attr "isa" "v9") (const_int 3) (const_int 6)))]) -;; XXX (define_expand "udivsi3" [(set (match_operand:SI 0 "register_operand" "") (udiv:SI (match_operand:SI 1 "nonimmediate_operand" "") @@ -4651,7 +4768,8 @@ (if_then_else (eq_attr "isa" "v9") (const_int 2) (const_int 5)))]) -; sparclet multiply/accumulate insns + +;; SPARClet multiply/accumulate insns (define_insn "*smacsi" [(set (match_operand:SI 0 "register_operand" "=r") @@ -5828,7 +5946,6 @@ } [(set_attr "type" "shift")]) -;; XXX UGH! (define_insn "ashldi3_v8plus" [(set (match_operand:DI 0 "register_operand" "=&h,&h,r") (ashift:DI (match_operand:DI 1 "arith_operand" "rI,0,rI") @@ -5938,7 +6055,6 @@ } [(set_attr "type" "shift")]) -;; XXX (define_insn "ashrdi3_v8plus" [(set (match_operand:DI 0 "register_operand" "=&h,&h,r") (ashiftrt:DI (match_operand:DI 1 "arith_operand" "rI,0,rI") @@ -6028,7 +6144,6 @@ } [(set_attr "type" "shift")]) -;; XXX (define_insn "lshrdi3_v8plus" [(set (match_operand:DI 0 "register_operand" "=&h,&h,r") (lshiftrt:DI (match_operand:DI 1 "arith_operand" "rI,0,rI") @@ -6416,6 +6531,7 @@ DONE; }) + ;; Tail call instructions. (define_expand "sibcall" @@ -7221,7 +7337,6 @@ FAIL; operands[2] = const0_rtx;") - (define_insn "" [(trap_if (match_operator 0 "noov_compare_operator" [(reg:CC CC_REG) (const_int 0)]) (match_operand:SI 1 "arith_operand" "rM"))] @@ -7896,6 +8011,7 @@ [(set_attr "type" "multi") (set_attr "length" "4")]) + ;; Vector instructions. (define_mode_iterator VM32 [V1SI V2HI V4QI]) @@ -8879,145 +8995,4 @@ [(set_attr "type" "fp") (set_attr "fptype" "double")]) -(define_expand "umulxhi_vis" - [(set (match_operand:DI 0 "register_operand" "") - (truncate:DI - (lshiftrt:TI - (mult:TI (zero_extend:TI - (match_operand:DI 1 "arith_operand" "")) - (zero_extend:TI - (match_operand:DI 2 "arith_operand" ""))) - (const_int 64))))] - "TARGET_VIS3" -{ - if (! TARGET_ARCH64) - { - emit_insn (gen_umulxhi_v8plus (operands[0], operands[1], operands[2])); - DONE; - } -}) - -(define_insn "*umulxhi_sp64" - [(set (match_operand:DI 0 "register_operand" "=r") - (truncate:DI - (lshiftrt:TI - (mult:TI (zero_extend:TI - (match_operand:DI 1 "arith_operand" "%r")) - (zero_extend:TI - (match_operand:DI 2 "arith_operand" "rI"))) - (const_int 64))))] - "TARGET_VIS3 && TARGET_ARCH64" - "umulxhi\t%1, %2, %0" - [(set_attr "type" "imul")]) - -(define_insn "umulxhi_v8plus" - [(set (match_operand:DI 0 "register_operand" "=r,h") - (truncate:DI - (lshiftrt:TI - (mult:TI (zero_extend:TI - (match_operand:DI 1 "arith_operand" "%r,0")) - (zero_extend:TI - (match_operand:DI 2 "arith_operand" "rI,rI"))) - (const_int 64)))) - (clobber (match_scratch:SI 3 "=&h,X")) - (clobber (match_scratch:SI 4 "=&h,X"))] - "TARGET_VIS3 && ! TARGET_ARCH64" - "* return output_v8plus_mult (insn, operands, \"umulxhi\");" - [(set_attr "type" "imul") - (set_attr "length" "9,8")]) - -(define_expand "xmulx_vis" - [(set (match_operand:DI 0 "register_operand" "") - (truncate:DI - (unspec:TI [(zero_extend:TI - (match_operand:DI 1 "arith_operand" "")) - (zero_extend:TI - (match_operand:DI 2 "arith_operand" ""))] - UNSPEC_XMUL)))] - "TARGET_VIS3" -{ - if (! TARGET_ARCH64) - { - emit_insn (gen_xmulx_v8plus (operands[0], operands[1], operands[2])); - DONE; - } -}) - -(define_insn "*xmulx_sp64" - [(set (match_operand:DI 0 "register_operand" "=r") - (truncate:DI - (unspec:TI [(zero_extend:TI - (match_operand:DI 1 "arith_operand" "%r")) - (zero_extend:TI - (match_operand:DI 2 "arith_operand" "rI"))] - UNSPEC_XMUL)))] - "TARGET_VIS3 && TARGET_ARCH64" - "xmulx\t%1, %2, %0" - [(set_attr "type" "imul")]) - -(define_insn "xmulx_v8plus" - [(set (match_operand:DI 0 "register_operand" "=r,h") - (truncate:DI - (unspec:TI [(zero_extend:TI - (match_operand:DI 1 "arith_operand" "%r,0")) - (zero_extend:TI - (match_operand:DI 2 "arith_operand" "rI,rI"))] - UNSPEC_XMUL))) - (clobber (match_scratch:SI 3 "=&h,X")) - (clobber (match_scratch:SI 4 "=&h,X"))] - "TARGET_VIS3 && ! TARGET_ARCH64" - "* return output_v8plus_mult (insn, operands, \"xmulx\");" - [(set_attr "type" "imul") - (set_attr "length" "9,8")]) - -(define_expand "xmulxhi_vis" - [(set (match_operand:DI 0 "register_operand" "") - (truncate:DI - (lshiftrt:TI - (unspec:TI [(zero_extend:TI - (match_operand:DI 1 "arith_operand" "")) - (zero_extend:TI - (match_operand:DI 2 "arith_operand" ""))] - UNSPEC_XMUL) - (const_int 64))))] - "TARGET_VIS3" -{ - if (! TARGET_ARCH64) - { - emit_insn (gen_xmulxhi_v8plus (operands[0], operands[1], operands[2])); - DONE; - } -}) - -(define_insn "*xmulxhi_sp64" - [(set (match_operand:DI 0 "register_operand" "=r") - (truncate:DI - (lshiftrt:TI - (unspec:TI [(zero_extend:TI - (match_operand:DI 1 "arith_operand" "%r")) - (zero_extend:TI - (match_operand:DI 2 "arith_operand" "rI"))] - UNSPEC_XMUL) - (const_int 64))))] - "TARGET_VIS3 && TARGET_ARCH64" - "xmulxhi\t%1, %2, %0" - [(set_attr "type" "imul")]) - -(define_insn "xmulxhi_v8plus" - [(set (match_operand:DI 0 "register_operand" "=r,h") - (truncate:DI - (lshiftrt:TI - (unspec:TI [(zero_extend:TI - (match_operand:DI 1 "arith_operand" "%r,0")) - (zero_extend:TI - (match_operand:DI 2 "arith_operand" "rI,rI"))] - UNSPEC_XMUL) - (const_int 64)))) - (clobber (match_scratch:SI 3 "=&h,X")) - (clobber (match_scratch:SI 4 "=&h,X"))] - "TARGET_VIS3 && !TARGET_ARCH64" - "* return output_v8plus_mult (insn, operands, \"xmulxhi\");" - [(set_attr "type" "imul") - (set_attr "length" "9,8")]) - (include "sync.md") |