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-rw-r--r--gcc/ChangeLog10
-rw-r--r--gcc/config/aarch64/aarch64-simd.md23
-rw-r--r--gcc/config/aarch64/iterators.md5
3 files changed, 38 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index bef76a8..3c42d60 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,15 @@
2013-04-29 James Greenhalgh <james.greenhalgh@arm.com>
+ * config/aarch64/aarch64-simd.md
+ (<optab><VDQF:mode><fcvt_target>2): New, maps to fix, fixuns.
+ (<fix_trunc_optab><VDQF:mode><fcvt_target>2): New, maps to
+ fix_trunc, fixuns_trunc.
+ (ftrunc<VDQF:mode>2): New.
+ * config/aarch64/iterators.md (optab): Add fix, fixuns.
+ (fix_trunc_optab): New.
+
+2013-04-29 James Greenhalgh <james.greenhalgh@arm.com>
+
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): Vectorize over ifloorf,
iceilf, lround, iroundf.
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 4546094..32ea587 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -1257,6 +1257,29 @@
(set_attr "simd_mode" "<MODE>")]
)
+(define_expand "<optab><VDQF:mode><fcvt_target>2"
+ [(set (match_operand:<FCVT_TARGET> 0 "register_operand")
+ (FIXUORS:<FCVT_TARGET> (unspec:<FCVT_TARGET>
+ [(match_operand:VDQF 1 "register_operand")]
+ UNSPEC_FRINTZ)))]
+ "TARGET_SIMD"
+ {})
+
+(define_expand "<fix_trunc_optab><VDQF:mode><fcvt_target>2"
+ [(set (match_operand:<FCVT_TARGET> 0 "register_operand")
+ (FIXUORS:<FCVT_TARGET> (unspec:<FCVT_TARGET>
+ [(match_operand:VDQF 1 "register_operand")]
+ UNSPEC_FRINTZ)))]
+ "TARGET_SIMD"
+ {})
+
+(define_expand "ftrunc<VDQF:mode>2"
+ [(set (match_operand:VDQF 0 "register_operand")
+ (unspec:VDQF [(match_operand:VDQF 1 "register_operand")]
+ UNSPEC_FRINTZ))]
+ "TARGET_SIMD"
+ {})
+
(define_insn "<optab><fcvt_target><VDQF:mode>2"
[(set (match_operand:VDQF 0 "register_operand" "=w")
(FLOATUORS:VDQF
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 8668d3f..d774c4c 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -560,6 +560,8 @@
(zero_extend "zero_extend")
(sign_extract "extv")
(zero_extract "extzv")
+ (fix "fix")
+ (unsigned_fix "fixuns")
(float "float")
(unsigned_float "floatuns")
(and "and")
@@ -580,6 +582,9 @@
(lt "lt")
(ge "ge")])
+(define_code_attr fix_trunc_optab [(fix "fix_trunc")
+ (unsigned_fix "fixuns_trunc")])
+
;; Optab prefix for sign/zero-extending operations
(define_code_attr su_optab [(sign_extend "") (zero_extend "u")
(div "") (udiv "u")