diff options
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/i386/i386.c | 2 |
2 files changed, 5 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 71d8a30..2129d7a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2017-09-26 Jakub Jelinek <jakub@redhat.com> + PR target/82267 + * config/i386/i386.c (ix86_print_operand_address_as): Only test + REGNO (base) == SP_REG if base is a REG. + PR middle-end/35691 * tree-ssa-reassoc.c (update_range_test): Dump r->exp each time if it is different SSA_NAME. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index d52d1df..63db7ac 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -19957,7 +19957,7 @@ ix86_print_operand_address_as (FILE *file, rtx addr, encode %esp as %rsp to avoid 0x67 prefix if there is no index or base register. */ if (TARGET_X32 && Pmode == SImode - && ((!index && base && REGNO (base) == SP_REG) + && ((!index && base && REG_P (base) && REGNO (base) == SP_REG) || (!base && index && REGNO (index) == SP_REG))) code = 'q'; |