diff options
| -rw-r--r-- | gcc/config/riscv/constraints.md | 9 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv.md | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c | 3 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c | 3 |
4 files changed, 15 insertions, 4 deletions
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index a9ee346..3ab6d54 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -243,6 +243,15 @@ (and (match_code "mem") (match_test "th_memidx_legitimate_index_p (op, true)"))) +(define_memory_constraint "th_m_noi" + "@internal + A MEM with does not match XTheadMemIdx operands." + (and (match_code "mem") + (and (match_test "!th_memidx_legitimate_modify_p (op, true)") + (and (match_test "!th_memidx_legitimate_modify_p (op, false)") + (and (match_test "!th_memidx_legitimate_index_p (op, false)") + (match_test "!th_memidx_legitimate_index_p (op, true)")))))) + ;; CORE-V Constraints (define_constraint "CV_alu_pow2" "@internal diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index d9f6c17..f46851d 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2592,8 +2592,8 @@ ;; In RV32, we lack fmv.x.d and fmv.d.x. Go through memory instead. ;; (However, we can still use fcvt.d.w to zero a floating-point register.) (define_insn "*movdf_hardfloat_rv32" - [(set (match_operand:DF 0 "nonimmediate_operand" "=f, f,f,f,m,m,*zmvf,*zmvr, *r,*r,*m") - (match_operand:DF 1 "move_operand" " f,zfli,G,m,f,G,*zmvr,*zmvf,*r*G,*m,*r"))] + [(set (match_operand:DF 0 "nonimmediate_operand" "=f, f,f,f,m,m,*zmvf,*zmvr, *r,*r,*th_m_noi") + (match_operand:DF 1 "move_operand" " f,zfli,G,m,f,G,*zmvr,*zmvf,*r*G,*th_m_noi,*r"))] "!TARGET_64BIT && TARGET_DOUBLE_FLOAT && (register_operand (operands[0], DFmode) || reg_or_0_operand (operands[1], DFmode))" diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c index 7c70b77..6746c31 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c @@ -35,5 +35,6 @@ double foo (int i, int j) return z; } -/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */ +/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */ +/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */ /* { dg-final { scan-assembler-times {\mth\.fmv\.hw\.x\M} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c index 4215eab..fb1ac2b 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c @@ -35,5 +35,6 @@ double foo (int i, int j) return z; } -/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */ +/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */ +/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */ /* { dg-final { scan-assembler-times {\mfmvp\.d\.x\M} 3 } } */ |