diff options
| -rw-r--r-- | ChangeLog | 14 | ||||
| -rw-r--r-- | contrib/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/ChangeLog | 243 | ||||
| -rw-r--r-- | gcc/DATESTAMP | 2 | ||||
| -rw-r--r-- | gcc/analyzer/ChangeLog | 18 | ||||
| -rw-r--r-- | gcc/fortran/ChangeLog | 10 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 57 | ||||
| -rw-r--r-- | libcpp/ChangeLog | 10 |
8 files changed, 357 insertions, 1 deletions
@@ -1,3 +1,17 @@ +2022-08-18 Sergei Trofimovich <siarheit@google.com> + + * Makefile.def: Drop libelf module and gcc-configure dependency + on it. + * Makefile.in: Regenerate with 'autogen Makefile.def'. + * Makefile.tpl (HOST_EXPORTS): Drop unused LIBELFLIBS and + LIBELFINC. + * configure: Regenrate. + * configure.ac (host_libs): Drop unused libelf. + +2022-08-18 Sergei Trofimovich <siarheit@google.com> + + * Makefile.in: Regenerate. + 2022-08-04 Eugene Rozenfeld <erozen@microsoft.com> * MAINTAINERS: Add myself as AutoFDO maintainer. diff --git a/contrib/ChangeLog b/contrib/ChangeLog index a7c4f2f..f4184ee 100644 --- a/contrib/ChangeLog +++ b/contrib/ChangeLog @@ -1,3 +1,7 @@ +2022-08-18 Andrea Corallo <andrea.corallo@arm.com> + + * git-fetch-vendor.sh : Fix typo. + 2022-08-02 Martin Liska <mliska@suse.cz> * gcc-changelog/git_commit.py: Do not deduce changelog for root ChangeLog. diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e193ffa..0500118 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,246 @@ +2022-08-18 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.h + (enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS): + Add new register class "ISC_REGS". + * config/xtensa/constraints.md (c): Add new register constraint. + * config/xtensa/xtensa.md (define_constants): Remove "A11_REG". + (sibcall_internal, sibcall_value_internal): + Change to use the new register constraint, and remove two split + patterns for fixups that are no longer needed. + +2022-08-18 Maciej W. Rozycki <macro@embecosm.com> + + * config/riscv/riscv.md (*mov<GPR:mode><X:mode>cc): Fix output + pattern formatting. + +2022-08-18 Tim Lange <mail@tim-lange.me> + + PR analyzer/106181 + * doc/invoke.texi: Add Wanalyzer-imprecise-fp-arithmetic. + +2022-08-18 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-path.cc (path_range_query::path_range_query): Add + various constructors to take a path. + (path_range_query::~path_range_query): Remove m_alloced_ranger. + (path_range_query::range_on_path_entry): Adjust for m_ranger being + a reference. + (path_range_query::set_path): Rename to... + (path_range_query::reset_path): ...this and call compute_ranges. + (path_range_query::ssa_range_in_phi): Adjust for m_ranger + reference. + (path_range_query::range_defined_in_block): Same. + (path_range_query::compute_ranges_in_block): Same. + (path_range_query::adjust_for_non_null_uses): Same. + (path_range_query::compute_exit_dependencies): Use m_path instead + of argument. + (path_range_query::compute_ranges): Remove path argument. + (path_range_query::range_of_stmt): Adjust for m_ranger reference. + (path_range_query::compute_outgoing_relations): Same. + * gimple-range-path.h (class path_range_query): Add various + constructors. + Make compute_ranges and compute_exit_dependencies private. + Rename set_path to reset_path. + Make m_ranger a reference. + Remove m_alloced_ranger. + * tree-ssa-dom.cc (pass_dominator::execute): Adjust constructor to + path_range_query. + * tree-ssa-loop-ch.cc (entry_loop_condition_is_static): Take a + ranger and instantiate a new path_range_query every time. + (ch_base::copy_headers): Pass ranger instead of path_range_query. + * tree-ssa-threadbackward.cc (class back_threader): Remove m_solver. + (back_threader::~back_threader): Remove m_solver. + (back_threader::find_taken_edge_switch): Adjust for m_ranger + reference. + (back_threader::find_taken_edge_cond): Same. + (back_threader::dump): Remove m_solver. + (back_threader::back_threader): Move verify_marked_backedges + here from the path_range_query constructor. + * tree-ssa-threadedge.cc (hybrid_jt_simplifier::simplify): Move + some code from compute_ranges_from_state here. + (hybrid_jt_simplifier::compute_ranges_from_state): Rename... + (hybrid_jt_simplifier::compute_exit_dependencies): ...to this. + * tree-ssa-threadedge.h (class hybrid_jt_simplifier): Rename + compute_ranges_from_state to compute_exit_dependencies. + Remove m_path. + +2022-08-18 Richard Biener <rguenther@suse.de> + + PR middle-end/106617 + * match.pd ((a ? b : c) > d -> a ? (b > d) : (c > d)): Fix + guard, disable on GENERIC to not cause quadratic behavior + with the fold-const.cc implementation and the use of ! + +2022-08-18 Andrew Pinski <apinski@marvell.com> + + PR gcov-profile/106659 + * gcov-dump.cc (INCLUDE_VECTOR): Include vector.h with + INCLUDE_VECTOR. + +2022-08-18 konglin1 <lingling.kong@intel.com> + + * config/i386/i386-expand.cc (ix86_expand_sse_movcc): Handle vector + BFmode. + (ix86_expand_vector_init_duplicate): Support vector BFmode. + (ix86_expand_vector_init_one_nonzero): Ditto. + (ix86_expand_vector_init_one_var): Ditto. + (ix86_expand_vector_init_concat): Ditto. + (ix86_expand_vector_init_interleave): Ditto. + (ix86_expand_vector_init_general): Ditto. + (ix86_expand_vector_init): Ditto. + (ix86_expand_vector_set_var): Ditto. + (ix86_expand_vector_set): Ditto. + (ix86_expand_vector_extract): Ditto. + * config/i386/i386.cc (classify_argument): Add BF vector modes. + (function_arg_64): Ditto. + (ix86_gimplify_va_arg): Ditto. + (ix86_get_ssemov): Ditto. + * config/i386/i386.h (VALID_AVX256_REG_MODE): Add BF vector modes. + (VALID_AVX512F_REG_MODE): Ditto. + (host_detect_local_cpu): Ditto. + (VALID_SSE2_REG_MODE): Ditto. + * config/i386/i386.md: Add BF vector modes. + (MODE_SIZE): Ditto. + (ssemodesuffix): Add bf suffix for BF vector modes. + (ssevecmode): Ditto. + * config/i386/sse.md (VMOVE): Adjust for BF vector modes. + (VI12HFBF_AVX512VL): Ditto. + (V_256_512): Ditto. + (VF_AVX512HFBF16): Ditto. + (VF_AVX512BWHFBF16): Ditto. + (VIHFBF): Ditto. + (avx512): Ditto. + (VIHFBF_256): Ditto. + (VIHFBF_AVX512BW): Ditto. + (VI2F_256_512):Ditto. + (V8_128):Ditto. + (V16_256): Ditto. + (V32_512): Ditto. + (sseinsnmode): Ditto. + (sseconstm1): Ditto. + (sseintmodesuffix): New mode_attr. + (avx512fmaskmode): Ditto. + (avx512fmaskmodelower): Ditto. + (ssedoublevecmode): Ditto. + (ssehalfvecmode): Ditto. + (ssehalfvecmodelower): Ditto. + (ssescalarmode): Add vector BFmode mapping. + (ssescalarmodelower): Ditto. + (ssexmmmode): Ditto. + (ternlogsuffix): Ditto. + (ssescalarsize): Ditto. + (sseintprefix): Ditto. + (i128): Ditto. + (xtg_mode): Ditto. + (bcstscalarsuff): Ditto. + (<avx512>_blendm<mode>): New define_insn for BFmode. + (<avx512>_store<mode>_mask): Ditto. + (vcond_mask_<mode><avx512fmaskmodelower>): Ditto. + (vec_set<mode>_0): New define_insn for BF vector set. + (V8BFH_128): New mode_iterator for BFmode. + (avx512fp16_mov<mode>): Ditto. + (vec_set<mode>): New define_insn for BF vector set. + (@vec_extract_hi_<mode>): Ditto. + (@vec_extract_lo_<mode>): Ditto. + (vec_set_hi_<mode>): Ditto. + (vec_set_lo_<mode>): Ditto. + (*vec_extract<mode>_0): New define_insn_and_split for BF + vector extract. + (*vec_extract<mode>): New define_insn. + (VEC_EXTRACT_MODE): Add BF vector modes. + (PINSR_MODE): Add V8BF. + (sse2p4_1): Ditto. + (pinsr_evex_isa): Ditto. + (<sse2p4_1>_pinsr<ssemodesuffix>): Adjust to support + insert for V8BFmode. + (pbroadcast_evex_isa): Add BF vector modes. + (AVX2_VEC_DUP_MODE): Ditto. + (VEC_INIT_MODE): Ditto. + (VEC_INIT_HALF_MODE): Ditto. + (avx2_pbroadcast<mode>): Adjust to support BF vector mode + broadcast. + (avx2_pbroadcast<mode>_1): Ditto. + (<avx512>_vec_dup<mode>_1): Ditto. + (<mask_codefor><avx512>_vec_dup_gpr<mode><mask_name>): + Ditto. + +2022-08-18 Martin Liska <mliska@suse.cz> + + * configure: Regenerate. + +2022-08-18 Haochen Gui <guihaoc@gcc.gnu.org> + + PR target/103109 + * config/rs6000/rs6000.md (<u>maddditi4): New pattern for multiply-add. + (<u>madddi4_highpart): New. + (<u>madddi4_highpart_le): New. + +2022-08-18 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-path.cc + (path_range_query::compute_exit_dependencies): Use + gimple_range_ssa_names. + +2022-08-18 zhongjuzhe <juzhe.zhong@rivai.ai> + + * config/riscv/predicates.md: Adjust runtime invariant. + * config/riscv/riscv-modes.def (MAX_BITSIZE_MODE_ANY_MODE): New. + (NUM_POLY_INT_COEFFS): New. + * config/riscv/riscv-protos.h (riscv_initial_elimination_offset):Adjust + runtime invariant. + * config/riscv/riscv-sr.cc (riscv_remove_unneeded_save_restore_calls): + Adjust runtime invariant. + * config/riscv/riscv.cc (struct riscv_frame_info): Adjust runtime + invariant. + (enum riscv_microarchitecture_type): Ditto. + (riscv_valid_offset_p): Ditto. + (riscv_valid_lo_sum_p): Ditto. + (riscv_address_insns): Ditto. + (riscv_load_store_insns): Ditto. + (riscv_legitimize_move): Ditto. + (riscv_binary_cost): Ditto. + (riscv_rtx_costs): Ditto. + (riscv_output_move): Ditto. + (riscv_extend_comparands): Ditto. + (riscv_flatten_aggregate_field): Ditto. + (riscv_get_arg_info): Ditto. + (riscv_pass_by_reference): Ditto. + (riscv_elf_select_rtx_section): Ditto. + (riscv_stack_align): Ditto. + (riscv_compute_frame_info): Ditto. + (riscv_initial_elimination_offset): Ditto. + (riscv_set_return_address): Ditto. + (riscv_for_each_saved_reg): Ditto. + (riscv_first_stack_step): Ditto. + (riscv_expand_prologue): Ditto. + (riscv_expand_epilogue): Ditto. + (riscv_can_use_return_insn): Ditto. + (riscv_secondary_memory_needed): Ditto. + (riscv_hard_regno_nregs): Ditto. + (riscv_convert_vector_bits): New. + (riscv_option_override): Adjust runtime invariant. + (riscv_promote_function_mode): Ditto. + * config/riscv/riscv.h (POLY_SMALL_OPERAND_P): New. + (BITS_PER_RISCV_VECTOR): New. + (BYTES_PER_RISCV_VECTOR): New. + * config/riscv/riscv.md: Adjust runtime invariant. + +2022-08-18 Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr): + Get __tls_get_addr address through got table when disable plt. + +2022-08-18 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.cc (xtensa_expand_prologue): + Use an "addmi" machine instruction for updating the stack pointer + rather than addition/subtraction via hard register A9, if the amount + of change satisfies the literal value conditions of that instruction + when the CALL0 ABI is used. + (xtensa_expand_epilogue): Ditto. + And also inhibit the stack pointer addition of constant zero. + 2022-08-17 Roger Sayle <roger@nextmovesoftware.com> PR target/106640 diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 17147d2..918be36 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20220818 +20220819 diff --git a/gcc/analyzer/ChangeLog b/gcc/analyzer/ChangeLog index 482ab88..ae77b7e 100644 --- a/gcc/analyzer/ChangeLog +++ b/gcc/analyzer/ChangeLog @@ -1,3 +1,21 @@ +2022-08-18 Tim Lange <mail@tim-lange.me> + + PR analyzer/106181 + * analyzer.opt: Add Wanalyzer-imprecise-floating-point-arithmetic. + * region-model.cc (is_any_cast_p): Formatting. + (region_model::check_region_size): Ensure precondition. + (class imprecise_floating_point_arithmetic): New abstract + diagnostic class for all floating-point related warnings. + (class float_as_size_arg): Concrete diagnostic class to complain + about floating-point operands inside the size argument. + (class contains_floating_point_visitor): + New visitor to find floating-point operands inside svalues. + (region_model::check_dynamic_size_for_floats): New function. + (region_model::set_dynamic_extents): + Call to check_dynamic_size_for_floats. + * region-model.h (class region_model): + Add region_model::check_dynamic_size_for_floats. + 2022-08-16 Martin Liska <mliska@suse.cz> * region-model.cc: Fix -Winconsistent-missing-override clang diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index 678059b..a46ee46 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,13 @@ +2022-08-18 Harald Anlauf <anlauf@gmx.de> + + Revert: + 2022-07-31 Harald Anlauf <anlauf@gmx.de> + + PR fortran/77652 + * check.cc (gfc_check_associated): Make the rank check of POINTER + vs. TARGET match the allowed forms of pointer assignment for the + selected Fortran standard. + 2022-08-17 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org> Jakub Jelinek <jakub@redhat.com> diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index c7c5abb..fe374ba 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,60 @@ +2022-08-18 Joseph Myers <joseph@codesourcery.com> + + * gcc.dg/cpp/c11-warning-1.c, gcc.dg/cpp/c11-warning-2.c, + gcc.dg/cpp/c11-warning-3.c, gcc.dg/cpp/c11-warning-4.c, + gcc.dg/cpp/c2x-warning-1.c, gcc.dg/cpp/c2x-warning-2.c, + gcc.dg/cpp/gnu11-warning-1.c, gcc.dg/cpp/gnu11-warning-2.c, + gcc.dg/cpp/gnu11-warning-3.c, gcc.dg/cpp/gnu11-warning-4.c, + gcc.dg/cpp/gnu2x-warning-1.c, gcc.dg/cpp/gnu2x-warning-2.c: New + tests. + +2022-08-18 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * gcc.target/xtensa/sibcalls.c: Add a new test function to ensure + that registers for arguments (occupy from A2 to A7) and for indirect + sibcall (should be assigned to A8) neither conflict nor spill out. + +2022-08-18 Harald Anlauf <anlauf@gmx.de> + + Revert: + 2022-08-18 Harald Anlauf <anlauf@gmx.de> + + PR fortran/77652 + * gfortran.dg/associated_target_9a.f90: New test. + * gfortran.dg/associated_target_9b.f90: New test. + +2022-08-18 Tim Lange <mail@tim-lange.me> + + PR analyzer/106181 + * gcc.dg/analyzer/allocation-size-1.c: New test. + * gcc.dg/analyzer/imprecise-floating-point-1.c: New test. + * gcc.dg/analyzer/pr106181.c: New test. + +2022-08-18 Richard Biener <rguenther@suse.de> + + PR middle-end/106617 + * gcc.dg/pr106617.c: New testcase. + +2022-08-18 konglin1 <lingling.kong@intel.com> + + * g++.target/i386/vect-bfloat16-1.C: New test. + * gcc.target/i386/vect-bfloat16-1.c: New test. + * gcc.target/i386/vect-bfloat16-2a.c: New test. + * gcc.target/i386/vect-bfloat16-2b.c: New test. + * gcc.target/i386/vect-bfloat16-typecheck_1.c: New test. + * gcc.target/i386/vect-bfloat16-typecheck_2.c: New test. + +2022-08-18 Haochen Gui <guihaoc@gcc.gnu.org> + + PR target/103109 + * gcc.target/powerpc/pr103109.h: New. + * gcc.target/powerpc/pr103109-1.c: New. + * gcc.target/powerpc/pr103109-2.c: New. + +2022-08-18 Lulu Cheng <chenglulu@loongson.cn> + + * gcc.target/loongarch/tls-gd-noplt.c: New test. + 2022-08-17 Maciej W. Rozycki <macro@embecosm.com> * gcc.target/riscv/fmax-snan.c: Add `dg-require-effective-target diff --git a/libcpp/ChangeLog b/libcpp/ChangeLog index ac99688..6b51584 100644 --- a/libcpp/ChangeLog +++ b/libcpp/ChangeLog @@ -1,3 +1,13 @@ +2022-08-18 Joseph Myers <joseph@codesourcery.com> + + * include/cpplib.h (struct cpp_options): Add warning_directive. + * init.cc (struct lang_flags, lang_defaults): Add + warning_directive. + * directives.cc (DIRECTIVE_TABLE): Mark #warning as STDC2X not + EXTENSION. + (directive_diagnostics): Diagnose #warning with -Wc11-c2x-compat, + or with -pedantic for a standard not supporting #warning. + 2022-08-16 Tom Honermann <tom@honermann.net> PR c++/106423 |