diff options
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/ia64/ia64.h | 3 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/ia64/pr56540.c | 6 |
4 files changed, 18 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 957d152..5269f93 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2018-03-02 Jakub Jelinek <jakub@redhat.com> + PR target/56540 + * config/ia64/ia64.h (TARGET_CPU_CPP_BUILTINS): Predefine + __SIZEOF_{FPREG,FLOAT{80,128}}__ macros. + * predict.c (test_prediction_value_range): Use PROB_UNINITIALIZED instead of -1U in last predictors element's probability member. diff --git a/gcc/config/ia64/ia64.h b/gcc/config/ia64/ia64.h index 384bfe6..6ecc155 100644 --- a/gcc/config/ia64/ia64.h +++ b/gcc/config/ia64/ia64.h @@ -38,6 +38,9 @@ do { \ builtin_define("__itanium__"); \ if (TARGET_BIG_ENDIAN) \ builtin_define("__BIG_ENDIAN__"); \ + builtin_define("__SIZEOF_FPREG__=16"); \ + builtin_define("__SIZEOF_FLOAT80__=16");\ + builtin_define("__SIZEOF_FLOAT128__=16");\ } while (0) #ifndef SUBTARGET_EXTRA_SPECS diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 9490005..67eefea3 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-03-02 Jakub Jelinek <jakub@redhat.com> + + PR target/56540 + * gcc.target/ia64/pr56540.c: New test. + 2018-03-02 Will Schmidt <will_schmidt@vnet.ibm.com> * gcc.target/powerpc/altivec-7-be.c: Remove VSX content, allow diff --git a/gcc/testsuite/gcc.target/ia64/pr56540.c b/gcc/testsuite/gcc.target/ia64/pr56540.c new file mode 100644 index 0000000..adcd2db --- /dev/null +++ b/gcc/testsuite/gcc.target/ia64/pr56540.c @@ -0,0 +1,6 @@ +/* PR target/56540 */ +/* { dg-do compile } */ + +extern int a[__SIZEOF_FPREG__ != sizeof (__fpreg) ? -1 : 1]; +extern int b[__SIZEOF_FLOAT80__ != sizeof (__float80) ? -1 : 1]; +extern int c[__SIZEOF_FLOAT128__ != sizeof (__float128) ? -1 : 1]; |