aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--gcc/ChangeLog14
-rw-r--r--gcc/config/arm/arm-cpu-cdata.h67
-rw-r--r--gcc/config/arm/arm-cpu-data.h15
-rw-r--r--gcc/config/arm/arm-cpu.h3
-rw-r--r--gcc/config/arm/arm-cpus.in35
-rw-r--r--gcc/config/arm/arm-tables.opt9
-rw-r--r--gcc/config/arm/arm-tune.md3
-rw-r--r--gcc/config/arm/driver-arm.c2
-rw-r--r--gcc/doc/invoke.texi14
9 files changed, 154 insertions, 8 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 89678c2..866c7ff 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,17 @@
+2017-07-04 James Greenhalgh <james.greenhalgh@arm.com>
+
+ * config/arm/arm-cpus.in (cortex-a55): New.
+ (cortex-a75): Likewise.
+ (cortex-a75.cortex-a55): Likewise.
+ * config/arm/driver-arm.c (arm_cpu_table): Add cortex-a55 and
+ cortex-a75.
+ * doc/invoke.texi (-mcpu): Document cortex-a55 and cortex-a75.
+ * config/arm/arm-cpu-cdata.h: Regenerate.
+ * config/arm/arm-cpu-data.h: Regenerate.
+ * config/arm/arm-cpu.h: Regenerate.
+ * config/arm/arm-tables.opt: Regenerate.
+ * config/arm/arm-tune.md: Regenerate.
+
2017-07-04 Jan Hubicka <hubicka@ucw.cz>
* haifa-sched.c (sched_create_recovery_edges): Update profile.
diff --git a/gcc/config/arm/arm-cpu-cdata.h b/gcc/config/arm/arm-cpu-cdata.h
index 1cf1149..acd36d4 100644
--- a/gcc/config/arm/arm-cpu-cdata.h
+++ b/gcc/config/arm/arm-cpu-cdata.h
@@ -388,6 +388,34 @@ static const cpu_arch_extension cpu_opttab_cortexa73cortexa53[] = {
{ NULL, false, false, {isa_nobit}}
};
+static const cpu_arch_extension cpu_opttab_cortexa55[] = {
+ {
+ "crypto", false, false,
+ { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+ },
+ {
+ "nofp", true, false,
+ { ISA_ALL_FP, isa_nobit }
+ },
+ { NULL, false, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa75[] = {
+ {
+ "crypto", false, false,
+ { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+ },
+ { NULL, false, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa75cortexa55[] = {
+ {
+ "crypto", false, false,
+ { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+ },
+ { NULL, false, false, {isa_nobit}}
+};
+
static const cpu_arch_extension cpu_opttab_cortexm33[] = {
{
"nofp", true, false,
@@ -1624,6 +1652,45 @@ const cpu_option all_cores[] =
},
{
{
+ "cortex-a55",
+ cpu_opttab_cortexa55,
+ {
+ ISA_ARMv8_2a,
+ isa_bit_fp16,ISA_FP_ARMv8,ISA_NEON,
+ ISA_FP_ARMv8,ISA_NEON,
+ isa_nobit
+ }
+ },
+ TARGET_ARCH_armv8_2_a
+ },
+ {
+ {
+ "cortex-a75",
+ cpu_opttab_cortexa75,
+ {
+ ISA_ARMv8_2a,
+ isa_bit_fp16,ISA_FP_ARMv8,ISA_NEON,
+ ISA_FP_ARMv8,ISA_NEON,
+ isa_nobit
+ }
+ },
+ TARGET_ARCH_armv8_2_a
+ },
+ {
+ {
+ "cortex-a75.cortex-a55",
+ cpu_opttab_cortexa75cortexa55,
+ {
+ ISA_ARMv8_2a,
+ isa_bit_fp16,ISA_FP_ARMv8,ISA_NEON,
+ ISA_FP_ARMv8,ISA_NEON,
+ isa_nobit
+ }
+ },
+ TARGET_ARCH_armv8_2_a
+ },
+ {
+ {
"cortex-m23",
NULL,
{
diff --git a/gcc/config/arm/arm-cpu-data.h b/gcc/config/arm/arm-cpu-data.h
index d42021d..1e05522 100644
--- a/gcc/config/arm/arm-cpu-data.h
+++ b/gcc/config/arm/arm-cpu-data.h
@@ -552,6 +552,21 @@ static const cpu_tune all_tunes[] =
(TF_LDSCHED),
&arm_cortex_a73_tune
},
+ { /* cortex-a55. */
+ TARGET_CPU_cortexa53,
+ (TF_LDSCHED),
+ &arm_cortex_a53_tune
+ },
+ { /* cortex-a75. */
+ TARGET_CPU_cortexa57,
+ (TF_LDSCHED),
+ &arm_cortex_a73_tune
+ },
+ { /* cortex-a75.cortex-a55. */
+ TARGET_CPU_cortexa53,
+ (TF_LDSCHED),
+ &arm_cortex_a73_tune
+ },
{ /* cortex-m23. */
TARGET_CPU_cortexm23,
(TF_LDSCHED),
diff --git a/gcc/config/arm/arm-cpu.h b/gcc/config/arm/arm-cpu.h
index e27634c..8fda717 100644
--- a/gcc/config/arm/arm-cpu.h
+++ b/gcc/config/arm/arm-cpu.h
@@ -128,6 +128,9 @@ enum processor_type
TARGET_CPU_cortexa72cortexa53,
TARGET_CPU_cortexa73cortexa35,
TARGET_CPU_cortexa73cortexa53,
+ TARGET_CPU_cortexa55,
+ TARGET_CPU_cortexa75,
+ TARGET_CPU_cortexa75cortexa55,
TARGET_CPU_cortexm23,
TARGET_CPU_cortexm33,
TARGET_CPU_arm_none
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index 3231740..946d543 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -1206,7 +1206,6 @@ begin cpu xgene1
costs xgene1
end cpu xgene1
-
# V8 A-profile big.LITTLE implementations
begin cpu cortex-a57.cortex-a53
cname cortexa57cortexa53
@@ -1249,6 +1248,40 @@ begin cpu cortex-a73.cortex-a53
end cpu cortex-a73.cortex-a53
+# ARMv8.2 A-profile Architecture Processors
+begin cpu cortex-a55
+ cname cortexa55
+ tune for cortex-a53
+ tune flags LDSCHED
+ architecture armv8.2-a+fp16
+ fpu neon-fp-armv8
+ option crypto add FP_ARMv8 CRYPTO
+ option nofp remove ALL_FP
+ costs cortex_a53
+end cpu cortex-a55
+
+begin cpu cortex-a75
+ cname cortexa75
+ tune for cortex-a57
+ tune flags LDSCHED
+ architecture armv8.2-a+fp16
+ fpu neon-fp-armv8
+ option crypto add FP_ARMv8 CRYPTO
+ costs cortex_a73
+end cpu cortex-a75
+
+
+# ARMv8.2 A-profile ARM DynamIQ big.LITTLE implementations
+begin cpu cortex-a75.cortex-a55
+ cname cortexa75cortexa55
+ tune for cortex-a53
+ tune flags LDSCHED
+ architecture armv8.2-a+fp16
+ fpu neon-fp-armv8
+ option crypto add FP_ARMv8 CRYPTO
+ costs cortex_a73
+end cpu cortex-a75.cortex-a55
+
# V8 M-profile implementations.
begin cpu cortex-m23
cname cortexm23
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index 0f50c64..5e2df9d 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -343,6 +343,15 @@ EnumValue
Enum(processor_type) String(cortex-a73.cortex-a53) Value( TARGET_CPU_cortexa73cortexa53)
EnumValue
+Enum(processor_type) String(cortex-a55) Value( TARGET_CPU_cortexa55)
+
+EnumValue
+Enum(processor_type) String(cortex-a75) Value( TARGET_CPU_cortexa75)
+
+EnumValue
+Enum(processor_type) String(cortex-a75.cortex-a55) Value( TARGET_CPU_cortexa75cortexa55)
+
+EnumValue
Enum(processor_type) String(cortex-m23) Value( TARGET_CPU_cortexm23)
EnumValue
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index 6252d42..ba2c7d8 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -56,5 +56,6 @@
cortexa53,cortexa57,cortexa72,
cortexa73,exynosm1,xgene1,
cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,
- cortexa73cortexa53,cortexm23,cortexm33"
+ cortexa73cortexa53,cortexa55,cortexa75,
+ cortexa75cortexa55,cortexm23,cortexm33"
(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/config/arm/driver-arm.c b/gcc/config/arm/driver-arm.c
index b034f13..ab6879e 100644
--- a/gcc/config/arm/driver-arm.c
+++ b/gcc/config/arm/driver-arm.c
@@ -52,6 +52,8 @@ static struct vendor_cpu arm_cpu_table[] = {
{"0xd07", "armv8-a+crc", "cortex-a57"},
{"0xd08", "armv8-a+crc", "cortex-a72"},
{"0xd09", "armv8-a+crc", "cortex-a73"},
+ {"0xd05", "armv8.2-a+fp16", "cortex-a55"},
+ {"0xd0a", "armv8.2-a+fp16", "cortex-a75"},
{"0xc14", "armv7-r", "cortex-r4"},
{"0xc15", "armv7-r", "cortex-r5"},
{"0xc20", "armv6-m", "cortex-m0"},
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 04cecf9..3e5cee8 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -15519,9 +15519,10 @@ Permissible names are: @samp{arm2}, @samp{arm250},
@samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s},
@samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8},
@samp{cortex-a9}, @samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a17},
-@samp{cortex-a32}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57},
-@samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-r4},
-@samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8},
+@samp{cortex-a32}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55},
+@samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75},
+@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7},
+@samp{cortex-r8},
@samp{cortex-m33},
@samp{cortex-m23},
@samp{cortex-m7},
@@ -15544,7 +15545,8 @@ Additionally, this option can specify that GCC should tune the performance
of the code for a big.LITTLE system. Permissible names are:
@samp{cortex-a15.cortex-a7}, @samp{cortex-a17.cortex-a7},
@samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53},
-@samp{cortex-a72.cortex-a35}, @samp{cortex-a73.cortex-a53}.
+@samp{cortex-a72.cortex-a35}, @samp{cortex-a73.cortex-a53},
+@samp{cortex-a75.cortex-a55}.
@option{-mtune=generic-@var{arch}} specifies that GCC should tune the
performance for a blend of processors within architecture @var{arch}.
@@ -15605,8 +15607,8 @@ Disables the floating-point and SIMD instructions on
@samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7},
@samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a12},
@samp{cortex-a15}, @samp{cortex-a17}, @samp{cortex-a15.cortex-a7},
-@samp{cortex-a17.cortex-a7}, @samp{cortex-a32}, @samp{cortex-a35}
-and @samp{cortex-a53}.
+@samp{cortex-a17.cortex-a7}, @samp{cortex-a32}, @samp{cortex-a35},
+@samp{cortex-a53} and @samp{cortex-a55}.
@item +nofp.dp
Disables the double-precision component of the floating-point instructions
generated by cgit v1.1 at 2024-10-31 23:49:31 +0000