diff options
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 38 | ||||
| -rw-r--r-- | gcc/config/arm/thumb2.md | 65 |
3 files changed, 34 insertions, 77 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fb36575..213d3ec 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -37,6 +37,14 @@ (movsi_cbranchsi4 peepholes): Rewrite to generate a sequence of one subtract and one cbranch insn. + * config/arm/thumb2.md (thumb2_movdi, thumb2_movsf_soft_insn, + thumb2_movdf_soft_insn): Delete patterns. + * config/arm/arm.md (arm_pool_range, thumb2_pool_range, + arm_neg_pool_range, thumb2_neg_pool_range): New attributes. + (pool_range, neg_pool_range): Use them to define defaults. + (movdi, arm_movsf_soft_insn, arm_movdf_soft_insn): Define them + and allow for TARGET_32BIT. + 2010-08-02 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * config/arm/arm.c (COSTS_N_INSNS): Remove definition. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 097defd..baba8b0 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -172,8 +172,17 @@ ; reference the pool. ; NEG_POOL_RANGE is nonzero for insns that can reference a constant pool entry ; before its address. -(define_attr "pool_range" "" (const_int 0)) -(define_attr "neg_pool_range" "" (const_int 0)) +(define_attr "arm_pool_range" "" (const_int 0)) +(define_attr "thumb2_pool_range" "" (const_int 0)) +(define_attr "arm_neg_pool_range" "" (const_int 0)) +(define_attr "thumb2_neg_pool_range" "" (const_int 0)) + +(define_attr "pool_range" "" + (cond [(eq_attr "is_thumb" "yes") (attr "thumb2_pool_range")] + (attr "arm_pool_range"))) +(define_attr "neg_pool_range" "" + (cond [(eq_attr "is_thumb" "yes") (attr "thumb2_neg_pool_range")] + (attr "arm_neg_pool_range"))) ; An assembler sequence may clobber the condition codes without us knowing. ; If such an insn references the pool, then we have no way of knowing how, @@ -4775,7 +4784,7 @@ (define_insn "*arm_movdi" [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m") (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r"))] - "TARGET_ARM + "TARGET_32BIT && !(TARGET_HARD_FLOAT && (TARGET_MAVERICK || TARGET_VFP)) && !TARGET_IWMMXT && ( register_operand (operands[0], DImode) @@ -4793,8 +4802,10 @@ " [(set_attr "length" "8,12,16,8,8") (set_attr "type" "*,*,*,load2,store2") - (set_attr "pool_range" "*,*,*,1020,*") - (set_attr "neg_pool_range" "*,*,*,1008,*")] + (set_attr "arm_pool_range" "*,*,*,1020,*") + (set_attr "arm_neg_pool_range" "*,*,*,1008,*") + (set_attr "thumb2_pool_range" "*,*,*,4096,*") + (set_attr "thumb2_neg_pool_range" "*,*,*,0,*")] ) (define_split @@ -5695,7 +5706,7 @@ ;; Pattern to recognize insn generated default case above (define_insn "*movhi_insn_arch4" - [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r") + [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r") (match_operand:HI 1 "general_operand" "rI,K,r,m"))] "TARGET_ARM && arm_arch4 @@ -6019,7 +6030,7 @@ (define_insn "*arm_movsf_soft_insn" [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m") (match_operand:SF 1 "general_operand" "r,mE,r"))] - "TARGET_ARM + "TARGET_32BIT && TARGET_SOFT_FLOAT && (GET_CODE (operands[0]) != MEM || register_operand (operands[1], SFmode))" @@ -6027,11 +6038,11 @@ mov%?\\t%0, %1 ldr%?\\t%0, %1\\t%@ float str%?\\t%1, %0\\t%@ float" - [(set_attr "length" "4,4,4") - (set_attr "predicable" "yes") + [(set_attr "predicable" "yes") (set_attr "type" "*,load1,store1") (set_attr "pool_range" "*,4096,*") - (set_attr "neg_pool_range" "*,4084,*")] + (set_attr "arm_neg_pool_range" "*,4084,*") + (set_attr "thumb2_neg_pool_range" "*,0,*")] ) ;;; ??? This should have alternatives for constants. @@ -6123,7 +6134,7 @@ (define_insn "*movdf_soft_insn" [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=r,r,r,r,m") (match_operand:DF 1 "soft_df_operand" "rDa,Db,Dc,mF,r"))] - "TARGET_ARM && TARGET_SOFT_FLOAT + "TARGET_32BIT && TARGET_SOFT_FLOAT && ( register_operand (operands[0], DFmode) || register_operand (operands[1], DFmode))" "* @@ -6139,8 +6150,9 @@ " [(set_attr "length" "8,12,16,8,8") (set_attr "type" "*,*,*,load2,store2") - (set_attr "pool_range" "1020") - (set_attr "neg_pool_range" "1008")] + (set_attr "pool_range" "*,*,*,1020,*") + (set_attr "arm_neg_pool_range" "*,*,*,1008,*") + (set_attr "thumb2_neg_pool_range" "*,*,*,0,*")] ) ;;; ??? This should have alternatives for constants. diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 55bb41ff..46767d4 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -200,29 +200,6 @@ (set_attr "length" "10,8")] ) -(define_insn "*thumb2_movdi" - [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m") - (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r"))] - "TARGET_THUMB2 - && !(TARGET_HARD_FLOAT && (TARGET_MAVERICK || TARGET_VFP)) - && !TARGET_IWMMXT" - "* - switch (which_alternative) - { - case 0: - case 1: - case 2: - return \"#\"; - default: - return output_move_double (operands); - } - " - [(set_attr "length" "8,12,16,8,8") - (set_attr "type" "*,*,*,load2,store2") - (set_attr "pool_range" "*,*,*,4096,*") - (set_attr "neg_pool_range" "*,*,*,0,*")] -) - ;; We have two alternatives here for memory loads (and similarly for stores) ;; to reflect the fact that the permissible constant pool ranges differ ;; between ldr instructions taking low regs and ldr instructions taking high @@ -269,7 +246,7 @@ ;; Thumb-2 always has load/store halfword instructions, so we can avoid a lot ;; of the messiness associated with the ARM patterns. (define_insn "*thumb2_movhi_insn" - [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r") + [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r") (match_operand:HI 1 "general_operand" "rI,n,r,m"))] "TARGET_THUMB2" "@ @@ -283,46 +260,6 @@ (set_attr "neg_pool_range" "*,*,*,250")] ) -(define_insn "*thumb2_movsf_soft_insn" - [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m") - (match_operand:SF 1 "general_operand" "r,mE,r"))] - "TARGET_THUMB2 - && TARGET_SOFT_FLOAT - && (GET_CODE (operands[0]) != MEM - || register_operand (operands[1], SFmode))" - "@ - mov%?\\t%0, %1 - ldr%?\\t%0, %1\\t%@ float - str%?\\t%1, %0\\t%@ float" - [(set_attr "predicable" "yes") - (set_attr "type" "*,load1,store1") - (set_attr "pool_range" "*,4096,*") - (set_attr "neg_pool_range" "*,0,*")] -) - -(define_insn "*thumb2_movdf_soft_insn" - [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=r,r,r,r,m") - (match_operand:DF 1 "soft_df_operand" "rDa,Db,Dc,mF,r"))] - "TARGET_THUMB2 && TARGET_SOFT_FLOAT - && ( register_operand (operands[0], DFmode) - || register_operand (operands[1], DFmode))" - "* - switch (which_alternative) - { - case 0: - case 1: - case 2: - return \"#\"; - default: - return output_move_double (operands); - } - " - [(set_attr "length" "8,12,16,8,8") - (set_attr "type" "*,*,*,load2,store2") - (set_attr "pool_range" "*,*,*,1020,*") - (set_attr "neg_pool_range" "*,*,*,0,*")] -) - (define_insn "*thumb2_cmpsi_shiftsi" [(set (reg:CC CC_REGNUM) (compare:CC (match_operand:SI 0 "s_register_operand" "r") |