diff options
| -rw-r--r-- | ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/ChangeLog | 151 | ||||
| -rw-r--r-- | gcc/DATESTAMP | 2 | ||||
| -rw-r--r-- | gcc/ada/ChangeLog | 25 | ||||
| -rw-r--r-- | gcc/c-family/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/fortran/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 94 |
7 files changed, 290 insertions, 1 deletions
@@ -1,3 +1,7 @@ +2024-07-03 Prathamesh Kulkarni <prathameshk@nvidia.com> + + * MAINTAINERS: Update my email address and add myself to DCO. + 2024-07-01 Claudiu Zissulescu <claziss@gmail.com> * MAINTAINERS: Update claziss email address. diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 91ad053..6ea3039 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,154 @@ +2024-07-03 Jeff Law <jlaw@ventanamicro.com> + + * reorg.cc (relax_delay_slots): Do not optimize a conditional + jump around an unconditional jump/return in the presence of + a text section switch. + +2024-07-03 John David Anglin <danglin@gcc.gnu.org> + + Revert: + 2023-10-05 John David Anglin <danglin@gcc.gnu.org> + + * config/pa/pa32-linux.h (MALLOC_ABI_ALIGNMENT): Delete. + +2024-07-03 Palmer Dabbelt <palmer@rivosinc.com> + + * doc/invoke.texi: Describe -march behavior for dependent extensions on + RISC-V. + +2024-07-03 Gianluca Guida <gianluca@rivosinc.com> + Patrick O'Neill <patrick@rivosinc.com> + + * common/config/riscv/riscv-common.cc + (riscv_subset_list::to_string): Skip zabha when not supported by + the assembler. + * config.in: Regenerate. + * config/riscv/arch-canonicalize: Make zabha imply zaamo. + * config/riscv/iterators.md (amobh): Add iterator for amo + byte/halfword. + * config/riscv/riscv.opt: Add zabha. + * config/riscv/sync.md (atomic_<atomic_optab><mode>): Add + subword atomic op pattern. + (zabha_atomic_fetch_<atomic_optab><mode>): Add subword + atomic_fetch op pattern. + (lrsc_atomic_fetch_<atomic_optab><mode>): Prefer zabha over lrsc + for subword atomic ops. + (zabha_atomic_exchange<mode>): Add subword atomic exchange + pattern. + (lrsc_atomic_exchange<mode>): Prefer zabha over lrsc for subword + atomic exchange ops. + * configure: Regenerate. + * configure.ac: Add zabha assembler check. + * doc/sourcebuild.texi: Add zabha documentation. + +2024-07-03 Pan Li <pan2.li@intel.com> + + PR target/115763 + * config/riscv/vector.md (*pred_broadcast<mode>): Split into + zvfh and zvfhmin part. + (*pred_broadcast<mode>_zvfh): New define_insn for zvfh part. + (*pred_broadcast<mode>_zvfhmin): Ditto but for zvfhmin. + +2024-07-03 Pan Li <pan2.li@intel.com> + + * match.pd: Allow any otype is less than itype truncation. + +2024-07-03 Pan Li <pan2.li@intel.com> + + * tree-vect-patterns.cc (gimple_unsigned_integer_sat_trunc): Add + new decl generated by match. + (vect_recog_sat_trunc_pattern): Add new func impl to recog the + .SAT_TRUNC pattern. + +2024-07-03 Richard Biener <rguenther@suse.de> + + * tree-vect-slp.cc (vectorizable_slp_permutation_1): Remove + redundant dump. + +2024-07-03 Jennifer Schmitz <jschmitz@nvidia.com> + + * match.pd: Fold x/sqrt(x) to sqrt(x). + +2024-07-03 Alexandre Oliva <oliva@adacore.com> + + * dwarf2out.cc (modified_type_die): Follow name's debug type. + +2024-07-03 Alexandre Oliva <oliva@adacore.com> + + PR target/113719 + * config/i386/i386-options.cc + (ix86_override_options_after_change_1): Add opts and opts_set + parms, operate on them, after factoring out of... + (ix86_override_options_after_change): ... this. Restore calls + of ix86_default_align and ix86_recompute_optlev_based_flags. + (ix86_option_override_internal): Call the factored-out bits. + +2024-07-03 Kyrylo Tkachov <ktkachov@nvidia.com> + + PR target/115475 + * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): + Define __ARM_FEATURE_SVE_BF16 for TARGET_SVE_BF16. + +2024-07-03 Kyrylo Tkachov <ktkachov@nvidia.com> + + PR target/115457 + * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): + Define __ARM_FEATURE_BF16 for TARGET_BF16_FP. + +2024-07-03 Richard Biener <rguenther@suse.de> + + * tree-vect-slp.cc (bst_traits::hash): Handle NULL elements + in SLP_TREE_SCALAR_STMTS. + (vect_print_slp_tree): Likewise. + (vect_mark_slp_stmts): Likewise. + (vect_mark_slp_stmts_relevant): Likewise. + (vect_find_last_scalar_stmt_in_slp): Likewise. + (vect_bb_slp_mark_live_stmts): Likewise. + (vect_slp_prune_covered_roots): Likewise. + (vect_bb_partition_graph_r): Likewise. + (vect_remove_slp_scalar_calls): Likewise. + (vect_slp_gather_vectorized_scalar_stmts): Likewise. + (vect_bb_slp_scalar_cost): Likewise. + (vect_contains_pattern_stmt_p): Likewise. + (vect_slp_convert_to_external): Likewise. + (vect_find_first_scalar_stmt_in_slp): Likewise. + (vect_optimize_slp_pass::remove_redundant_permutations): Likewise. + (vect_slp_analyze_node_operations_1): Likewise. + (vect_schedule_slp_node): Likewise. + * tree-vect-stmts.cc (can_vectorize_live_stmts): Likewise. + (vectorizable_shift): Likewise. + * tree-vect-data-refs.cc (vect_slp_analyze_load_dependences): + Handle NULL elements in SLP_TREE_SCALAR_STMTS. + +2024-07-03 Georg-Johann Lay <avr@gjlay.de> + + PR target/98762 + * config/avr/avr.cc (avr_out_movqi_r_mr_reg_disp_tiny): Properly + restore the base register when it is partially clobbered. + +2024-07-03 Tamar Christina <tamar.christina@arm.com> + + PR tree-optimization/114932 + * tree-ssa-loop-ivopts.cc (constant_multiple_of): Use + aff_combination_constant_multiple_p instead. + +2024-07-03 Tamar Christina <tamar.christina@arm.com> + + PR tree-optimization/114932 + * tree-affine.cc (wide_int_constant_multiple_p): Support 0 and 0 being + multiples. + +2024-07-03 Richard Sandiford <richard.sandiford@arm.com> + + * df.h (DF_LR_DCE): New df_problem_id. + (df_lr_dce): New macro. + * df-core.cc (rest_of_handle_df_finish): Check for a null free_fun. + * df-problems.cc (df_lr_finalize): Split out fast DCE handling to... + (df_lr_dce_finalize): ...this new function. + (problem_LR_DCE): New df_problem. + (df_lr_add_problem): Register LR_DCE rather than LR itself. + * dce.cc (fast_dce): Clear df_lr_dce->solutions_dirty. + 2024-07-02 Pengxuan Zheng <quic_pzheng@quicinc.com> PR target/113859 diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index f8fa5e4..efaf824 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20240703 +20240704 diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog index 02db1fb..986adf3 100644 --- a/gcc/ada/ChangeLog +++ b/gcc/ada/ChangeLog @@ -1,3 +1,28 @@ +2024-07-03 Alexandre Oliva <oliva@adacore.com> + + * gcc-interface/misc.cc (gnat_get_array_descr_info): Only follow + TYPE_DEBUG_TYPE if TYPE_CAN_HAVE_DEBUG_TYPE_P. + * gcc-interface/utils.cc (sized_type_hash): New struct. + (sized_type_hasher): New struct. + (sized_type_hash_table): New variable. + (init_gnat_utils): Allocate it. + (destroy_gnat_utils): Release it. + (sized_type_hasher::equal): New. + (hash_sized_type): New. + (canonicalize_sized_type): New. + (make_type_from_size): Use it to cache packed variants. Fix + type reuse by combining biased_p and for_biased earlier. Hold + the combination in for_biased, adjusting later uses. + +2024-07-03 Alexandre Oliva <oliva@adacore.com> + + * gcc-interface/cuintp.cc (UI_To_gnu): Add mode that selects a + wide enough unsigned type. Fail if the constant exceeds the + representable numbers. + * gcc-interface/decl.cc (gnat_to_gnu_entity): Use it for + numerator and denominator of fixed-point types. In case of + failure, fall back to an indeterminate fraction. + 2024-07-02 Eric Botcazou <ebotcazou@adacore.com> * exp_ch4.adb (Expand_Concatenate): In the case where an operand diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog index f111c59..edfee4d 100644 --- a/gcc/c-family/ChangeLog +++ b/gcc/c-family/ChangeLog @@ -1,3 +1,10 @@ +2024-07-03 Lewis Hyatt <lhyatt@gmail.com> + + PR pch/115312 + * c-opts.cc (c_common_init): Call c_init_preprocess() before + c_finish_options() so that a parser is available to process any + includes specified on the command line. + 2024-06-25 Andrew Pinski <quic_apinski@quicinc.com> PR c++/115624 diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index d71616a..bc7a6f5 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,11 @@ +2024-07-03 Harald Anlauf <anlauf@gmx.de> + + PR fortran/115700 + * trans-stmt.cc (trans_associate_var): When the associate target + is an array-valued character variable, the length is known at entry + of the associate block. Move setting of string length of the + selector to the initialization part of the block. + 2024-07-01 Andrew Stubbs <ams@baylibre.com> Thomas Schwinge <thomas@codesourcery.com> diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 9aeec32..febb524 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,97 @@ +2024-07-03 Harald Anlauf <anlauf@gmx.de> + + PR fortran/115700 + * gfortran.dg/associate_69.f90: New test. + +2024-07-03 Gianluca Guida <gianluca@rivosinc.com> + Patrick O'Neill <patrick@rivosinc.com> + + * lib/target-supports.exp: Add zabha testsuite infra support. + * gcc.target/riscv/amo/inline-atomics-1.c: Remove zabha to continue to + test the lr/sc subword patterns. + * gcc.target/riscv/amo/inline-atomics-2.c: Ditto. + * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c: Ditto. + * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c: Ditto. + * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c: Ditto. + * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c: Ditto. + * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c: Ditto. + * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c: Ditto. + * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c: Ditto. + * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c: Ditto. + * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c: Ditto. + * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c: Ditto. + * gcc.target/riscv/amo/zabha-all-amo-ops-char-run.c: New test. + * gcc.target/riscv/amo/zabha-all-amo-ops-short-run.c: New test. + * gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c: New test. + * gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c: New test. + * gcc.target/riscv/amo/zabha-rvwmo-amo-add-char.c: New test. + * gcc.target/riscv/amo/zabha-rvwmo-amo-add-short.c: New test. + * gcc.target/riscv/amo/zabha-ztso-amo-add-char.c: New test. + * gcc.target/riscv/amo/zabha-ztso-amo-add-short.c: New test. + +2024-07-03 Luis Silva <Luis.Silva1@synopsys.com> + + * gcc.target/arc/pr9001184797.c: Fix compiler warnings. + +2024-07-03 Pan Li <pan2.li@intel.com> + + PR target/115763 + * gcc.target/riscv/rvv/base/scalar_move-5.c: Adjust asm check. + * gcc.target/riscv/rvv/base/scalar_move-6.c: Ditto. + * gcc.target/riscv/rvv/base/scalar_move-7.c: Ditto. + * gcc.target/riscv/rvv/base/scalar_move-8.c: Ditto. + * gcc.target/riscv/rvv/base/pr115763-1.c: New test. + * gcc.target/riscv/rvv/base/pr115763-2.c: New test. + +2024-07-03 Jennifer Schmitz <jschmitz@nvidia.com> + + * gcc.dg/tree-ssa/sqrt_div.c: New test. + +2024-07-03 Alexandre Oliva <oliva@adacore.com> + + * gnat.dg/bias1.adb: Count occurrences of -7.*DW_AT_GNU_bias. + +2024-07-03 Kyrylo Tkachov <ktkachov@nvidia.com> + + PR target/115475 + * gcc.target/aarch64/acle/bf16_sve_feature.c: New test. + +2024-07-03 Kyrylo Tkachov <ktkachov@nvidia.com> + + PR target/115457 + * gcc.target/aarch64/acle/bf16_feature.c: New test. + +2024-07-03 Georg-Johann Lay <avr@gjlay.de> + + PR target/98762 + * gcc.target/avr/torture/pr98762.c: New test. + +2024-07-03 liuhongt <hongtao.liu@intel.com> + + PR target/115748 + * gcc.target/i386/avx512-check.h: Move runtime check into a + separate function and guard it with target ("no-avx"). + +2024-07-03 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c: + Update vssubu check from vv to vx. + * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c: + Ditto. + * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c: + Ditto. + +2024-07-03 Richard Biener <rguenther@suse.de> + + PR tree-optimization/115764 + * gcc.dg/vect/bb-slp-76.c: New testcase. + +2024-07-03 Lewis Hyatt <lhyatt@gmail.com> + + PR pch/115312 + * g++.dg/pch/pr115312.C: New test. + * g++.dg/pch/pr115312.Hs: New test. + 2024-07-02 Pengxuan Zheng <quic_pzheng@quicinc.com> PR target/113859 |