diff options
509 files changed, 8674 insertions, 470 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 4322bff..984e906 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -792,7 +792,7 @@ Roger Sayle sayle <roger@nextmovesoftware.com> Tobias Schlüter tobi <tobias.schlueter@physik.uni-muenchen.de> Bernd Schmidt bernds <bernds_cb1@t-online.de> Will Schmidt willschm <will_schmidt@vnet.ibm.com> -Jennifer Schmitz jschmitz <jschmitz@nvidia.com> +Jennifer Schmitz jschmitz <jschmitz@mailbox.org> Stefan Schulze Frielinghaus stefansf <stefansf@linux.ibm.com> Andreas Schwab schwab <schwab@linux-m68k.org> Tilo Schwarz tiloschwarz <tilo@tilo-schwarz.de> @@ -973,7 +973,6 @@ Navid Rahimi <navidr@gcc.gnu.org> Rishi Raj <rishiraj45035@gmail.com> Trevor Saunders <tbsaunde+gcc@tbsaunde.org> Bill Schmidt <bill.schmidt@fastmail.com> -Jennifer Schmitz <jschmitz@nvidia.com> Nathaniel Shead <nathanieloshead@gmail.org> Nathan Sidwell <nathan@acm.org> Edward Smith-Rowland <esmithrowland@gmail.com> diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 59534a0..65ccd4b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,54 @@ +2025-10-26 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR target/122270 + * config/riscv/riscv-vector-builtins-bases.cc (vset::fold): Use the + unshare_expr for the statement that will be added seperately rather + the one which will be used for the replacement. + +2025-10-26 James K. Lowden <jklowden@cobolworx.com> + + * doc/install.texi: Add libxml2 dependency for COBOL + library. Clarify 128-bit numeric dependency. + +2025-10-26 Gerald Pfeifer <gerald@pfeifer.com> + + * poly-int.h: Change struct poly_int to class poly_int. + +2025-10-26 LIU Hao <lh_mouse@126.com> + + PR target/119079 + * config/i386/i386.md: Use `movsxd` to perform SI-to-DI extension in Intel + syntax. + +2025-10-26 Kuan-Lin Chen <rufus@andestech.com> + + * config/riscv/riscv.cc (riscv_legitimize_move): Append extend. + +2025-10-26 Osama Abdelkader <osama.abdelkader@gmail.com> + + * wide-int.h: Fix typo "accomodate" to "accommodate" in comment. + * value-range-storage.h: Likewise. + * tree-vectorizer.h (dr_set_safe_speculative_read_required): + Fix duplicate "the the" to "the" in comment. + +2025-10-25 Sam James <sam@gentoo.org> + + * doc/extend.texi (nocf_check): Fix syntax errors in example. + +2025-10-25 Jiahao Xu <xujiahao@loongson.cn> + + * config/loongarch/lasx.md (vec_extract<mode><lasxhalf>): New define_expand. + (vec_extract_lo_<mode>): New define_insn_and_split. + (vec_extract_hi_<mode>): New define_insn. + * config/loongarch/loongarch-protos.h (loongarch_check_vect_par_cnst_half) + New function prototype. + * config/loongarch/loongarch.cc (loongarch_split_reduction): + Implement TARGET_VECTORIZE_SPLIT_REDUCTION. + (loongarch_check_vect_par_cnst_half): New function. + * config/loongarch/predicates.md + (vect_par_cnst_low_half): New predicate. + (vect_par_cnst_high_half): New predicate. + 2025-10-24 Andrew MacLeod <amacleod@redhat.com> PR tree-optimization/114025 diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 8135eec..6e95eff 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20251025 +20251027 diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog index a732e94..e6dbda6 100644 --- a/gcc/ada/ChangeLog +++ b/gcc/ada/ChangeLog @@ -1,3 +1,9 @@ +2025-10-26 Eric Botcazou <ebotcazou@adacore.com> + + PR ada/13370 + * sem_prag.adb (Analyze_Pragma) <Pragma_Machine_Attribute>: Set the + Has_Delayed_Freeze flag if the argument is not a literal. + 2025-10-24 Eric Botcazou <ebotcazou@adacore.com> PR ada/80033 diff --git a/gcc/ada/freeze.adb b/gcc/ada/freeze.adb index 346789f..d8fdc30 100644 --- a/gcc/ada/freeze.adb +++ b/gcc/ada/freeze.adb @@ -5646,14 +5646,9 @@ package body Freeze is -- If the component is an access type with an allocator as default -- value, the designated type will be frozen by the corresponding - -- expression in init_proc. In order to place the freeze node for - -- the designated type before that for the current record type, - -- freeze it now. - - -- Same process if the component is an array of access types, - -- initialized with an aggregate. If the designated type is - -- private, it cannot contain allocators, and it is premature - -- to freeze the type, so we check for this as well. + -- expression in the initialization procedure. In order to place + -- the freeze node for the designated type ahead of that for the + -- current record type, freeze the designated type right now. elsif Is_Access_Type (Etype (Comp)) and then Present (Parent (Comp)) @@ -5665,17 +5660,16 @@ package body Freeze is declare Alloc : constant Node_Id := Unqualify (Expression (Parent (Comp))); - + Desig_Typ : constant Entity_Id := + Designated_Type (Etype (Comp)); begin if Nkind (Alloc) = N_Allocator then - -- If component is pointer to a class-wide type, freeze -- the specific type in the expression being allocated. -- The expression may be a subtype indication, in which -- case freeze the subtype mark. - if Is_Class_Wide_Type (Designated_Type (Etype (Comp))) - then + if Is_Class_Wide_Type (Desig_Typ) then if Is_Entity_Name (Expression (Alloc)) then Freeze_And_Append (Entity (Expression (Alloc)), N, Result); @@ -5686,21 +5680,24 @@ package body Freeze is (Entity (Subtype_Mark (Expression (Alloc))), N, Result); end if; - elsif Is_Itype (Designated_Type (Etype (Comp))) then + elsif Is_Itype (Desig_Typ) then Check_Itype (Etype (Comp)); else - Freeze_And_Append - (Designated_Type (Etype (Comp)), N, Result); + Freeze_And_Append (Desig_Typ, N, Result); end if; end if; end; + elsif Is_Access_Type (Etype (Comp)) and then Is_Itype (Designated_Type (Etype (Comp))) then Check_Itype (Etype (Comp)); - -- Freeze the designated type when initializing a component with - -- an aggregate in case the aggregate contains allocators. + -- Likewise if the component is an array of access types that is + -- initialized with an aggregate, in case the aggregate contains + -- allocators. But if the designated type is private, it cannot + -- contain allocators, and it is premature to freeze the type, + -- so we check for this as well. -- type T is ...; -- type T_Ptr is access all T; @@ -5712,13 +5709,15 @@ package body Freeze is elsif Is_Array_Type (Etype (Comp)) and then Is_Access_Type (Component_Type (Etype (Comp))) + and then Present (Parent (Comp)) + and then Nkind (Parent (Comp)) = N_Component_Declaration + and then Present (Expression (Parent (Comp))) + and then Nkind (Expression (Parent (Comp))) = N_Aggregate then declare - Comp_Par : constant Node_Id := Parent (Comp); Desig_Typ : constant Entity_Id := Designated_Type (Component_Type (Etype (Comp))); - begin -- The only case when this sort of freezing is not done is -- when the designated type is class-wide and the root type @@ -5740,12 +5739,7 @@ package body Freeze is then null; - elsif Is_Fully_Defined (Desig_Typ) - and then Present (Comp_Par) - and then Nkind (Comp_Par) = N_Component_Declaration - and then Present (Expression (Comp_Par)) - and then Nkind (Expression (Comp_Par)) = N_Aggregate - then + elsif Is_Fully_Defined (Desig_Typ) then Freeze_And_Append (Desig_Typ, N, Result); end if; end; diff --git a/gcc/ada/gcc-interface/utils.cc b/gcc/ada/gcc-interface/utils.cc index f176ca9..83b9e82 100644 --- a/gcc/ada/gcc-interface/utils.cc +++ b/gcc/ada/gcc-interface/utils.cc @@ -3226,6 +3226,9 @@ create_field_decl (tree name, tree type, tree record_type, tree size, tree pos, { tree field_decl = build_decl (input_location, FIELD_DECL, name, type); + /* The type must be frozen at this point. */ + gcc_assert (COMPLETE_TYPE_P (type)); + DECL_CONTEXT (field_decl) = record_type; TREE_READONLY (field_decl) = TYPE_READONLY (type); diff --git a/gcc/ada/sem_ch12.adb b/gcc/ada/sem_ch12.adb index 3575b04..24d276b 100644 --- a/gcc/ada/sem_ch12.adb +++ b/gcc/ada/sem_ch12.adb @@ -17639,6 +17639,8 @@ package body Sem_Ch12 is Set_Etype (N2, E); end if; + -- If the entity is global, save its type in the generic node + if Is_Global (E) then Set_Global_Type (N, N2); @@ -17659,12 +17661,24 @@ package body Sem_Ch12 is Set_Etype (N, Empty); end if; + -- If default actuals have been added to a generic instantiation + -- and they are global, save them in the generic node. + if Nkind (Parent (N)) in N_Generic_Instantiation and then N = Name (Parent (N)) then Save_Global_Defaults (Parent (N), Parent (N2)); end if; + if Nkind (Parent (N)) = N_Selected_Component + and then N = Selector_Name (Parent (N)) + and then Nkind (Parent (Parent (N))) in N_Generic_Instantiation + and then Parent (N) = Name (Parent (Parent (N))) + then + Save_Global_Defaults + (Parent (Parent (N)), Parent (Parent (N2))); + end if; + elsif Nkind (Parent (N)) = N_Selected_Component and then Nkind (Parent (N2)) = N_Expanded_Name then @@ -18488,12 +18502,13 @@ package body Sem_Ch12 is elsif Nkind (N) = N_Pragma then Save_References_In_Pragma (N); + -- Aspects + elsif Nkind (N) = N_Aspect_Specification then declare P : constant Node_Id := Parent (N); - Expr : Node_Id; - begin + begin if Permits_Aspect_Specifications (P) then -- The capture of global references within aspects @@ -18505,15 +18520,11 @@ package body Sem_Ch12 is if Requires_Delayed_Save (Original_Node (P)) then null; - -- Otherwise save all global references within the - -- aspects - - else - Expr := Expression (N); + -- Otherwise save all global references within the + -- expression of the aspect. - if Present (Expr) then - Save_Global_References (Expr); - end if; + elsif Present (Expression (N)) then + Save_Global_References (Expression (N)); end if; end if; end; @@ -18523,10 +18534,11 @@ package body Sem_Ch12 is elsif Nkind (N) = N_Implicit_Label_Declaration then null; + -- Other nodes + else Save_References_In_Descendants (N); end if; - end Save_References; --------------------- diff --git a/gcc/ada/sem_ch7.adb b/gcc/ada/sem_ch7.adb index 2002cc7..989e6bf 100644 --- a/gcc/ada/sem_ch7.adb +++ b/gcc/ada/sem_ch7.adb @@ -2266,7 +2266,32 @@ package body Sem_Ch7 is Next_Elmt (Op_Elmt_2); end loop; - -- Case 2: We have not found any explicit overriding and + -- Case 2: For a formal type, we need to explicitly check + -- whether a local subprogram hides from all visibility + -- the implicitly declared primitive, because subprograms + -- declared in a generic package specification are never + -- primitive for a formal type, even if they happen to + -- override an operation of the type (RM 3.2.3(7.d/2)). + + if Is_Generic_Type (E) then + declare + S : Entity_Id; + + begin + S := E; + while Present (S) loop + if Chars (S) = Chars (Parent_Subp) + and then Type_Conformant (Prim_Op, S) + then + goto Next_Primitive; + end if; + + Next_Entity (S); + end loop; + end; + end if; + + -- Case 3: We have not found any explicit overriding and -- hence we need to declare the operation (i.e., make it -- visible). diff --git a/gcc/ada/sem_prag.adb b/gcc/ada/sem_prag.adb index 28c5f17..6b38de0 100644 --- a/gcc/ada/sem_prag.adb +++ b/gcc/ada/sem_prag.adb @@ -21867,8 +21867,17 @@ package body Sem_Prag is if Rep_Item_Too_Late (Def_Id, N) then return; - else - Set_Has_Gigi_Rep_Item (Def_Id); + end if; + + Set_Has_Gigi_Rep_Item (Def_Id); + + -- The pragma is processed directly by the back end when Def_Id is + -- translated. If the argument is not a string literal, it may be + -- declared after Def_Id and before the pragma, which requires the + -- processing of Def_Id to be delayed for the back end. + + if Nkind (Get_Pragma_Arg (Arg2)) /= N_String_Literal then + Set_Has_Delayed_Freeze (Def_Id); end if; end Machine_Attribute; diff --git a/gcc/c-family/c-opts.cc b/gcc/c-family/c-opts.cc index 7bec3f1..b7dc8ce 100644 --- a/gcc/c-family/c-opts.cc +++ b/gcc/c-family/c-opts.cc @@ -230,7 +230,6 @@ c_common_init_options_struct (struct gcc_options *opts) /* By default, C99-like requirements for complex multiply and divide. */ opts->x_flag_complex_method = 2; - opts->x_flag_default_complex_method = opts->x_flag_complex_method; } /* Common initialization before calling option handlers. */ diff --git a/gcc/cobol/ChangeLog b/gcc/cobol/ChangeLog index e1595a0..d2cc68a 100644 --- a/gcc/cobol/ChangeLog +++ b/gcc/cobol/ChangeLog @@ -1,3 +1,7 @@ +2025-10-26 Eric Botcazou <ebotcazou@adacore.com> + + * Make-lang.in ($(srcdir)/cobol/token_names.h): Silence recipe. + 2025-10-23 Robert Dubner <rdubner@symas.com> * genapi.cc (parser_alphabet): Alphabet encoding. diff --git a/gcc/cobol/Make-lang.in b/gcc/cobol/Make-lang.in index 1f9995f..ed6b588 100644 --- a/gcc/cobol/Make-lang.in +++ b/gcc/cobol/Make-lang.in @@ -245,7 +245,7 @@ cobol/scan.o: cobol/scan.cc \ # Update token names if the generator script is installed # (by a developer) and there's been a change. $(srcdir)/cobol/token_names.h: cobol/parse.cc - if [ -f $@.gen ]; then \ + @if [ -f $@.gen ]; then \ $@.gen $(subst .cc,.h,$^) \ | diff -u $@ - \ | patch -t --set-time $@ ; \ diff --git a/gcc/common.opt b/gcc/common.opt index 9b8fbf6..92b0d4d 100644 --- a/gcc/common.opt +++ b/gcc/common.opt @@ -53,9 +53,6 @@ bool in_lto_p = false Variable enum incremental_link flag_incremental_link = INCREMENTAL_LINK_NONE -Variable -int flag_default_complex_method = 1 - ; Language specific warning pass for unused results. Variable bool flag_warn_unused_result = false diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index a34d2e3..96c183d 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -3128,6 +3128,20 @@ } [(set_attr "type" "mult")]) +(define_expand "abs<mode>2" + [(set (match_operand:V_INT 0 "register_operand") + (abs:V_INT (match_operand:V_INT 1 "register_operand")))] + "" + { + rtx vcc = gen_reg_rtx (DImode); + rtx zero = gcn_vec_constant (<MODE>mode, 0); + emit_insn (gen_vec_cmp<mode>di (vcc, gen_rtx_LT (VOIDmode, 0, 0), + operands[1], zero)); + emit_insn (gen_sub<mode>3_exec (operands[0], zero, operands[1], + operands[1], vcc)); + DONE; + }) + ;; }}} ;; {{{ FP binops - special cases diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 8a3e336..218377a 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -4982,7 +4982,7 @@ "TARGET_64BIT" "@ {cltq|cdqe} - movs{lq|x}\t{%1, %0|%0, %1}" + movs{lq|xd}\t{%1, %0|%0, %1}" [(set_attr "type" "imovx") (set_attr "mode" "DI") (set_attr "prefix_0f" "0") @@ -27859,7 +27859,7 @@ { output_asm_insn ("mov{<imodesuffix>}\t{%3, %<k>1|%<k>1, %3}", operands); output_asm_insn ("mov{<imodesuffix>}\t{%<k>1, %0|%0, %<k>1}", operands); - return "movs{lq|x}\t{%2, %1|%1, %2}"; + return "movs{lq|xd}\t{%2, %1|%1, %2}"; } [(set_attr "type" "multi") (set_attr "length" "24")]) diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index c782cac..5c2a9eb 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -4056,6 +4056,17 @@ loongarch_rtx_costs (rtx x, machine_mode mode, int outer_code, *total = loongarch_cost->int_mult_di; else *total = loongarch_cost->int_mult_si; + + /* Check for mul_widen. */ + if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND + && GET_CODE (XEXP (x, 1)) == SIGN_EXTEND) + || (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND + && GET_CODE (XEXP (x, 1)) == ZERO_EXTEND)) + { + *total += (set_src_cost (XEXP (XEXP (x, 0), 0), mode, speed) + + set_src_cost (XEXP (XEXP (x, 1), 0), mode, speed)); + return true; + } return false; case DIV: diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index a275a2d..be9a235 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -2523,6 +2523,38 @@ [(set_attr "type" "condmove") (set_attr "mode" "<GPR:MODE>")]) +(define_insn_and_split "both_non_zero" + [(set (match_operand:DI 0 "register_operand" "=r") + (and:DI (ne:DI (match_operand:DI 1 "register_operand" "r") + (const_int 0)) + (ne:DI (match_operand:DI 2 "register_operand" "r") + (const_int 0))))] + "TARGET_64BIT" + "#" + "&& true" + [(set (match_dup 0) + (ne:DI (match_dup 1) (const_int 0))) + (set (match_dup 0) + (if_then_else:DI (ne:DI (match_dup 2) (const_int 0)) + (match_dup 0) + (const_int 0)))]) + +(define_insn_and_split "both_non_zero_subreg" + [(set (match_operand:DI 0 "register_operand" "=r") + (and:DI (subreg:DI (ne:SI (match_operand:DI 1 "register_operand" "r") + (const_int 0)) 0) + (subreg:DI (ne:SI (match_operand:DI 2 "register_operand" "r") + (const_int 0)) 0)))] + "TARGET_64BIT" + "#" + "&& true" + [(set (match_dup 0) + (ne:DI (match_dup 1) (const_int 0))) + (set (match_dup 0) + (if_then_else:DI (ne:DI (match_dup 2) (const_int 0)) + (match_dup 0) + (const_int 0)))]) + ;; fsel copies the 3rd argument when the 1st is non-zero and the 2nd ;; argument if the 1st is zero. This means operand 2 and 3 are ;; inverted in the instruction. @@ -3041,6 +3073,16 @@ [(set_attr "type" "shift") (set_attr "mode" "SI")]) +(define_insn "sign_extend_ashift<GPR:mode><SHORT:mode>" + [(set (match_operand:GPR 0 "register_operand" "=r") + (ashift:GPR + (sign_extend:GPR (match_operand:SHORT 1 "register_operand" "r")) + (match_operand:SI 2 "const_uimm5_operand")))] + "(GET_MODE_BITSIZE (<SHORT:MODE>mode) + INTVAL (operands[2])) == 32" + "slli.w\t%0,%1,%2" + [(set_attr "type" "shift") + (set_attr "mode" "<GPR:MODE>")]) + (define_insn "*rotr<mode>3" [(set (match_operand:GPR 0 "register_operand" "=r,r") (rotatert:GPR (match_operand:GPR 1 "register_operand" "r,r") diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 59b71ed..697198f 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -1,4 +1,4 @@ -;); Machine description for RISC-V Bit Manipulation operations. +;; Machine description for RISC-V Bit Manipulation operations. ;; Copyright (C) 2021-2025 Free Software Foundation, Inc. ;; This file is part of GCC. @@ -237,19 +237,20 @@ [(set_attr "type" "bitmanip") (set_attr "mode" "<X:MODE>")]) -(define_insn_and_split "*<optab>_not_const<mode>" - [(set (match_operand:X 0 "register_operand" "=r") - (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r")) - (match_operand:X 2 "const_arith_operand" "I"))) - (clobber (match_scratch:X 3 "=&r"))] +(define_peephole2 + [(match_scratch:X 4 "r") + (set (match_operand:X 0 "register_operand") + (not:X (match_operand:X 1 "register_operand"))) + (set (match_operand:X 2 "register_operand") + (bitmanip_bitwise:X (match_dup 0) + (match_operand 3 "const_int_operand"))) + (match_dup 4)] "(TARGET_ZBB || TARGET_ZBKB) && !TARGET_ZCB - && !optimize_function_for_size_p (cfun)" - "#" - "&& reload_completed" - [(set (match_dup 3) (match_dup 2)) - (set (match_dup 0) (bitmanip_bitwise:X (not:X (match_dup 1)) (match_dup 3)))] - "" - [(set_attr "type" "bitmanip")]) + && !optimize_function_for_size_p (cfun) + && rtx_equal_p (operands[0], operands[2]) + && riscv_const_insns (operands[3], false) == 1" + [(set (match_dup 4) (match_dup 3)) + (set (match_dup 0) (bitmanip_bitwise:X (not:X (match_dup 1)) (match_dup 4)))]) ;; '(a >= 0) ? b : 0' is emitted branchless (from if-conversion). Without a ;; bit of extra help for combine (i.e., the below split), we end up emitting diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 013b1dd..cdb706a 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -834,7 +834,8 @@ extern bool th_print_operand_address (FILE *, machine_mode, rtx); extern bool strided_load_broadcast_p (void); extern bool riscv_prefer_agnostic_p (void); extern bool riscv_use_divmod_expander (void); -void riscv_init_cumulative_args (CUMULATIVE_ARGS *, const_tree, rtx, tree, int); +void riscv_init_cumulative_args (CUMULATIVE_ARGS *, const_tree, + rtx, tree, int, bool); extern bool riscv_option_valid_attribute_p (tree, tree, tree, int); extern bool diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 7e4d396..22b77cc 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -1793,12 +1793,13 @@ public: The fold routines expect the replacement statement to have the same lhs as the original call, so return the copy statement rather than the field update. */ - gassign *copy = gimple_build_assign (unshare_expr (f.lhs), rhs_tuple); + gassign *copy = gimple_build_assign (f.lhs, rhs_tuple); /* Get a reference to the individual vector. */ tree field = tuple_type_field (TREE_TYPE (f.lhs)); tree lhs_array - = build3 (COMPONENT_REF, TREE_TYPE (field), f.lhs, field, NULL_TREE); + = build3 (COMPONENT_REF, TREE_TYPE (field), unshare_expr (f.lhs), + field, NULL_TREE); tree lhs_vector = build4 (ARRAY_REF, TREE_TYPE (rhs_vector), lhs_array, index, NULL_TREE, NULL_TREE); gassign *update = gimple_build_assign (lhs_vector, rhs_vector); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index d5de76c..74701b7 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -740,6 +740,7 @@ static tree riscv_handle_fndecl_attribute (tree *, tree, tree, int, bool *); static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *); static tree riscv_handle_rvv_vector_bits_attribute (tree *, tree, tree, int, bool *); +static tree riscv_handle_rvv_vls_cc_attribute (tree *, tree, tree, int, bool *); /* Defining target-specific uses of __attribute__. */ static const attribute_spec riscv_gnu_attributes[] = @@ -763,6 +764,8 @@ static const attribute_spec riscv_gnu_attributes[] = standard vector calling convention variant. Syntax: __attribute__((riscv_vector_cc)). */ {"riscv_vector_cc", 0, 0, false, true, true, true, NULL, NULL}, + {"riscv_vls_cc", 0, 1, false, true, true, true, + riscv_handle_rvv_vls_cc_attribute, NULL}, /* This attribute is used to declare a new type, to appoint the exactly bits size of the type. For example: @@ -790,6 +793,8 @@ static const attribute_spec riscv_attributes[] = standard vector calling convention variant. Syntax: [[riscv::vector_cc]]. */ {"vector_cc", 0, 0, false, true, true, true, NULL, NULL}, + {"vls_cc", 0, 1, false, true, true, true, riscv_handle_rvv_vls_cc_attribute, + NULL}, /* This attribute is used to declare a new type, to appoint the exactly bits size of the type. For example: @@ -3723,6 +3728,12 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) riscv_vector::emit_vec_extract (result, v, gen_int_mode (index + i, Pmode)); + /* The low-part must be zero-extended when ELEN == 32 and + mode == 64. */ + if (num == 2 && i == 0) + emit_insn (gen_extend_insn (int_reg, result, mode, smode, + true)); + if (i == 1) { if (UNITS_PER_WORD < mode_size) @@ -5872,11 +5883,12 @@ typedef struct { floating-point registers. */ static int -riscv_flatten_aggregate_field (const_tree type, - riscv_aggregate_field fields[2], +riscv_flatten_aggregate_field (const_tree type, riscv_aggregate_field *fields, int n, HOST_WIDE_INT offset, - bool ignore_zero_width_bit_field_p) + bool ignore_zero_width_bit_field_p, + bool vls_p = false, unsigned abi_vlen = 0) { + int max_aggregate_field = vls_p ? 8 : 2; switch (TREE_CODE (type)) { case RECORD_TYPE: @@ -5903,9 +5915,9 @@ riscv_flatten_aggregate_field (const_tree type, else { HOST_WIDE_INT pos = offset + int_byte_position (f); - n = riscv_flatten_aggregate_field (TREE_TYPE (f), - fields, n, pos, - ignore_zero_width_bit_field_p); + n = riscv_flatten_aggregate_field ( + TREE_TYPE (f), fields, n, pos, ignore_zero_width_bit_field_p, + vls_p, abi_vlen); } if (n < 0) return -1; @@ -5915,13 +5927,14 @@ riscv_flatten_aggregate_field (const_tree type, case ARRAY_TYPE: { HOST_WIDE_INT n_elts; - riscv_aggregate_field subfields[2]; + riscv_aggregate_field subfields[8]; tree index = TYPE_DOMAIN (type); tree elt_size = TYPE_SIZE_UNIT (TREE_TYPE (type)); - int n_subfields = riscv_flatten_aggregate_field (TREE_TYPE (type), - subfields, 0, offset, - ignore_zero_width_bit_field_p); - + int n_subfields + = riscv_flatten_aggregate_field (TREE_TYPE (type), subfields, 0, + offset, + ignore_zero_width_bit_field_p, vls_p, + abi_vlen); /* Can't handle incomplete types nor sizes that are not fixed. */ if (n_subfields <= 0 || !COMPLETE_TYPE_P (type) @@ -5941,7 +5954,7 @@ riscv_flatten_aggregate_field (const_tree type, for (HOST_WIDE_INT i = 0; i < n_elts; i++) for (int j = 0; j < n_subfields; j++) { - if (n >= 2) + if (n >= max_aggregate_field) return -1; fields[n] = subfields[j]; @@ -5973,18 +5986,36 @@ riscv_flatten_aggregate_field (const_tree type, } default: - if (n < 2 - && ((SCALAR_FLOAT_TYPE_P (type) - && GET_MODE_SIZE (TYPE_MODE (type)).to_constant () <= UNITS_PER_FP_ARG) - || (INTEGRAL_TYPE_P (type) - && GET_MODE_SIZE (TYPE_MODE (type)).to_constant () <= UNITS_PER_WORD))) + poly_uint64 mode_size = GET_MODE_SIZE (TYPE_MODE (type)); + if (vls_p) { - fields[n].type = type; - fields[n].offset = offset; - return n + 1; + gcc_assert (abi_vlen != 0); + if (n < max_aggregate_field + && (VECTOR_TYPE_P (type) && mode_size.is_constant () + && (mode_size.to_constant () <= abi_vlen * 8))) + { + fields[n].type = type; + fields[n].offset = offset; + return n + 1; + } + else + return -1; } else - return -1; + { + if (n < max_aggregate_field + && ((SCALAR_FLOAT_TYPE_P (type) + && mode_size.to_constant () <= UNITS_PER_FP_ARG) + || (INTEGRAL_TYPE_P (type) + && mode_size.to_constant () <= UNITS_PER_WORD))) + { + fields[n].type = type; + fields[n].offset = offset; + return n + 1; + } + else + return -1; + } } } @@ -5993,14 +6024,16 @@ riscv_flatten_aggregate_field (const_tree type, static int riscv_flatten_aggregate_argument (const_tree type, - riscv_aggregate_field fields[2], - bool ignore_zero_width_bit_field_p) + riscv_aggregate_field *fields, + bool ignore_zero_width_bit_field_p, + bool vls_p = false, unsigned abi_vlen = 0) { if (!type || TREE_CODE (type) != RECORD_TYPE) return -1; return riscv_flatten_aggregate_field (type, fields, 0, 0, - ignore_zero_width_bit_field_p); + ignore_zero_width_bit_field_p, vls_p, + abi_vlen); } /* See whether TYPE is a record whose fields should be returned in one or @@ -6163,18 +6196,22 @@ riscv_pass_vls_aggregate_in_gpr (struct riscv_arg_info *info, machine_mode mode, return gen_rtx_PARALLEL (mode, gen_rtvec (1, x)); } +static const predefined_function_abi & +riscv_fntype_abi_1 (const_tree fntype, bool check_only); + /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE. For a library call, FNTYPE is 0. */ void riscv_init_cumulative_args (CUMULATIVE_ARGS *cum, const_tree fntype, - rtx, tree, int) + rtx, tree, int, bool check_only) { memset (cum, 0, sizeof (*cum)); if (fntype) - cum->variant_cc = (riscv_cc) fntype_abi (fntype).id (); + cum->variant_cc = + (riscv_cc) riscv_fntype_abi_1 (fntype, check_only).id (); else cum->variant_cc = RISCV_CC_BASE; } @@ -6197,7 +6234,7 @@ riscv_hard_regno_nregs (unsigned int regno, machine_mode mode); static rtx riscv_get_vector_arg (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum, - machine_mode mode, bool return_p) + machine_mode mode, bool return_p, bool vls_p = false) { gcc_assert (riscv_v_ext_mode_p (mode)); @@ -6233,8 +6270,9 @@ riscv_get_vector_arg (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum, int arg_reg_end = V_ARG_LAST - V_REG_FIRST; int aligned_reg_start = ROUND_UP (arg_reg_start, LMUL); - /* For scalable data and scalable tuple return value. */ - if (return_p) + /* For scalable data and scalable tuple return value. + For VLS CC, we may pass struct like tuple, so need defer the handling. */ + if (return_p && !vls_p) return gen_rtx_REG (mode, aligned_reg_start + V_REG_FIRST); /* Iterate through the USED_VRS array to find vector register groups that have @@ -6271,6 +6309,224 @@ riscv_get_vector_arg (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum, return NULL_RTX; } + +#define RISCV_ALL_VALID_ABI_VLEN(F) \ + F (32) \ + F (64) \ + F (128) \ + F (256) \ + F (512) \ + F (1024) \ + F (2048) \ + F (4096) \ + F (8192) \ + F (16384) + +/* Return true if CC is a variant of VLS CC. */ + +static bool +riscv_vls_cc_p (riscv_cc cc) +{ + switch (cc) + { +#define VLS_CC_ABI_VLEN_CASE(ABI_VLEN) \ + case RISCV_CC_VLS_V_##ABI_VLEN: + RISCV_ALL_VALID_ABI_VLEN (VLS_CC_ABI_VLEN_CASE) + +#undef VLS_CC_ABI_VLEN_CASE + return true; + default: + return false; + } +} + +/* Get ABI_VLEN from cc. */ + +static unsigned int +riscv_get_cc_abi_vlen (riscv_cc cc) +{ + switch (cc) + { +#define VLS_CC_ABI_VLEN_CASE(ABI_VLEN) \ + case RISCV_CC_VLS_V_##ABI_VLEN: \ + return ABI_VLEN; + RISCV_ALL_VALID_ABI_VLEN (VLS_CC_ABI_VLEN_CASE) + +#undef VLS_CC_ABI_VLEN_CASE + default: + gcc_unreachable (); + } +} + +/* Return true if ABI_VLEN is a valid for VLS_CC. */ + +static bool +riscv_valid_abi_vlen_vls_cc_p (unsigned abi_vlen) +{ + switch (abi_vlen) + { +#define VLS_CC_ABI_VLEN_CASE(ABI_VLEN) \ + case ABI_VLEN: + RISCV_ALL_VALID_ABI_VLEN (VLS_CC_ABI_VLEN_CASE) + +#undef VLS_CC_ABI_VLEN_CASE + return true; + default: + return false; + } +} + +static riscv_cc +riscv_get_riscv_cc_by_abi_vlen (unsigned abi_vlen) +{ + switch (abi_vlen) + { +#define VLS_CC_ABI_VLEN_CASE(ABI_VLEN) \ + case ABI_VLEN: \ + return RISCV_CC_VLS_V_##ABI_VLEN; + RISCV_ALL_VALID_ABI_VLEN (VLS_CC_ABI_VLEN_CASE) + +#undef VLS_CC_ABI_VLEN_CASE + default: + gcc_unreachable (); + } +} + +/* Get a VLS type has same size as MODE in ABI_VLEN, but element is always + in integer mode. */ + +static machine_mode +riscv_get_vls_container_type (machine_mode mode, unsigned abi_vlen) +{ + machine_mode element_mode = GET_MODE_INNER (mode); + unsigned int mode_size = GET_MODE_SIZE (mode).to_constant (); + unsigned int lmul = ROUND_UP (mode_size * 8, abi_vlen) / abi_vlen; + + /* Always use integer mode to pass to simplify the logic - we allow pass + unsupported vector type in vector register, e.g. float16x4_t even no vector + fp16 support. */ + switch (GET_MODE_SIZE (element_mode).to_constant ()) + { + case 1: + element_mode = QImode; + break; + case 2: + element_mode = HImode; + break; + case 4: + element_mode = SImode; + break; + case 8: + element_mode = DImode; + break; + default: + gcc_unreachable (); + } + + scalar_mode smode = as_a<scalar_mode> (element_mode); + return get_lmul_mode (smode, lmul).require (); +} + +/* Pass VLS type argument in vector argument register. */ + +static rtx +riscv_pass_vls_in_vr (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum, + machine_mode mode, bool return_p) +{ + gcc_assert (riscv_v_ext_vls_mode_p (mode)); + + unsigned int abi_vlen = riscv_get_cc_abi_vlen (cum->variant_cc); + unsigned int mode_size = GET_MODE_SIZE (mode).to_constant (); + unsigned int lmul = ROUND_UP (mode_size * 8, abi_vlen) / abi_vlen; + + /* Put into memory if it need more than 8 registers (> LMUL 8). */ + if (lmul > 8) + return NULL_RTX; + + machine_mode vla_mode = riscv_get_vls_container_type (mode, abi_vlen); + rtx reg = riscv_get_vector_arg (info, cum, vla_mode, + return_p, /* vls_p */ true); + + /* Can't get vector register to pass, pass by memory. */ + if (!reg) + return NULL_RTX; + + PUT_MODE (reg, mode); + + return reg; +} + +/* Pass aggregate with VLS type argument in vector argument registers. */ + +static rtx +riscv_pass_aggregate_in_vr (struct riscv_arg_info *info, + const CUMULATIVE_ARGS *cum, const_tree type, + bool return_p) +{ + riscv_aggregate_field fields[8]; + unsigned int abi_vlen = riscv_get_cc_abi_vlen (cum->variant_cc); + int i; + int n = riscv_flatten_aggregate_argument (type, fields, true, + /* vls_p */ true, abi_vlen); + + if (n == -1) + return NULL_RTX; + + /* Check all field has same size. */ + unsigned int mode_size + = GET_MODE_SIZE (TYPE_MODE (fields[0].type)).to_constant (); + for (int i = 1; i < n; i++) + if (GET_MODE_SIZE (TYPE_MODE (fields[i].type)).to_constant () != mode_size) + return NULL_RTX; /* Return NULL_RTX if we cannot find a suitable reg. */ + + /* Check total size is <= abi_vlen * 8, we use up to 8 vector register to + pass argument. */ + if (mode_size * 8 > abi_vlen) + return NULL_RTX; /* Return NULL_RTX if we cannot find a suitable reg. */ + + /* Backup cum->used_vrs since we will defer the update until + riscv_function_arg_advance. */ + CUMULATIVE_ARGS local_cum; + memcpy (&local_cum, cum, sizeof (local_cum)); + + unsigned num_vrs = 0; + + /* Allocate vector registers for the arguments. */ + rtx expr_list[8]; + for (i = 0; i < n; i++) + { + machine_mode mode = TYPE_MODE (fields[i].type); + machine_mode vla_mode = riscv_get_vls_container_type (mode, abi_vlen); + /* Use riscv_get_vector_arg with VLA type to simplify the calling + convention implementation. */ + rtx reg + = riscv_get_vector_arg (info, &local_cum, vla_mode, + return_p, /* vls_p */true); + + /* Can't get vector register to pass, pass by memory. */ + if (!reg) + return NULL_RTX; + + PUT_MODE (reg, mode); + + expr_list[i] + = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (fields[i].offset)); + + num_vrs += info->num_vrs; + + /* Set the corresponding register in USED_VRS to used status. */ + for (unsigned int i = 0; i < info->num_vrs; i++) + { + gcc_assert (!local_cum.used_vrs[info->vr_offset + i]); + local_cum.used_vrs[info->vr_offset + i] = true; + } + } + + info->num_vrs = num_vrs; + + return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (n, expr_list)); +} + /* Fill INFO with information about a single argument, and return an RTL pattern to pass or return the argument. Return NULL_RTX if argument cannot pass or return in registers, then the argument may be passed by reference or @@ -6363,7 +6619,17 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum, if (riscv_vector_type_p (type) && riscv_v_ext_mode_p (mode)) return riscv_get_vector_arg (info, cum, mode, return_p); - /* For vls mode aggregated in gpr. */ + if (riscv_vls_cc_p (cum->variant_cc)) + { + if (riscv_v_ext_vls_mode_p (mode)) + return riscv_pass_vls_in_vr (info, cum, mode, return_p); + + rtx ret = riscv_pass_aggregate_in_vr (info, cum, type, return_p); + if (ret) + return ret; + } + + /* For vls mode aggregated in gpr (for non-VLS-CC). */ if (riscv_v_ext_vls_mode_p (mode)) return riscv_pass_vls_aggregate_in_gpr (info, mode, gpr_base); } @@ -6420,7 +6686,8 @@ riscv_function_arg_advance (cumulative_args_t cum_v, cum->used_vrs[info.vr_offset + i] = true; } - if ((info.num_vrs > 0 || info.num_mrs > 0) && cum->variant_cc != RISCV_CC_V) + if ((info.num_vrs > 0 || info.num_mrs > 0) && cum->variant_cc != RISCV_CC_V + && !riscv_vls_cc_p (cum->variant_cc)) { error ("RVV type %qT cannot be passed to an unprototyped function", arg.type); @@ -6463,7 +6730,8 @@ riscv_function_value (const_tree ret_type, const_tree fn_decl_or_type, { const_tree fntype = TREE_CODE (fn_decl_or_type) == FUNCTION_DECL ? TREE_TYPE (fn_decl_or_type) : fn_decl_or_type; - riscv_init_cumulative_args (&args, fntype, NULL_RTX, NULL_TREE, 0); + riscv_init_cumulative_args (&args, fntype, NULL_RTX, NULL_TREE, 0, + /* check_only */true); } else memset (&args, 0, sizeof args); @@ -6532,14 +6800,20 @@ riscv_pass_by_reference (cumulative_args_t cum_v, const function_arg_info &arg) /* Implement TARGET_RETURN_IN_MEMORY. */ static bool -riscv_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED) +riscv_return_in_memory (const_tree type, const_tree fntype) { CUMULATIVE_ARGS args; + + if (fntype) + riscv_init_cumulative_args (&args, fntype, NULL_RTX, NULL_TREE, 0, + /* check_only */true); + else + /* The rules for returning in memory are the same as for passing the + first named argument by reference. */ + memset (&args, 0, sizeof args); + cumulative_args_t cum = pack_cumulative_args (&args); - /* The rules for returning in memory are the same as for passing the - first named argument by reference. */ - memset (&args, 0, sizeof args); function_arg_info arg (const_cast<tree> (type), /*named=*/true); return riscv_pass_by_reference (cum, arg); } @@ -6583,9 +6857,9 @@ riscv_setup_incoming_varargs (cumulative_args_t cum, /* Return the descriptor of the Standard Vector Calling Convention Variant. */ static const predefined_function_abi & -riscv_v_abi () +riscv_v_abi (riscv_cc abi) { - predefined_function_abi &v_abi = function_abis[RISCV_CC_V]; + predefined_function_abi &v_abi = function_abis[abi]; if (!v_abi.initialized_p ()) { HARD_REG_SET full_reg_clobbers @@ -6595,7 +6869,7 @@ riscv_v_abi () CLEAR_HARD_REG_BIT (full_reg_clobbers, regno); for (int regno = V_REG_FIRST + 24; regno <= V_REG_FIRST + 31; regno += 1) CLEAR_HARD_REG_BIT (full_reg_clobbers, regno); - v_abi.initialize (RISCV_CC_V, full_reg_clobbers); + v_abi.initialize (abi, full_reg_clobbers); } return v_abi; } @@ -6756,13 +7030,14 @@ riscv_validate_vector_type (const_tree type, const char *hint) RISC-V V registers. */ static bool -riscv_return_value_is_vector_type_p (const_tree fntype) +riscv_return_value_is_vector_type_p (const_tree fntype, bool check_only) { tree return_type = TREE_TYPE (fntype); if (riscv_vector_type_p (return_type)) { - riscv_validate_vector_type (return_type, "return type"); + if (!check_only) + riscv_validate_vector_type (return_type, "return type"); return true; } else @@ -6773,7 +7048,7 @@ riscv_return_value_is_vector_type_p (const_tree fntype) RISC-V V registers. */ static bool -riscv_arguments_is_vector_type_p (const_tree fntype) +riscv_arguments_is_vector_type_p (const_tree fntype, bool check_only) { for (tree chain = TYPE_ARG_TYPES (fntype); chain && chain != void_list_node; chain = TREE_CHAIN (chain)) @@ -6781,7 +7056,8 @@ riscv_arguments_is_vector_type_p (const_tree fntype) tree arg_type = TREE_VALUE (chain); if (riscv_vector_type_p (arg_type)) { - riscv_validate_vector_type (arg_type, "argument type"); + if (!check_only) + riscv_validate_vector_type (arg_type, "argument type"); return true; } } @@ -6792,14 +7068,15 @@ riscv_arguments_is_vector_type_p (const_tree fntype) /* Return true if FUNC is a riscv_vector_cc function. For more details please reference the below link. https://github.com/riscv-non-isa/riscv-c-api-doc/pull/67 */ + static bool -riscv_vector_cc_function_p (const_tree fntype) +riscv_vector_cc_function_p (const_tree fntype, bool check_only) { tree attr = TYPE_ATTRIBUTES (fntype); bool vector_cc_p = lookup_attribute ("vector_cc", attr) != NULL_TREE || lookup_attribute ("riscv_vector_cc", attr) != NULL_TREE; - if (vector_cc_p && !TARGET_VECTOR) + if (vector_cc_p && !TARGET_VECTOR && !check_only) error_at (input_location, "function attribute %qs requires the V ISA extension", "riscv_vector_cc"); @@ -6807,26 +7084,91 @@ riscv_vector_cc_function_p (const_tree fntype) return vector_cc_p; } -/* Implement TARGET_FNTYPE_ABI. */ +/* Return the riscv_cc value according to the attribute arguments. + If the attribute arguments are invalid, return RISCV_CC_UNKNOWN + and emit an error message. */ + +static riscv_cc +riscv_get_vls_cc_attr (const_tree args, bool check_only = false) +{ + /* Default ABI_VLEN is 128. */ + int abi_vlen = 128; + + if (args && TREE_CODE (args) == TREE_LIST) + { + tree vlen_arg = TREE_VALUE (args); + if (vlen_arg && TREE_CODE (vlen_arg) == INTEGER_CST) + abi_vlen = TREE_INT_CST_LOW (vlen_arg); + } + + if (!riscv_valid_abi_vlen_vls_cc_p (abi_vlen)) + { + error_at (input_location, + "unsupported ABI_VLEN value %d for %qs attribute;" + "ABI_VLEN must be in the range [32, 16384] and must be " + "a power of 2.", + "riscv_vls_cc", abi_vlen); + return RISCV_CC_UNKNOWN; + } + + return riscv_get_riscv_cc_by_abi_vlen (abi_vlen); +} + +/* Return true if FUNC is a riscv_vector_cc function. + For more details please reference the below link. + https://github.com/riscv-non-isa/riscv-c-api-doc/pull/67 */ +static riscv_cc +riscv_vls_cc_function_abi (const_tree fntype, bool check_only) +{ + tree attr = TYPE_ATTRIBUTES (fntype); + bool vls_cc_p = lookup_attribute ("vls_cc", attr) != NULL_TREE + || lookup_attribute ("riscv_vls_cc", attr) != NULL_TREE; + + if (!vls_cc_p) + return RISCV_CC_UNKNOWN; + + if (!TARGET_VECTOR && !check_only) + error_at (input_location, + "function attribute %qs requires the vector ISA extension", + "riscv_vls_cc"); + + tree args = TREE_VALUE (attr); + return riscv_get_vls_cc_attr (args); +} + +/* Implemention of TARGET_FNTYPE_ABI, but one extra parameter `check_only` + to suppress warning message. */ static const predefined_function_abi & -riscv_fntype_abi (const_tree fntype) +riscv_fntype_abi_1 (const_tree fntype, bool check_only) { /* Implement the vector calling convention. For more details please reference the below link. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/389 */ bool validate_v_abi_p = false; - validate_v_abi_p |= riscv_return_value_is_vector_type_p (fntype); - validate_v_abi_p |= riscv_arguments_is_vector_type_p (fntype); - validate_v_abi_p |= riscv_vector_cc_function_p (fntype); + validate_v_abi_p |= riscv_return_value_is_vector_type_p (fntype, check_only); + validate_v_abi_p |= riscv_arguments_is_vector_type_p (fntype, check_only); + validate_v_abi_p |= riscv_vector_cc_function_p (fntype, check_only); if (validate_v_abi_p) - return riscv_v_abi (); + return riscv_v_abi (RISCV_CC_V); + + riscv_cc abi = riscv_vls_cc_function_abi (fntype, check_only); + if (abi != RISCV_CC_UNKNOWN) + return riscv_v_abi (abi); return default_function_abi; } +/* Implement TARGET_FNTYPE_ABI. */ + +static const predefined_function_abi & +riscv_fntype_abi (const_tree fntype) +{ + return riscv_fntype_abi_1 (fntype, /* check_only */true); +} + /* Return riscv calling convention of call_insn. */ riscv_cc get_riscv_cc (const rtx use) @@ -6916,6 +7258,25 @@ riscv_handle_type_attribute (tree *node ATTRIBUTE_UNUSED, tree name, tree args, } static tree +riscv_handle_rvv_vls_cc_attribute (tree *node, tree name, tree args, + ATTRIBUTE_UNUSED int flags, + bool *no_add_attrs) +{ + bool vls_cc_p = is_attribute_p ("vls_cc", name) + || is_attribute_p ("riscv_vls_cc", name); + + if (!vls_cc_p) + return NULL_TREE; + + riscv_cc cc = riscv_get_vls_cc_attr (args); + + if (cc == RISCV_CC_UNKNOWN) + *no_add_attrs = true; + + return NULL_TREE; +} + +static tree riscv_handle_rvv_vector_bits_attribute (tree *node, tree name, tree args, ATTRIBUTE_UNUSED int flags, bool *no_add_attrs) @@ -11082,7 +11443,7 @@ riscv_asm_output_variant_cc (FILE *stream, const tree decl, const char *name) if (TREE_CODE (decl) == FUNCTION_DECL) { riscv_cc cc = (riscv_cc) fndecl_abi (decl).id (); - if (cc == RISCV_CC_V) + if (cc == RISCV_CC_V || riscv_vls_cc_p (cc)) { fprintf (stream, "\t.variant_cc\t"); assemble_name (stream, name); diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 9146571..a0ad75c 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -779,6 +779,17 @@ enum riscv_cc { RISCV_CC_BASE = 0, /* Base standard RISC-V ABI. */ RISCV_CC_V, /* For functions that pass or return values in V registers. */ + /* For functions that pass or return values in V registers. */ + RISCV_CC_VLS_V_32, + RISCV_CC_VLS_V_64, + RISCV_CC_VLS_V_128, + RISCV_CC_VLS_V_256, + RISCV_CC_VLS_V_512, + RISCV_CC_VLS_V_1024, + RISCV_CC_VLS_V_2048, + RISCV_CC_VLS_V_4096, + RISCV_CC_VLS_V_8192, + RISCV_CC_VLS_V_16384, RISCV_CC_UNKNOWN }; @@ -786,6 +797,8 @@ typedef struct { /* The calling convention that current function used. */ enum riscv_cc variant_cc; + unsigned int abi_vlen; + /* Number of integer registers used so far, up to MAX_ARGS_IN_REGISTERS. */ unsigned int num_gprs; @@ -809,7 +822,7 @@ extern enum riscv_cc get_riscv_cc (const rtx use); #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ riscv_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT), \ - (N_NAMED_ARGS) != -1) + (N_NAMED_ARGS) != -1, /* check_only */false) #define EPILOGUE_USES(REGNO) riscv_epilogue_uses (REGNO) diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index 374288d..4ba7f54 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -680,26 +680,15 @@ (set_attr "mode" "SI") (set_attr "length" "3")]) -(define_insn_and_split "one_cmplsi2" - [(set (match_operand:SI 0 "register_operand" "=a") - (not:SI (match_operand:SI 1 "register_operand" "r")))] +(define_expand "one_cmplsi2" + [(set (match_operand:SI 0 "register_operand") + (not:SI (match_operand:SI 1 "register_operand")))] "" - "#" - "&& can_create_pseudo_p ()" - [(set (match_dup 2) - (const_int -1)) - (set (match_dup 0) - (xor:SI (match_dup 1) - (match_dup 2)))] { - operands[2] = gen_reg_rtx (SImode); -} - [(set_attr "type" "arith") - (set_attr "mode" "SI") - (set (attr "length") - (if_then_else (match_test "TARGET_DENSITY") - (const_int 5) - (const_int 6)))]) + emit_insn (gen_xorsi3 (operands[0], operands[1], + force_reg (SImode, constm1_rtx))); + DONE; +}) (define_insn "negsf2" [(set (match_operand:SF 0 "register_operand" "=f") diff --git a/gcc/cp/parser.cc b/gcc/cp/parser.cc index 0917a16..5836122 100644 --- a/gcc/cp/parser.cc +++ b/gcc/cp/parser.cc @@ -32724,6 +32724,8 @@ cp_parser_label_declaration (cp_parser* parser) /* If we failed, stop. */ if (identifier == error_mark_node) break; + if (parser->omp_metadirective_state) + identifier = mangle_metadirective_region_label (parser, identifier); /* Declare it as a label. */ finish_label_decl (identifier); /* If the next token is a `;', stop. */ diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index fb117f5..882c082 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -6896,15 +6896,14 @@ compiler checks for @code{nocf_check} attribute mismatch and reports a warning in case of mismatch. @smallexample -@{ -int foo (void) __attribute__(nocf_check); -void (*foo1)(void) __attribute__(nocf_check); +int foo (void) __attribute__((nocf_check)); +void (*foo1)(void) __attribute__((nocf_check)); void (*foo2)(void); /* foo's address is assumed to be valid. */ int foo (void) - +@{ /* This call site is not checked for control-flow validity. */ (*foo1)(); diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi index 576b7ee..50cefa1 100644 --- a/gcc/doc/install.texi +++ b/gcc/doc/install.texi @@ -304,17 +304,14 @@ mdoc. GNU groff is required to convert them to PDF format. Conversion to HTML is done with mandoc, available at @uref{https://mandoc.bsd.lv}. +The COBOL runtime library. libgcobol, requires libxml2 2.9 or later. +It implements support for @code{XML PARSE}. + Because ISO COBOL defines strict requirements for numerical precision, -gcobol requires hardware with 128-bit computation instructions. This -requirement applies to both host and target. For integer and -fixed-point computation, gcobol uses -@deftp {Data type} __int128 -@end deftp -meaning @code{16 == sizeof(long long int)}. -For floating point, gcobol uses -@deftp {Data type} _Float128 -@end deftp -(On some architectures, GCC supports 128-bit floating point in software.) +gcobol computes with 128-bit operands. This requirement applies to +both host and target. For integers, gcobol requires the platform to +support the GCC @code{__int128} type. For floating point it uses +@code{_Float128} or similar. gcobol has so far been tested on two architectures only: x86_64 and aarch64 with little-endian encoding. diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index 7ca0cb0..385a62b 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,31 @@ +2025-10-26 Paul Thomas <pault@gcc.gnu.org> + + PR fortran/122290 + * decl.cc (variable_decl): Matching component initializer + expressions in PDT templates should be done with gfc_match_expr + to avoid reduction too early. If the expression type is unknown + copy the component typespec. + (gfc_get_pdt_instance): Change comment from a TODO to an + explanation. Insert parameter values in initializers. For + components that are not marked with PDT attributes, do the + full reduction for init expressions. + * primary.cc (gfc_match_actual_arglist): Convert PDT kind exprs + using the component initializer. + * resolve.cc (resolve_typebound_intrinsic_op): Preempt + gfc_check_new_interface for pdt_types as well as entities used + in submodules. + * simplify.cc (get_kind): Remove PDT kind conversion. + +2025-10-25 Harald Anlauf <anlauf@gmx.de> + + PR fortran/114023 + * trans-expr.cc (gfc_trans_pointer_assignment): Always set dtype + when remapping a pointer. For unlimited polymorphic LHS use + elem_len from RHS. + * trans-intrinsic.cc (gfc_conv_is_contiguous_expr): Extend inline + generated code for IS_CONTIGUOUS for pointer arguments to detect + when span differs from the element size. + 2025-10-24 Harald Anlauf <anlauf@gmx.de> PR fortran/122386 diff --git a/gcc/fortran/decl.cc b/gcc/fortran/decl.cc index 5da3c26..569786a 100644 --- a/gcc/fortran/decl.cc +++ b/gcc/fortran/decl.cc @@ -3101,7 +3101,16 @@ variable_decl (int elem) goto cleanup; } - m = gfc_match_init_expr (&initializer); + if (gfc_comp_struct (gfc_current_state ()) + && gfc_current_block ()->attr.pdt_template) + { + m = gfc_match_expr (&initializer); + if (initializer && initializer->ts.type == BT_UNKNOWN) + initializer->ts = current_ts; + } + else + m = gfc_match_init_expr (&initializer); + if (m == MATCH_NO) { gfc_error ("Expected an initialization expression at %C"); @@ -3179,7 +3188,7 @@ variable_decl (int elem) gfc_error ("BOZ literal constant at %L cannot appear as an " "initializer", &initializer->where); m = MATCH_ERROR; - goto cleanup; + goto cleanup; } param->value = gfc_copy_expr (initializer); } @@ -4035,8 +4044,8 @@ gfc_get_pdt_instance (gfc_actual_arglist *param_list, gfc_symbol **sym, gfc_insert_parameter_exprs (kind_expr, type_param_spec_list); ok = gfc_simplify_expr (kind_expr, 1); - /* Variable expressions seem to default to BT_PROCEDURE. - TODO find out why this is and fix it. */ + /* Variable expressions default to BT_PROCEDURE in the absence of an + initializer so allow for this. */ if (kind_expr->ts.type != BT_INTEGER && kind_expr->ts.type != BT_PROCEDURE) { @@ -4271,6 +4280,9 @@ gfc_get_pdt_instance (gfc_actual_arglist *param_list, gfc_symbol **sym, if (!c2->initializer && c1->initializer) c2->initializer = gfc_copy_expr (c1->initializer); + + if (c2->initializer) + gfc_insert_parameter_exprs (c2->initializer, type_param_spec_list); } /* Copy the array spec. */ @@ -4374,7 +4386,21 @@ gfc_get_pdt_instance (gfc_actual_arglist *param_list, gfc_symbol **sym, } else if (!(c2->attr.pdt_kind || c2->attr.pdt_len || c2->attr.pdt_string || c2->attr.pdt_array) && c1->initializer) - c2->initializer = gfc_copy_expr (c1->initializer); + { + c2->initializer = gfc_copy_expr (c1->initializer); + if (c2->initializer->ts.type == BT_UNKNOWN) + c2->initializer->ts = c2->ts; + gfc_insert_parameter_exprs (c2->initializer, type_param_spec_list); + /* The template initializers are parsed using gfc_match_expr rather + than gfc_match_init_expr. Apply the missing reduction to the + PDT instance initializers. */ + if (!gfc_reduce_init_expr (c2->initializer)) + { + gfc_free_expr (c2->initializer); + goto error_return; + } + gfc_simplify_expr (c2->initializer, 1); + } } if (alloc_seen) diff --git a/gcc/fortran/options.cc b/gcc/fortran/options.cc index 21839ef..59c6462 100644 --- a/gcc/fortran/options.cc +++ b/gcc/fortran/options.cc @@ -133,6 +133,7 @@ gfc_init_options_struct (struct gcc_options *opts) opts->frontend_set_flag_errno_math = true; opts->x_flag_associative_math = -1; opts->frontend_set_flag_associative_math = true; + opts->x_flag_complex_method = 1; } /* Get ready for options handling. Keep in sync with diff --git a/gcc/fortran/primary.cc b/gcc/fortran/primary.cc index cba4208..2d2c664 100644 --- a/gcc/fortran/primary.cc +++ b/gcc/fortran/primary.cc @@ -2071,6 +2071,23 @@ gfc_match_actual_arglist (int sub_flag, gfc_actual_arglist **argp, bool pdt) } } + /* PDT kind expressions are acceptable as initialization expressions. + However, intrinsics with a KIND argument reject them. Convert the + expression now by use of the component initializer. */ + if (tail->expr + && tail->expr->expr_type == EXPR_VARIABLE + && gfc_expr_attr (tail->expr).pdt_kind) + { + gfc_ref *ref; + gfc_expr *tmp = NULL; + for (ref = tail->expr->ref; ref; ref = ref->next) + if (!ref->next && ref->type == REF_COMPONENT + && ref->u.c.component->attr.pdt_kind + && ref->u.c.component->initializer) + tmp = gfc_copy_expr (ref->u.c.component->initializer); + if (tmp) + gfc_replace_expr (tail->expr, tmp); + } next: if (gfc_match_char (')') == MATCH_YES) diff --git a/gcc/fortran/resolve.cc b/gcc/fortran/resolve.cc index 1c49ccf..117a51c 100644 --- a/gcc/fortran/resolve.cc +++ b/gcc/fortran/resolve.cc @@ -16077,10 +16077,14 @@ resolve_typebound_intrinsic_op (gfc_symbol* derived, gfc_intrinsic_op op, /* Preempt 'gfc_check_new_interface' for submodules, where the mechanism for handling module procedures winds up resolving - operator interfaces twice and would otherwise cause an error. */ + operator interfaces twice and would otherwise cause an error. + Likewise, new instances of PDTs can cause the operator inter- + faces to be resolved multiple times. */ for (intr = derived->ns->op[op]; intr; intr = intr->next) if (intr->sym == target_proc - && target_proc->attr.used_in_submodule) + && (target_proc->attr.used_in_submodule + || derived->attr.pdt_type + || derived->attr.pdt_template)) return true; if (!gfc_check_new_interface (derived->ns->op[op], diff --git a/gcc/fortran/simplify.cc b/gcc/fortran/simplify.cc index 00b02f3..b25cd2c 100644 --- a/gcc/fortran/simplify.cc +++ b/gcc/fortran/simplify.cc @@ -120,26 +120,10 @@ static int get_kind (bt type, gfc_expr *k, const char *name, int default_kind) { int kind; - gfc_expr *tmp; if (k == NULL) return default_kind; - if (k->expr_type == EXPR_VARIABLE - && k->symtree->n.sym->ts.type == BT_DERIVED - && k->symtree->n.sym->ts.u.derived->attr.pdt_type) - { - gfc_ref *ref; - for (ref = k->ref; ref; ref = ref->next) - if (!ref->next && ref->type == REF_COMPONENT - && ref->u.c.component->attr.pdt_kind - && ref->u.c.component->initializer) - { - tmp = gfc_copy_expr (ref->u.c.component->initializer); - gfc_replace_expr (k, tmp); - } - } - if (k->expr_type != EXPR_CONSTANT) { gfc_error ("KIND parameter of %s at %L must be an initialization " diff --git a/gcc/fortran/trans-expr.cc b/gcc/fortran/trans-expr.cc index 21f256b..67b60c7 100644 --- a/gcc/fortran/trans-expr.cc +++ b/gcc/fortran/trans-expr.cc @@ -11344,21 +11344,33 @@ gfc_trans_pointer_assignment (gfc_expr * expr1, gfc_expr * expr2) int dim; gcc_assert (remap->u.ar.dimen == expr1->rank); + /* Always set dtype. */ + tree dtype = gfc_conv_descriptor_dtype (desc); + tmp = gfc_get_dtype (TREE_TYPE (desc)); + gfc_add_modify (&block, dtype, tmp); + + /* For unlimited polymorphic LHS use elem_len from RHS. */ + if (UNLIMITED_POLY (expr1) && expr2->ts.type != BT_CLASS) + { + tree elem_len; + tmp = TYPE_SIZE_UNIT (gfc_typenode_for_spec (&expr2->ts)); + elem_len = fold_convert (gfc_array_index_type, tmp); + elem_len = gfc_evaluate_now (elem_len, &block); + tmp = gfc_conv_descriptor_elem_len (desc); + gfc_add_modify (&block, tmp, + fold_convert (TREE_TYPE (tmp), elem_len)); + } + if (rank_remap) { /* Do rank remapping. We already have the RHS's descriptor converted in rse and now have to build the correct LHS descriptor for it. */ - tree dtype, data, span; + tree data, span; tree offs, stride; tree lbound, ubound; - /* Set dtype. */ - dtype = gfc_conv_descriptor_dtype (desc); - tmp = gfc_get_dtype (TREE_TYPE (desc)); - gfc_add_modify (&block, dtype, tmp); - /* Copy data pointer. */ data = gfc_conv_descriptor_data_get (rse.expr); gfc_conv_descriptor_data_set (&block, desc, data); diff --git a/gcc/fortran/trans-intrinsic.cc b/gcc/fortran/trans-intrinsic.cc index 05017d0..89a03d8 100644 --- a/gcc/fortran/trans-intrinsic.cc +++ b/gcc/fortran/trans-intrinsic.cc @@ -2316,10 +2316,14 @@ gfc_conv_is_contiguous_expr (gfc_se *se, gfc_expr *arg) int i; tree fncall0; gfc_array_spec *as; + gfc_symbol *sym = NULL; if (arg->ts.type == BT_CLASS) gfc_add_class_array_ref (arg); + if (arg->expr_type == EXPR_VARIABLE) + sym = arg->symtree->n.sym; + ss = gfc_walk_expr (arg); gcc_assert (ss != gfc_ss_terminator); gfc_init_se (&argse, NULL); @@ -2342,7 +2346,7 @@ gfc_conv_is_contiguous_expr (gfc_se *se, gfc_expr *arg) fncall0 = build_call_expr_loc (input_location, gfor_fndecl_is_contiguous0, 1, desc); se->expr = fncall0; - se->expr = convert (logical_type_node, se->expr); + se->expr = convert (boolean_type_node, se->expr); } else { @@ -2374,6 +2378,22 @@ gfc_conv_is_contiguous_expr (gfc_se *se, gfc_expr *arg) } se->expr = cond; } + + /* A pointer that does not have the CONTIGUOUS attribute needs to be checked + if it points to an array whose span differs from the element size. */ + if (as && sym && IS_POINTER(sym) && !sym->attr.contiguous) + { + tree span = gfc_conv_descriptor_span_get (desc); + tmp = fold_convert (TREE_TYPE (span), + gfc_conv_descriptor_elem_len (desc)); + cond = fold_build2_loc (input_location, EQ_EXPR, boolean_type_node, + span, tmp); + se->expr = fold_build2_loc (input_location, TRUTH_ANDIF_EXPR, + boolean_type_node, cond, + convert (boolean_type_node, se->expr)); + } + + gfc_free_ss_chain (ss); } diff --git a/gcc/fortran/trans-stmt.cc b/gcc/fortran/trans-stmt.cc index f25335d..0e82d2a 100644 --- a/gcc/fortran/trans-stmt.cc +++ b/gcc/fortran/trans-stmt.cc @@ -2092,6 +2092,22 @@ trans_associate_var (gfc_symbol *sym, gfc_wrapped_block *block) gfc_free_expr (expr1); gfc_free_expr (expr2); } + /* PDT array and string components are separately allocated for each element + of a PDT array. Therefore, there is no choice but to copy in and copy out + the target expression. */ + else if (e && is_subref_array (e) + && (gfc_expr_attr (e).pdt_array || gfc_expr_attr (e).pdt_string)) + { + gfc_se init; + gcc_assert (GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (sym->backend_decl))); + gfc_init_se (&init, NULL); + gfc_conv_subref_array_arg (&init, e, false, INTENT_INOUT, + sym && sym->attr.pointer); + init.expr = build_fold_indirect_ref_loc (input_location, init.expr); + gfc_add_modify (&init.pre, sym->backend_decl, init.expr); + gfc_add_init_cleanup (block, gfc_finish_block (&init.pre), + gfc_finish_block (&init.post)); + } else if ((sym->attr.dimension || sym->attr.codimension) && !class_target && (sym->as->type == AS_DEFERRED || sym->assoc->variable)) { diff --git a/gcc/function-abi.h b/gcc/function-abi.h index 6cb552f..338f0e1 100644 --- a/gcc/function-abi.h +++ b/gcc/function-abi.h @@ -28,7 +28,7 @@ along with GCC; see the file COPYING3. If not see NUM_ABI_IDS is the maximum number of such ABIs that GCC can handle at once. A bitfield with this number of bits can represent any combinaion of the supported ABIs. */ -const size_t NUM_ABI_IDS = 8; +const size_t NUM_ABI_IDS = 12; /* Information about one of the target's predefined ABIs. */ class predefined_function_abi diff --git a/gcc/go/go-lang.cc b/gcc/go/go-lang.cc index 0c9c9ce..0222b8a 100644 --- a/gcc/go/go-lang.cc +++ b/gcc/go/go-lang.cc @@ -173,7 +173,6 @@ go_langhook_init_options_struct (struct gcc_options *opts) /* Default to avoiding range issues for complex multiply and divide. */ opts->x_flag_complex_method = 2; - opts->x_flag_default_complex_method = opts->x_flag_complex_method; /* The builtin math functions should not set errno. */ opts->x_flag_errno_math = 0; diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc index 3dcb1be..97ef09a 100644 --- a/gcc/ifcvt.cc +++ b/gcc/ifcvt.cc @@ -1289,13 +1289,13 @@ noce_try_sign_bit_splat (struct noce_if_info *if_info) bool speed_p = optimize_insn_for_speed_p (); if (exact_log2 (val_a + 1) >= 0 && (rtx_cost (shift_right, mode, SET, 1, speed_p) - <= rtx_cost (and_form, mode, SET, 1, speed_p))) + < rtx_cost (and_form, mode, SET, 1, speed_p))) temp = expand_simple_binop (mode, LSHIFTRT, temp, GEN_INT (rshift_count), if_info->x, false, OPTAB_WIDEN); else if (exact_log2 (~val_a + 1) >= 0 && (rtx_cost (shift_left, mode, SET, 1, speed_p) - <= rtx_cost (and_form, mode, SET, 1, speed_p))) + < rtx_cost (and_form, mode, SET, 1, speed_p))) temp = expand_simple_binop (mode, ASHIFT, temp, GEN_INT (ctz_hwi (val_a)), if_info->x, false, OPTAB_WIDEN); @@ -1341,13 +1341,13 @@ noce_try_sign_bit_splat (struct noce_if_info *if_info) bool speed_p = optimize_insn_for_speed_p (); if (exact_log2 (val_b + 1) >= 0 && (rtx_cost (shift_right, mode, SET, 1, speed_p) - <= rtx_cost (and_form, mode, SET, 1, speed_p))) + < rtx_cost (and_form, mode, SET, 1, speed_p))) temp = expand_simple_binop (mode, LSHIFTRT, temp, GEN_INT (rshift_count), if_info->x, false, OPTAB_WIDEN); else if (exact_log2 (~val_b + 1) >= 0 && (rtx_cost (shift_left, mode, SET, 1, speed_p) - <= rtx_cost (and_form, mode, SET, 1, speed_p))) + < rtx_cost (and_form, mode, SET, 1, speed_p))) temp = expand_simple_binop (mode, ASHIFT, temp, GEN_INT (ctz_hwi (val_b)), if_info->x, false, OPTAB_WIDEN); diff --git a/gcc/jit/ChangeLog b/gcc/jit/ChangeLog index f33f18a..9bbc62f 100644 --- a/gcc/jit/ChangeLog +++ b/gcc/jit/ChangeLog @@ -1,3 +1,9 @@ +2025-10-26 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> + + * jit-recording.cc (recording::array_type::make_debug_string, + recording::array_type::write_reproducer): Use PRIu64 format + specifier for uint64_t. + 2025-10-22 Antoni Boucher <bouanto@zoho.com> * docs/topics/types.rst: Document new types. diff --git a/gcc/jit/jit-recording.cc b/gcc/jit/jit-recording.cc index 6816a71..5c641f6 100644 --- a/gcc/jit/jit-recording.cc +++ b/gcc/jit/jit-recording.cc @@ -3430,7 +3430,7 @@ recording::string * recording::array_type::make_debug_string () { return string::from_printf (m_ctxt, - "%s[%ld]", + "%s[%" PRIu64 "]", m_element_type->get_debug_string (), m_num_elements); } @@ -3446,7 +3446,7 @@ recording::array_type::write_reproducer (reproducer &r) " gcc_jit_context_new_array_type_u64 (%s,\n" " %s, /* gcc_jit_location *loc */\n" " %s, /* gcc_jit_type *element_type */\n" - " %li); /* int num_elements */\n", + " %" PRIu64 "); /* int num_elements */\n", id, r.get_identifier (get_context ()), r.get_identifier (m_loc), diff --git a/gcc/lto/lto-lang.cc b/gcc/lto/lto-lang.cc index e41b548..3e71a8f 100644 --- a/gcc/lto/lto-lang.cc +++ b/gcc/lto/lto-lang.cc @@ -841,7 +841,6 @@ lto_init_options_struct (struct gcc_options *opts) safe choice. This will pessimize Fortran code with LTO unless people specify a complex method manually or use -ffast-math. */ opts->x_flag_complex_method = 2; - opts->x_flag_default_complex_method = opts->x_flag_complex_method; } /* Handle command-line option SCODE. If the option takes an argument, it is diff --git a/gcc/opts.cc b/gcc/opts.cc index 21ac6b5..ceb1e0f 100644 --- a/gcc/opts.cc +++ b/gcc/opts.cc @@ -454,6 +454,9 @@ init_options_struct (struct gcc_options *opts, struct gcc_options *opts_set) /* Some targets have ABI-specified unwind tables. */ opts->x_flag_unwind_tables = targetm_common.unwind_tables_default; + /* Languages not explicitly specifying a default get fortran rules. */ + opts->x_flag_complex_method = 1; + /* Some targets have other target-specific initialization. */ targetm_common.option_init_struct (opts); } @@ -1393,10 +1396,6 @@ finish_options (struct gcc_options *opts, struct gcc_options *opts_set, || opts->x_flag_peel_loops || opts->x_optimize >= 3); - /* Use a frontend provided default for the complex eval method. */ - if (!opts_set->x_flag_complex_method) - opts->x_flag_complex_method = opts->x_flag_default_complex_method; - /* Use -fvect-cost-model=cheap instead of -fvect-cost-mode=very-cheap by default with explicit -ftree-{loop,slp}-vectorize. */ if (opts->x_optimize == 2 diff --git a/gcc/poly-int.h b/gcc/poly-int.h index 77f7875..d99f63b 100644 --- a/gcc/poly-int.h +++ b/gcc/poly-int.h @@ -374,7 +374,7 @@ template<> struct poly_int_fullness<true> { using type = poly_int_full; }; /* A class containing polynomial integers. The polynomial has N coefficients of type C, and N - 1 indeterminates. */ template<unsigned int N, typename C> -struct poly_int +class poly_int { public: poly_int () = default; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 4b9bd57..844176e 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,36 @@ +2025-10-26 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR target/122270 + * gcc.target/riscv/rvv/base/pr122270-1.c: New test. + +2025-10-26 Kuan-Lin Chen <rufus@andestech.com> + + * gcc.target/riscv/rvv/autovec/pr111391-2.c: Add expected asm. + +2025-10-26 Eric Botcazou <ebotcazou@adacore.com> + + * gnat.dg/machine_attr3.ads, gnat.dg/machine_attr3.adb: New test. + +2025-10-26 Paul Thomas <pault@gcc.gnu.org> + + PR fortran/122290 + * gfortran.dg/pdt_60.f03: New test. + +2025-10-26 Alexandre Oliva <oliva@adacore.com> + + PR target/121599 + * gcc.target/aarch64/sve2/pr121599.c: Tolerate alterate insn + selection. + +2025-10-25 Harald Anlauf <anlauf@gmx.de> + + PR fortran/114023 + * gfortran.dg/is_contiguous_5.f90: New test. + +2025-10-25 Jiahao Xu <xujiahao@loongson.cn> + + * gcc.target/loongarch/lasx-reduc-1.c: New test. + 2025-10-24 Andrew MacLeod <amacleod@redhat.com> * gcc.dg/pr110405.c: New. diff --git a/gcc/testsuite/c-c++-common/ubsan/align-5.c b/gcc/testsuite/c-c++-common/ubsan/align-5.c index 4847901..6d2ac26 100644 --- a/gcc/testsuite/c-c++-common/ubsan/align-5.c +++ b/gcc/testsuite/c-c++-common/ubsan/align-5.c @@ -11,4 +11,6 @@ foo (char *p) return *q; } -/* { dg-final { scan-assembler "__ubsan_handle" } } */ +/* xfail, see PR 122038 as __builtin_assume_aligned should be instrumented instead + of only the load. */ +/* { dg-final { scan-assembler "__ubsan_handle" { xfail *-*-* } } } */ diff --git a/gcc/testsuite/g++.dg/opt/pr122394.C b/gcc/testsuite/g++.dg/opt/pr122394.C new file mode 100644 index 0000000..1f84beb --- /dev/null +++ b/gcc/testsuite/g++.dg/opt/pr122394.C @@ -0,0 +1,20 @@ +// PR tree-optimization/122394 +// { dg-do compile { target c++23 } } +// { dg-options "-O1 -g" } + +#include <compare> + +struct A { + friend auto operator<=> (A, A) = default; + double a; +}; +void foo (); +A b, c; + +void +bar () +{ + bool d = c >= b; + if (d) + foo (); +} diff --git a/gcc/testsuite/g++.target/riscv/rvv/xtheadvector/pr116593.C b/gcc/testsuite/g++.target/riscv/rvv/xtheadvector/pr116593.C index cef5bec..a263c83 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/xtheadvector/pr116593.C +++ b/gcc/testsuite/g++.target/riscv/rvv/xtheadvector/pr116593.C @@ -1,5 +1,6 @@ /* Test that we do not have ice when compile */ /* { dg-do compile } */ +/* { dg-skip-if "requires hosted libstdc++ for vector" { ! hostedlib } } */ /* { dg-options "-march=rv32gc_zfh_xtheadvector -mabi=ilp32d -O2" { target { rv32 } } } */ /* { dg-options "-march=rv64gc_zfh_xtheadvector -mabi=lp64d -O2" { target { rv64 } } } */ diff --git a/gcc/testsuite/gcc.dg/complex-8.c b/gcc/testsuite/gcc.dg/complex-8.c new file mode 100644 index 0000000..ea20adf --- /dev/null +++ b/gcc/testsuite/gcc.dg/complex-8.c @@ -0,0 +1,13 @@ +/* PR tree-optimization/122325. */ + +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-cplxlower" } */ +/* { dg-require-effective-target double64 } */ + +__complex double +foo (__complex double a, __complex double b) +{ + return a / b; +} + +/* { dg-final { scan-tree-dump-times "__(?:gnu_)?divdc3" 1 "cplxlower1" } } */ diff --git a/gcc/testsuite/gcc.dg/complex-9.c b/gcc/testsuite/gcc.dg/complex-9.c new file mode 100644 index 0000000..413c507 --- /dev/null +++ b/gcc/testsuite/gcc.dg/complex-9.c @@ -0,0 +1,13 @@ +/* PR tree-optimization/122325. */ + +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -fdump-tree-cplxlower" } */ +/* { dg-require-effective-target double64 } */ + +__complex double +foo (__complex double a, __complex double b) +{ + return a / b; +} + +/* { dg-final { scan-tree-dump-not "__(?:gnu_)?divdc3" "cplxlower1" } } */ diff --git a/gcc/testsuite/gcc.dg/pr107389.c b/gcc/testsuite/gcc.dg/torture/pr107389.c index deb6338..23c2776 100644 --- a/gcc/testsuite/gcc.dg/pr107389.c +++ b/gcc/testsuite/gcc.dg/torture/pr107389.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-fdump-tree-optimized-alias" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */ +/* { dg-additional-options "-fdump-tree-optimized-alias" } */ unsigned foo (void *p) { diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr111003.c b/gcc/testsuite/gcc.dg/tree-ssa/pr111003.c index 59d3a96..10cfe88 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/pr111003.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr111003.c @@ -31,4 +31,4 @@ static int *i() { } int main() { k(c, c); } -/* { dg-final { scan-tree-dump-not "foo" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "foo" "optimized" { xfail *-*-* } } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-111.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-111.c new file mode 100644 index 0000000..7b96a83 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-111.c @@ -0,0 +1,11 @@ +/* PR122435 */ +/* { dg-do compile } */ +/* { dg-options "-O -fdump-tree-fre1-details" } */ + +void foo (unsigned *p) +{ + int i = *p; + *(int *)p = i; +} + +/* { dg-final { scan-tree-dump "Deleted redundant store" "fre1" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr122419.c b/gcc/testsuite/gcc.dg/vect/pr122419.c new file mode 100644 index 0000000..b428cfb --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr122419.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ + +int a; +long b; +void c() +{ + for (; b; b--) + a = (char)a; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pr121599.c b/gcc/testsuite/gcc.target/aarch64/sve2/pr121599.c index 90c5ac9..da4b7aa 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/pr121599.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/pr121599.c @@ -7,7 +7,7 @@ /* ** foo: -** movi d([0-9]+), #0 +** movi? [vdz]([0-9]+)\.?b?, #0 ** movprfx z0\.b, p0/z, z0\.b ** usqadd z0\.b, p0/m, z0\.b, z\1\.b ** ret @@ -19,7 +19,7 @@ svuint8_t foo (svbool_t pg, svuint8_t op1) /* ** bar: -** movi d([0-9]+), #0 +** movi? [vdz]([0-9]+)\.?b?, #0 ** movprfx z0\.b, p0/z, z0\.b ** suqadd z0\.b, p0/m, z0\.b, z\1\.b ** ret diff --git a/gcc/testsuite/gcc.target/i386/builtin-copysign-8b.c b/gcc/testsuite/gcc.target/i386/builtin-copysign-8b.c index 8f0cb27..dc9e461 100644 --- a/gcc/testsuite/gcc.target/i386/builtin-copysign-8b.c +++ b/gcc/testsuite/gcc.target/i386/builtin-copysign-8b.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mno-avx512f -mavx" } */ +/* { dg-options "-O2 -mno-avx512f -mavx -mtune=generic" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target { ! ia32 } } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/compare-both-non-zero.c b/gcc/testsuite/gcc.target/loongarch/compare-both-non-zero.c new file mode 100644 index 0000000..b813df4 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/compare-both-non-zero.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target { loongarch64*-*-* } } } */ +/* { dg-options "-O3" } */ + +int +test (int a, int b) +{ + return a && b; +} + +/* { dg-final { scan-assembler "maskeqz" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/sign_extend_ashift.c b/gcc/testsuite/gcc.target/loongarch/sign_extend_ashift.c new file mode 100644 index 0000000..921fda9 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/sign_extend_ashift.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { loongarch64*-*-* } } } */ +/* { dg-options "-O3" } */ +/* { dg-final { scan-assembler "slli\\.w" } } */ +/* { dg-final { scan-assembler-not "slli\\.d" } } */ +/* { dg-final { scan-assembler-not "ext\\.w\\.b" } } */ + +unsigned int +test (unsigned int id) +{ + return id << 24; +} diff --git a/gcc/testsuite/gcc.target/loongarch/widen-mul-rtx-cost-signed.c b/gcc/testsuite/gcc.target/loongarch/widen-mul-rtx-cost-signed.c new file mode 100644 index 0000000..1e1e75f --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/widen-mul-rtx-cost-signed.c @@ -0,0 +1,13 @@ +/* Verify optimization for mulw.d.w, + which can help with the replacement of the high-latency div.w. */ +/* { dg-do compile { target { loongarch64*-*-* } } } */ +/* { dg-options "-O3" } */ + +int +test (int a) +{ + return a / 3; +} + +/* { dg-final { scan-assembler {\tmulw.d.w\t} } } */ +/* { dg-final { scan-assembler-not {\tdiv.w\t} } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/widen-mul-rtx-cost-unsigned.c b/gcc/testsuite/gcc.target/loongarch/widen-mul-rtx-cost-unsigned.c new file mode 100644 index 0000000..32a428f --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/widen-mul-rtx-cost-unsigned.c @@ -0,0 +1,11 @@ +/* Verify optimization for mulh.wu, which can reduce insns. */ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +int +test (unsigned int a) +{ + return a / 3; +} + +/* { dg-final { scan-assembler {\tmulh.wu\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr120553-2.c b/gcc/testsuite/gcc.target/riscv/pr120553-2.c index 1501f86..000f4bb 100644 --- a/gcc/testsuite/gcc.target/riscv/pr120553-2.c +++ b/gcc/testsuite/gcc.target/riscv/pr120553-2.c @@ -83,8 +83,8 @@ T1(63) #endif /* { dg-final { scan-assembler-times "\\t(srai)" 128 { target rv64 } } } */ -/* { dg-final { scan-assembler-times "\\t(orn|ori|bset)" 128 { target rv64 } } } */ +/* { dg-final { scan-assembler-times "\\t(orn|ori|bset)" 196 { target rv64 } } } */ /* { dg-final { scan-assembler-times "\\t(srai)" 64 { target rv32 } } } */ -/* { dg-final { scan-assembler-times "\\t(orn|ori|bset)" 64 { target rv32 } } } */ +/* { dg-final { scan-assembler-times "\\t(orn|ori|bset)" 66 { target rv32 } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr64345.c b/gcc/testsuite/gcc.target/riscv/pr64345.c new file mode 100644 index 0000000..8ca4e24 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr64345.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gcbv_zicond -mabi=lp64d" { target rv64 } } */ +/* { dg-options "-O2 -march=rv32gcbv_zicond -mabi=ilp32" { target rv32 } } */ + + + +unsigned int test0 (unsigned int x) { return ((x >> 4) ^ 1) & 1; } + +unsigned int test1 (unsigned int x) { return ((x >> 4) & 1) ^ 1; } + +unsigned int test2 (unsigned int x) { return ~(x >> 4) & 1; } + +unsigned int test3 (unsigned int x) { return ((~x >> 4) & 1); } + +unsigned int test4 (unsigned int x) { return (x >> 4) & 1; } + +int test5 (int vi) { return vi - (((vi >> 6) & 0x01) << 1); } + +int test6 (int vi) { return vi - (((vi >> 6) & 0x01) << 1) - 1; } + + +/* { dg-final { scan-assembler-times "\\tbexti" 5 } } */ +/* { dg-final { scan-assembler-times "\\txori" 3 } } */ +/* { dg-final { scan-assembler-times "\\tnot" 1 } } */ +/* { dg-final { scan-assembler-times "\\tsrli" 2 } } */ +/* { dg-final { scan-assembler-times "\\tandi" 2 } } */ +/* { dg-final { scan-assembler-times "\\tsub" 2 } } */ +/* { dg-final { scan-assembler-times "\\taddi" 1 } } */ + + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-2.c index 32db3a6..e0d757a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-2.c @@ -6,5 +6,6 @@ /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*2,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 } } */ /* { dg-final { scan-assembler-times {vmv\.x\.s} 2 } } */ /* { dg-final { scan-assembler-times {vslidedown.vi\s+v[0-9]+,\s*v[0-9]+,\s*1} 1 } } */ -/* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,[a-x0-9]+,32} 1 } } */ +/* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,[a-x0-9]+,32} 2 } } */ +/* { dg-final { scan-assembler-times {srli\s+[a-x0-9]+,[a-x0-9]+,32} 1 } } */ /* { dg-final { scan-assembler-times {or\s+[a-x0-9]+,[a-x0-9]+,[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr122270-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr122270-1.c new file mode 100644 index 0000000..a026a7e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr122270-1.c @@ -0,0 +1,10 @@ +/* { dg-options "" } */ +/* { dg-do compile } */ +/* { dg-add-options riscv_v } */ +/* PR target/122270 */ + +#include "riscv_vector.h" + +void a(vfloat32m1_t b, vfloat32m1x4_t *c) { + *c = __riscv_vset_v_f32m1_f32m1x4(*c, 3, b); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_128bit_vector.c new file mode 100644 index 0000000..7091d2a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_128bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_128bit_vector.h" +// Function under test: +// int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_256bit_vector.c new file mode 100644 index 0000000..da3ff2a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_256bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_256bit_vector.h" +// Function under test: +// int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_32bit_vector.c new file mode 100644 index 0000000..907aa706 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_32bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_32bit_vector.h" +// Function under test: +// int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_64bit_vector.c new file mode 100644 index 0000000..3036ada --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_64bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_64bit_vector.h" +// Function under test: +// int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_all_mixed.c new file mode 100644 index 0000000..1a57881 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_all_mixed.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_all_mixed.h" +// Function under test: +// double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_call_mixed_function.c new file mode 100644 index 0000000..90ab8c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_call_mixed_function.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_call_mixed_function.h" +// Function under test: +// int helper_mixed_function(int i, int32x4_t v, float f) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vector_elements.c new file mode 100644 index 0000000..4309984 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vector_elements.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_different_vector_elements.h" +// Function under test: +// int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec, +// int32x4_t int_vec, int64x2_t long_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v9 \[ short_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ int_vec \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v11 \[ long_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vectors_struct.c new file mode 100644 index 0000000..66cd626 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_different_vectors_struct.h" +// Function under test: +// struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_width_vectors_struct.c new file mode 100644 index 0000000..09def6d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_width_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_different_width_vectors_struct.h" +// Function under test: +// different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+\)[[:space:]]+\(reg:V8HI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_equivalent_struct.c new file mode 100644 index 0000000..8cd74f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_equivalent_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_equivalent_struct.h" +// Function under test: +// equivalent_struct_t test_equivalent_struct(equivalent_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_four_registers.c new file mode 100644 index 0000000..837932c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_four_registers.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_four_registers.h" +// Function under test: +// int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_fp_vs_int_vectors.c new file mode 100644 index 0000000..1c1564a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_fp_vs_int_vectors.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_fp_vs_int_vectors.h" +// Function under test: +// float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec, +// double64x2_t double_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ float_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v10 \[ double_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_large_vector_small_abi_vlen.c new file mode 100644 index 0000000..e44a8af --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_large_vector_small_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_large_vector_small_abi_vlen.h" +// Function under test: +// int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_args.c new file mode 100644 index 0000000..8b3b2a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_args.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_args.h" +// Function under test: +// int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_float_vector.c new file mode 100644 index 0000000..32f3de4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_float_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_float_vector.h" +// Function under test: +// float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_int_vector.c new file mode 100644 index 0000000..ac2ef23 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_int_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_int_vector.h" +// Function under test: +// int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct.c new file mode 100644 index 0000000..5b2ea03 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_struct.h" +// Function under test: +// struct_mixed_t test_mixed_struct(struct_mixed_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct_advanced.c new file mode 100644 index 0000000..6962363 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct_advanced.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_struct_advanced.h" +// Function under test: +// mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_vector_types_struct.c new file mode 100644 index 0000000..0eb676e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_vector_types_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_vector_types_struct.h" +// Function under test: +// mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+\)[[:space:]]+\(reg:V4SF \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_unions.c new file mode 100644 index 0000000..5be696c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_unions.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_multiple_unions.h" +// Function under test: +// union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_vectors.c new file mode 100644 index 0000000..3f3c5e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_vectors.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_multiple_vectors.h" +// Function under test: +// int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_with_small_abi_vlen.c new file mode 100644 index 0000000..3bab9a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_with_small_abi_vlen.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_multiple_with_small_abi_vlen.h" +// Function under test: +// int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2, +// int32x4_t v3, int32x4_t v4) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion.c new file mode 100644 index 0000000..7ab38ee --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_register_exhaustion.h" +// Function under test: +// int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, +// int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, +// int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, +// int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, +// int32x4_t v17) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion_mixed.c new file mode 100644 index 0000000..6fd3c0b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion_mixed.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_register_exhaustion_mixed.h" +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_pressure_scenarios.c new file mode 100644 index 0000000..ca0f8b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_pressure_scenarios.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_register_pressure_scenarios.h" +// Function under test: +// void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2, +// int32x4_t medium1, int32x4_t medium2, +// int32x8_t large1) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ medium2 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ large1 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_same_vectors_struct.c new file mode 100644 index 0000000..92acb96 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_same_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_same_vectors_struct.h" +// Function under test: +// struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_simple_union.c new file mode 100644 index 0000000..201ff4e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_simple_union.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_simple_union.h" +// Function under test: +// union_vector_t test_simple_union(union_vector_t u) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_register.c new file mode 100644 index 0000000..bb92880 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_register.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_single_register.h" +// Function under test: +// int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_vector_struct.c new file mode 100644 index 0000000..9cfa866 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_vector_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_single_vector_struct.h" +// Function under test: +// struct_single_vector_t test_single_vector_struct(struct_single_vector_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_different_abi_vlen.c new file mode 100644 index 0000000..24478f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_different_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_different_abi_vlen.h" +// Function under test: +// two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_eight_128bit_vectors.c new file mode 100644 index 0000000..21c918c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_eight_128bit_vectors.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_eight_128bit_vectors.h" +// Function under test: +// eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v10 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v11 \[ s\+48 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v12 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v13 \[ s\+80 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v14 \[ s\+96 \]\)\)} "expand" } } */ +// Check argument 8 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v15 \[ s\+112 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_five_256bit_vectors.c new file mode 100644 index 0000000..f32b61c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_five_256bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_five_256bit_vectors.h" +// Function under test: +// five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_four_256bit_vectors.c new file mode 100644 index 0000000..8efa10f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_four_256bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_four_256bit_vectors.h" +// Function under test: +// four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_nine_128bit_vectors.c new file mode 100644 index 0000000..0204829 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_nine_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_nine_128bit_vectors.h" +// Function under test: +// nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_two_registers.c new file mode 100644 index 0000000..8a40a16 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_two_registers.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_two_registers.h" +// Function under test: +// int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_vector_array_struct.c new file mode 100644 index 0000000..94e516c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_vector_array_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_vector_array_struct.h" +// Function under test: +// struct_vector_array_t test_vector_array_struct(struct_vector_array_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_128bit_vector.c new file mode 100644 index 0000000..12acdaa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_128bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_128bit_vector.h" +// Function under test: +// int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_256bit_vector.c new file mode 100644 index 0000000..ead0e70 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_256bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_256bit_vector.h" +// Function under test: +// int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_32bit_vector.c new file mode 100644 index 0000000..c97a7c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_32bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_32bit_vector.h" +// Function under test: +// int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_64bit_vector.c new file mode 100644 index 0000000..f3fb86d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_64bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_64bit_vector.h" +// Function under test: +// int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_all_mixed.c new file mode 100644 index 0000000..7eeaa6b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_all_mixed.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_all_mixed.h" +// Function under test: +// double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_call_mixed_function.c new file mode 100644 index 0000000..0676290 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_call_mixed_function.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_call_mixed_function.h" +// Function under test: +// int helper_mixed_function(int i, int32x4_t v, float f) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vector_elements.c new file mode 100644 index 0000000..dff67ab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vector_elements.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_different_vector_elements.h" +// Function under test: +// int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec, +// int32x4_t int_vec, int64x2_t long_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v9 \[ short_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ int_vec \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v11 \[ long_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vectors_struct.c new file mode 100644 index 0000000..40d4442 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_different_vectors_struct.h" +// Function under test: +// struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_width_vectors_struct.c new file mode 100644 index 0000000..2cd1322 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_width_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_different_width_vectors_struct.h" +// Function under test: +// different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+\)[[:space:]]+\(reg:V8HI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_equivalent_struct.c new file mode 100644 index 0000000..6463c5c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_equivalent_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_equivalent_struct.h" +// Function under test: +// equivalent_struct_t test_equivalent_struct(equivalent_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_four_registers.c new file mode 100644 index 0000000..4d84a37 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_four_registers.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_four_registers.h" +// Function under test: +// int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_fp_vs_int_vectors.c new file mode 100644 index 0000000..7e992f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_fp_vs_int_vectors.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_fp_vs_int_vectors.h" +// Function under test: +// float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec, +// double64x2_t double_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ float_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v10 \[ double_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_large_vector_small_abi_vlen.c new file mode 100644 index 0000000..ab3027b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_large_vector_small_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_large_vector_small_abi_vlen.h" +// Function under test: +// int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_args.c new file mode 100644 index 0000000..d16d14b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_args.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_args.h" +// Function under test: +// int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_float_vector.c new file mode 100644 index 0000000..5cd6e52 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_float_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_float_vector.h" +// Function under test: +// float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_int_vector.c new file mode 100644 index 0000000..fb4aff9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_int_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_int_vector.h" +// Function under test: +// int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct.c new file mode 100644 index 0000000..3db1d27 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_struct.h" +// Function under test: +// struct_mixed_t test_mixed_struct(struct_mixed_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct_advanced.c new file mode 100644 index 0000000..a8c07f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct_advanced.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_struct_advanced.h" +// Function under test: +// mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_vector_types_struct.c new file mode 100644 index 0000000..0a230ac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_vector_types_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_vector_types_struct.h" +// Function under test: +// mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+\)[[:space:]]+\(reg:V4SF \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_unions.c new file mode 100644 index 0000000..18051f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_unions.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_multiple_unions.h" +// Function under test: +// union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_vectors.c new file mode 100644 index 0000000..25a6042 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_vectors.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_multiple_vectors.h" +// Function under test: +// int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_with_small_abi_vlen.c new file mode 100644 index 0000000..c9959ae --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_with_small_abi_vlen.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_multiple_with_small_abi_vlen.h" +// Function under test: +// int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2, +// int32x4_t v3, int32x4_t v4) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion.c new file mode 100644 index 0000000..3da8d8f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_register_exhaustion.h" +// Function under test: +// int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, +// int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, +// int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, +// int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, +// int32x4_t v17) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion_mixed.c new file mode 100644 index 0000000..7fc773b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion_mixed.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_register_exhaustion_mixed.h" +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_pressure_scenarios.c new file mode 100644 index 0000000..9c3cd79 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_pressure_scenarios.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_register_pressure_scenarios.h" +// Function under test: +// void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2, +// int32x4_t medium1, int32x4_t medium2, +// int32x8_t large1) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ medium2 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ large1 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_same_vectors_struct.c new file mode 100644 index 0000000..42041b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_same_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_same_vectors_struct.h" +// Function under test: +// struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_simple_union.c new file mode 100644 index 0000000..9ea145f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_simple_union.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_simple_union.h" +// Function under test: +// union_vector_t test_simple_union(union_vector_t u) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_register.c new file mode 100644 index 0000000..a52c0a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_register.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_single_register.h" +// Function under test: +// int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_vector_struct.c new file mode 100644 index 0000000..f467fd5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_vector_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_single_vector_struct.h" +// Function under test: +// struct_single_vector_t test_single_vector_struct(struct_single_vector_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_different_abi_vlen.c new file mode 100644 index 0000000..7d7bedd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_different_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_different_abi_vlen.h" +// Function under test: +// two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_eight_128bit_vectors.c new file mode 100644 index 0000000..8e576f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_eight_128bit_vectors.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_eight_128bit_vectors.h" +// Function under test: +// eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v10 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v11 \[ s\+48 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v12 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v13 \[ s\+80 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v14 \[ s\+96 \]\)\)} "expand" } } */ +// Check argument 8 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v15 \[ s\+112 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_five_256bit_vectors.c new file mode 100644 index 0000000..5575aab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_five_256bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_five_256bit_vectors.h" +// Function under test: +// five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_four_256bit_vectors.c new file mode 100644 index 0000000..6e9fd33 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_four_256bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_four_256bit_vectors.h" +// Function under test: +// four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_nine_128bit_vectors.c new file mode 100644 index 0000000..734d929 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_nine_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_nine_128bit_vectors.h" +// Function under test: +// nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_two_registers.c new file mode 100644 index 0000000..743d773 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_two_registers.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_two_registers.h" +// Function under test: +// int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_vector_array_struct.c new file mode 100644 index 0000000..dc4623e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_vector_array_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_vector_array_struct.h" +// Function under test: +// struct_vector_array_t test_vector_array_struct(struct_vector_array_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_128bit_vector.c new file mode 100644 index 0000000..6ee5565 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_128bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_128bit_vector.h" +// Function under test: +// int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_256bit_vector.c new file mode 100644 index 0000000..363dd61 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_256bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_256bit_vector.h" +// Function under test: +// int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_32bit_vector.c new file mode 100644 index 0000000..63e2a84 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_32bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_32bit_vector.h" +// Function under test: +// int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_64bit_vector.c new file mode 100644 index 0000000..5c1269a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_64bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_64bit_vector.h" +// Function under test: +// int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_all_mixed.c new file mode 100644 index 0000000..7580504 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_all_mixed.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_all_mixed.h" +// Function under test: +// double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_call_mixed_function.c new file mode 100644 index 0000000..1d494e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_call_mixed_function.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_call_mixed_function.h" +// Function under test: +// int helper_mixed_function(int i, int32x4_t v, float f) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vector_elements.c new file mode 100644 index 0000000..9650ea4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vector_elements.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_different_vector_elements.h" +// Function under test: +// int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec, +// int32x4_t int_vec, int64x2_t long_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v9 \[ short_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ int_vec \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v11 \[ long_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vectors_struct.c new file mode 100644 index 0000000..41335d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_different_vectors_struct.h" +// Function under test: +// struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_width_vectors_struct.c new file mode 100644 index 0000000..da85d52 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_width_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_different_width_vectors_struct.h" +// Function under test: +// different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+\)[[:space:]]+\(reg:V8HI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_equivalent_struct.c new file mode 100644 index 0000000..d2d0f07 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_equivalent_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_equivalent_struct.h" +// Function under test: +// equivalent_struct_t test_equivalent_struct(equivalent_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_four_registers.c new file mode 100644 index 0000000..c11c3e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_four_registers.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_four_registers.h" +// Function under test: +// int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_fp_vs_int_vectors.c new file mode 100644 index 0000000..3862322 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_fp_vs_int_vectors.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_fp_vs_int_vectors.h" +// Function under test: +// float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec, +// double64x2_t double_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ float_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v10 \[ double_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_large_vector_small_abi_vlen.c new file mode 100644 index 0000000..1ec92f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_large_vector_small_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_large_vector_small_abi_vlen.h" +// Function under test: +// int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_args.c new file mode 100644 index 0000000..d0a01e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_args.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_args.h" +// Function under test: +// int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_float_vector.c new file mode 100644 index 0000000..9acf247 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_float_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_float_vector.h" +// Function under test: +// float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_int_vector.c new file mode 100644 index 0000000..4d3265c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_int_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_int_vector.h" +// Function under test: +// int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct.c new file mode 100644 index 0000000..63b5ea0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_struct.h" +// Function under test: +// struct_mixed_t test_mixed_struct(struct_mixed_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct_advanced.c new file mode 100644 index 0000000..8721f44 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct_advanced.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_struct_advanced.h" +// Function under test: +// mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_vector_types_struct.c new file mode 100644 index 0000000..10efd1e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_vector_types_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_vector_types_struct.h" +// Function under test: +// mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+\)[[:space:]]+\(reg:V4SF \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_unions.c new file mode 100644 index 0000000..ab90555 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_unions.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_multiple_unions.h" +// Function under test: +// union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_vectors.c new file mode 100644 index 0000000..8ec429b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_vectors.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_multiple_vectors.h" +// Function under test: +// int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_with_small_abi_vlen.c new file mode 100644 index 0000000..bf8f4d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_with_small_abi_vlen.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_multiple_with_small_abi_vlen.h" +// Function under test: +// int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2, +// int32x4_t v3, int32x4_t v4) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion.c new file mode 100644 index 0000000..892fa74 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_register_exhaustion.h" +// Function under test: +// int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, +// int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, +// int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, +// int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, +// int32x4_t v17) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion_mixed.c new file mode 100644 index 0000000..8f28061 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion_mixed.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_register_exhaustion_mixed.h" +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_pressure_scenarios.c new file mode 100644 index 0000000..e16b945 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_pressure_scenarios.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_register_pressure_scenarios.h" +// Function under test: +// void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2, +// int32x4_t medium1, int32x4_t medium2, +// int32x8_t large1) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ medium2 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ large1 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_same_vectors_struct.c new file mode 100644 index 0000000..9e9c55d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_same_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_same_vectors_struct.h" +// Function under test: +// struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_simple_union.c new file mode 100644 index 0000000..34f83d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_simple_union.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_simple_union.h" +// Function under test: +// union_vector_t test_simple_union(union_vector_t u) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_register.c new file mode 100644 index 0000000..141684c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_register.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_single_register.h" +// Function under test: +// int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_vector_struct.c new file mode 100644 index 0000000..c275b40 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_vector_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_single_vector_struct.h" +// Function under test: +// struct_single_vector_t test_single_vector_struct(struct_single_vector_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_different_abi_vlen.c new file mode 100644 index 0000000..2704451 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_different_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_different_abi_vlen.h" +// Function under test: +// two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_eight_128bit_vectors.c new file mode 100644 index 0000000..30209a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_eight_128bit_vectors.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_eight_128bit_vectors.h" +// Function under test: +// eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v10 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v11 \[ s\+48 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v12 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v13 \[ s\+80 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v14 \[ s\+96 \]\)\)} "expand" } } */ +// Check argument 8 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v15 \[ s\+112 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_five_256bit_vectors.c new file mode 100644 index 0000000..3a3f4b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_five_256bit_vectors.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_five_256bit_vectors.h" +// Function under test: +// five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v12 \[ s\+128 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_four_256bit_vectors.c new file mode 100644 index 0000000..9822d96 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_four_256bit_vectors.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_four_256bit_vectors.h" +// Function under test: +// four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_nine_128bit_vectors.c new file mode 100644 index 0000000..5231401 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_nine_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_nine_128bit_vectors.h" +// Function under test: +// nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_two_registers.c new file mode 100644 index 0000000..c313cfc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_two_registers.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_two_registers.h" +// Function under test: +// int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_vector_array_struct.c new file mode 100644 index 0000000..33843a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_vector_array_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_vector_array_struct.h" +// Function under test: +// struct_vector_array_t test_vector_array_struct(struct_vector_array_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_128bit_vector.c new file mode 100644 index 0000000..87d7ac3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_128bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_128bit_vector.h" +// Function under test: +// int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_256bit_vector.c new file mode 100644 index 0000000..1c5b27d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_256bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_256bit_vector.h" +// Function under test: +// int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_32bit_vector.c new file mode 100644 index 0000000..b985252 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_32bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_32bit_vector.h" +// Function under test: +// int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_64bit_vector.c new file mode 100644 index 0000000..b12c6a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_64bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_64bit_vector.h" +// Function under test: +// int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_all_mixed.c new file mode 100644 index 0000000..770bec6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_all_mixed.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_all_mixed.h" +// Function under test: +// double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_call_mixed_function.c new file mode 100644 index 0000000..dc5a6cd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_call_mixed_function.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_call_mixed_function.h" +// Function under test: +// int helper_mixed_function(int i, int32x4_t v, float f) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vector_elements.c new file mode 100644 index 0000000..bed512b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vector_elements.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_different_vector_elements.h" +// Function under test: +// int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec, +// int32x4_t int_vec, int64x2_t long_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v9 \[ short_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ int_vec \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v11 \[ long_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vectors_struct.c new file mode 100644 index 0000000..0b56802 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_different_vectors_struct.h" +// Function under test: +// struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_width_vectors_struct.c new file mode 100644 index 0000000..361bff7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_width_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_different_width_vectors_struct.h" +// Function under test: +// different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+\)[[:space:]]+\(reg:V8HI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_equivalent_struct.c new file mode 100644 index 0000000..42d7c95 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_equivalent_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_equivalent_struct.h" +// Function under test: +// equivalent_struct_t test_equivalent_struct(equivalent_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_four_registers.c new file mode 100644 index 0000000..a4897e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_four_registers.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_four_registers.h" +// Function under test: +// int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_fp_vs_int_vectors.c new file mode 100644 index 0000000..90f15c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_fp_vs_int_vectors.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_fp_vs_int_vectors.h" +// Function under test: +// float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec, +// double64x2_t double_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ float_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v10 \[ double_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_large_vector_small_abi_vlen.c new file mode 100644 index 0000000..166bc8d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_large_vector_small_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_large_vector_small_abi_vlen.h" +// Function under test: +// int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_args.c new file mode 100644 index 0000000..5f95941 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_args.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_args.h" +// Function under test: +// int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_float_vector.c new file mode 100644 index 0000000..7cef54c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_float_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_float_vector.h" +// Function under test: +// float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_int_vector.c new file mode 100644 index 0000000..d383a34 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_int_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_int_vector.h" +// Function under test: +// int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct.c new file mode 100644 index 0000000..44c80b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_struct.h" +// Function under test: +// struct_mixed_t test_mixed_struct(struct_mixed_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct_advanced.c new file mode 100644 index 0000000..c173c0a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct_advanced.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_struct_advanced.h" +// Function under test: +// mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_vector_types_struct.c new file mode 100644 index 0000000..bda5096 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_vector_types_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_vector_types_struct.h" +// Function under test: +// mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+\)[[:space:]]+\(reg:V4SF \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_unions.c new file mode 100644 index 0000000..58bac01 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_unions.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_multiple_unions.h" +// Function under test: +// union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_vectors.c new file mode 100644 index 0000000..8294c54 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_vectors.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_multiple_vectors.h" +// Function under test: +// int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_with_small_abi_vlen.c new file mode 100644 index 0000000..2f0c620 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_with_small_abi_vlen.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_multiple_with_small_abi_vlen.h" +// Function under test: +// int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2, +// int32x4_t v3, int32x4_t v4) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion.c new file mode 100644 index 0000000..9538ba0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_register_exhaustion.h" +// Function under test: +// int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, +// int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, +// int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, +// int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, +// int32x4_t v17) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion_mixed.c new file mode 100644 index 0000000..118627d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion_mixed.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_register_exhaustion_mixed.h" +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_pressure_scenarios.c new file mode 100644 index 0000000..7b6737b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_pressure_scenarios.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_register_pressure_scenarios.h" +// Function under test: +// void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2, +// int32x4_t medium1, int32x4_t medium2, +// int32x8_t large1) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ medium2 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ large1 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_same_vectors_struct.c new file mode 100644 index 0000000..04e1bef --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_same_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_same_vectors_struct.h" +// Function under test: +// struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_simple_union.c new file mode 100644 index 0000000..beaa25e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_simple_union.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_simple_union.h" +// Function under test: +// union_vector_t test_simple_union(union_vector_t u) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_register.c new file mode 100644 index 0000000..d21028e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_register.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_single_register.h" +// Function under test: +// int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_vector_struct.c new file mode 100644 index 0000000..bab73584 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_vector_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_single_vector_struct.h" +// Function under test: +// struct_single_vector_t test_single_vector_struct(struct_single_vector_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_different_abi_vlen.c new file mode 100644 index 0000000..11dd3c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_different_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_different_abi_vlen.h" +// Function under test: +// two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_eight_128bit_vectors.c new file mode 100644 index 0000000..b1199d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_eight_128bit_vectors.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_eight_128bit_vectors.h" +// Function under test: +// eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v10 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v11 \[ s\+48 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v12 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v13 \[ s\+80 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v14 \[ s\+96 \]\)\)} "expand" } } */ +// Check argument 8 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v15 \[ s\+112 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_five_256bit_vectors.c new file mode 100644 index 0000000..fe48ae0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_five_256bit_vectors.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_five_256bit_vectors.h" +// Function under test: +// five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v12 \[ s\+128 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_four_256bit_vectors.c new file mode 100644 index 0000000..d4026ba --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_four_256bit_vectors.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_four_256bit_vectors.h" +// Function under test: +// four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_nine_128bit_vectors.c new file mode 100644 index 0000000..c6111b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_nine_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_nine_128bit_vectors.h" +// Function under test: +// nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_two_registers.c new file mode 100644 index 0000000..7c919f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_two_registers.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_two_registers.h" +// Function under test: +// int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_vector_array_struct.c new file mode 100644 index 0000000..c4c57f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_vector_array_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_vector_array_struct.h" +// Function under test: +// struct_vector_array_t test_vector_array_struct(struct_vector_array_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_128bit_vector.c new file mode 100644 index 0000000..8452f93 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_128bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_128bit_vector.h" +// Function under test: +// int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_256bit_vector.c new file mode 100644 index 0000000..3579523 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_256bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_256bit_vector.h" +// Function under test: +// int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_32bit_vector.c new file mode 100644 index 0000000..310c607 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_32bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_32bit_vector.h" +// Function under test: +// int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_64bit_vector.c new file mode 100644 index 0000000..d34af19 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_64bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_64bit_vector.h" +// Function under test: +// int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_all_mixed.c new file mode 100644 index 0000000..763f9b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_all_mixed.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_all_mixed.h" +// Function under test: +// double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_call_mixed_function.c new file mode 100644 index 0000000..eb7a97f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_call_mixed_function.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_call_mixed_function.h" +// Function under test: +// int helper_mixed_function(int i, int32x4_t v, float f) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vector_elements.c new file mode 100644 index 0000000..2e34be5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vector_elements.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_different_vector_elements.h" +// Function under test: +// int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec, +// int32x4_t int_vec, int64x2_t long_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v12 \[ short_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ int_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vectors_struct.c new file mode 100644 index 0000000..e3a2fd9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_different_vectors_struct.h" +// Function under test: +// struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_width_vectors_struct.c new file mode 100644 index 0000000..f3fdc9c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_width_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_different_width_vectors_struct.h" +// Function under test: +// different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_equivalent_struct.c new file mode 100644 index 0000000..ca39ab1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_equivalent_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_equivalent_struct.h" +// Function under test: +// equivalent_struct_t test_equivalent_struct(equivalent_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_four_registers.c new file mode 100644 index 0000000..78674a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_four_registers.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_four_registers.h" +// Function under test: +// int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_fp_vs_int_vectors.c new file mode 100644 index 0000000..dd02323 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_fp_vs_int_vectors.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_fp_vs_int_vectors.h" +// Function under test: +// float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec, +// double64x2_t double_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v12 \[ float_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_large_vector_small_abi_vlen.c new file mode 100644 index 0000000..a304c3a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_large_vector_small_abi_vlen.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_large_vector_small_abi_vlen.h" +// Function under test: +// int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_args.c new file mode 100644 index 0000000..12a8530 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_args.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_mixed_args.h" +// Function under test: +// int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_float_vector.c new file mode 100644 index 0000000..777e0b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_float_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_mixed_float_vector.h" +// Function under test: +// float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_int_vector.c new file mode 100644 index 0000000..16d31f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_int_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_mixed_int_vector.h" +// Function under test: +// int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct.c new file mode 100644 index 0000000..1ec749a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_mixed_struct.h" +// Function under test: +// struct_mixed_t test_mixed_struct(struct_mixed_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct_advanced.c new file mode 100644 index 0000000..9bc0eac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct_advanced.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_mixed_struct_advanced.h" +// Function under test: +// mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_vector_types_struct.c new file mode 100644 index 0000000..1e4f8a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_vector_types_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_mixed_vector_types_struct.h" +// Function under test: +// mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_unions.c new file mode 100644 index 0000000..01e3762 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_unions.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_multiple_unions.h" +// Function under test: +// union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_vectors.c new file mode 100644 index 0000000..9004567 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_multiple_vectors.h" +// Function under test: +// int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_with_small_abi_vlen.c new file mode 100644 index 0000000..4f4a78d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_with_small_abi_vlen.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_multiple_with_small_abi_vlen.h" +// Function under test: +// int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2, +// int32x4_t v3, int32x4_t v4) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion.c new file mode 100644 index 0000000..5400b18 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_register_exhaustion.h" +// Function under test: +// int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, +// int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, +// int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, +// int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, +// int32x4_t v17) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion_mixed.c new file mode 100644 index 0000000..0fce4dd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion_mixed.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_register_exhaustion_mixed.h" +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_pressure_scenarios.c new file mode 100644 index 0000000..661e1ce --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_pressure_scenarios.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_register_pressure_scenarios.h" +// Function under test: +// void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2, +// int32x4_t medium1, int32x4_t medium2, +// int32x8_t large1) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v10 \[ small2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ medium1 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ medium2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_same_vectors_struct.c new file mode 100644 index 0000000..92d4204 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_same_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_same_vectors_struct.h" +// Function under test: +// struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_simple_union.c new file mode 100644 index 0000000..581b350 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_simple_union.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_simple_union.h" +// Function under test: +// union_vector_t test_simple_union(union_vector_t u) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_register.c new file mode 100644 index 0000000..beb8e04 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_register.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_single_register.h" +// Function under test: +// int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_vector_struct.c new file mode 100644 index 0000000..f569caf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_vector_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_single_vector_struct.h" +// Function under test: +// struct_single_vector_t test_single_vector_struct(struct_single_vector_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_different_abi_vlen.c new file mode 100644 index 0000000..7801147 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_different_abi_vlen.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_struct_different_abi_vlen.h" +// Function under test: +// two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_eight_128bit_vectors.c new file mode 100644 index 0000000..72cb536 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_eight_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_struct_eight_128bit_vectors.h" +// Function under test: +// eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_five_256bit_vectors.c new file mode 100644 index 0000000..ccc1d79 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_five_256bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_struct_five_256bit_vectors.h" +// Function under test: +// five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_four_256bit_vectors.c new file mode 100644 index 0000000..12c054f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_four_256bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_struct_four_256bit_vectors.h" +// Function under test: +// four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_nine_128bit_vectors.c new file mode 100644 index 0000000..723c1f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_nine_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_struct_nine_128bit_vectors.h" +// Function under test: +// nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_two_registers.c new file mode 100644 index 0000000..1cea3bc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_two_registers.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_two_registers.h" +// Function under test: +// int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_vector_array_struct.c new file mode 100644 index 0000000..ede6525 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_vector_array_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_vector_array_struct.h" +// Function under test: +// struct_vector_array_t test_vector_array_struct(struct_vector_array_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_128bit_vector.c new file mode 100644 index 0000000..a5d4b1d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_128bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_128bit_vector.h" +// Function under test: +// int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_256bit_vector.c new file mode 100644 index 0000000..2c405c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_256bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_256bit_vector.h" +// Function under test: +// int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_32bit_vector.c new file mode 100644 index 0000000..917bc54 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_32bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_32bit_vector.h" +// Function under test: +// int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_64bit_vector.c new file mode 100644 index 0000000..b158857 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_64bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_64bit_vector.h" +// Function under test: +// int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_all_mixed.c new file mode 100644 index 0000000..51dc947 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_all_mixed.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_all_mixed.h" +// Function under test: +// double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_call_mixed_function.c new file mode 100644 index 0000000..3227893 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_call_mixed_function.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_call_mixed_function.h" +// Function under test: +// int helper_mixed_function(int i, int32x4_t v, float f) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vector_elements.c new file mode 100644 index 0000000..a49f7a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vector_elements.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_different_vector_elements.h" +// Function under test: +// int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec, +// int32x4_t int_vec, int64x2_t long_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v12 \[ short_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ int_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vectors_struct.c new file mode 100644 index 0000000..33dba6a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_different_vectors_struct.h" +// Function under test: +// struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_width_vectors_struct.c new file mode 100644 index 0000000..4b16990 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_width_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_different_width_vectors_struct.h" +// Function under test: +// different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_equivalent_struct.c new file mode 100644 index 0000000..c82fd43 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_equivalent_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_equivalent_struct.h" +// Function under test: +// equivalent_struct_t test_equivalent_struct(equivalent_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_four_registers.c new file mode 100644 index 0000000..42afa82 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_four_registers.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_four_registers.h" +// Function under test: +// int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_fp_vs_int_vectors.c new file mode 100644 index 0000000..690c296 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_fp_vs_int_vectors.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_fp_vs_int_vectors.h" +// Function under test: +// float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec, +// double64x2_t double_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v12 \[ float_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_large_vector_small_abi_vlen.c new file mode 100644 index 0000000..2a23285 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_large_vector_small_abi_vlen.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_large_vector_small_abi_vlen.h" +// Function under test: +// int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_args.c new file mode 100644 index 0000000..76d3252 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_args.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_mixed_args.h" +// Function under test: +// int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_float_vector.c new file mode 100644 index 0000000..97ac4b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_float_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_mixed_float_vector.h" +// Function under test: +// float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_int_vector.c new file mode 100644 index 0000000..02327db --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_int_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_mixed_int_vector.h" +// Function under test: +// int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct.c new file mode 100644 index 0000000..609dd0e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_mixed_struct.h" +// Function under test: +// struct_mixed_t test_mixed_struct(struct_mixed_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct_advanced.c new file mode 100644 index 0000000..db015da --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct_advanced.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_mixed_struct_advanced.h" +// Function under test: +// mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_vector_types_struct.c new file mode 100644 index 0000000..955543f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_vector_types_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_mixed_vector_types_struct.h" +// Function under test: +// mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_unions.c new file mode 100644 index 0000000..ca2fbb8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_unions.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_multiple_unions.h" +// Function under test: +// union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_vectors.c new file mode 100644 index 0000000..f6d8fa2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_multiple_vectors.h" +// Function under test: +// int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_with_small_abi_vlen.c new file mode 100644 index 0000000..1d033fa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_with_small_abi_vlen.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_multiple_with_small_abi_vlen.h" +// Function under test: +// int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2, +// int32x4_t v3, int32x4_t v4) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion.c new file mode 100644 index 0000000..98e7e6f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_register_exhaustion.h" +// Function under test: +// int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, +// int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, +// int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, +// int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, +// int32x4_t v17) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion_mixed.c new file mode 100644 index 0000000..4a62377 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion_mixed.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_register_exhaustion_mixed.h" +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_pressure_scenarios.c new file mode 100644 index 0000000..22b934c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_pressure_scenarios.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_register_pressure_scenarios.h" +// Function under test: +// void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2, +// int32x4_t medium1, int32x4_t medium2, +// int32x8_t large1) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v10 \[ small2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ medium1 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ medium2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_same_vectors_struct.c new file mode 100644 index 0000000..ae92296 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_same_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_same_vectors_struct.h" +// Function under test: +// struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_simple_union.c new file mode 100644 index 0000000..9ca77c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_simple_union.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_simple_union.h" +// Function under test: +// union_vector_t test_simple_union(union_vector_t u) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_register.c new file mode 100644 index 0000000..e78ac7c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_register.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_single_register.h" +// Function under test: +// int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_vector_struct.c new file mode 100644 index 0000000..db93b2a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_vector_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_single_vector_struct.h" +// Function under test: +// struct_single_vector_t test_single_vector_struct(struct_single_vector_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_different_abi_vlen.c new file mode 100644 index 0000000..6ebb269 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_different_abi_vlen.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_struct_different_abi_vlen.h" +// Function under test: +// two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_eight_128bit_vectors.c new file mode 100644 index 0000000..06c309e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_eight_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_struct_eight_128bit_vectors.h" +// Function under test: +// eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_five_256bit_vectors.c new file mode 100644 index 0000000..cd3d77a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_five_256bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_struct_five_256bit_vectors.h" +// Function under test: +// five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_four_256bit_vectors.c new file mode 100644 index 0000000..deaa87e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_four_256bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_struct_four_256bit_vectors.h" +// Function under test: +// four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_nine_128bit_vectors.c new file mode 100644 index 0000000..82ef5ba --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_nine_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_struct_nine_128bit_vectors.h" +// Function under test: +// nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_two_registers.c new file mode 100644 index 0000000..da2d81f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_two_registers.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_two_registers.h" +// Function under test: +// int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_vector_array_struct.c new file mode 100644 index 0000000..7236598 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_vector_array_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_vector_array_struct.h" +// Function under test: +// struct_vector_array_t test_vector_array_struct(struct_vector_array_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_128bit_vector.c new file mode 100644 index 0000000..9681dd2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_128bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_128bit_vector.h" +// Function under test: +// int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_256bit_vector.c new file mode 100644 index 0000000..cb54cd7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_256bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_256bit_vector.h" +// Function under test: +// int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_32bit_vector.c new file mode 100644 index 0000000..345dcac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_32bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_32bit_vector.h" +// Function under test: +// int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_64bit_vector.c new file mode 100644 index 0000000..429d9e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_64bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_64bit_vector.h" +// Function under test: +// int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_all_mixed.c new file mode 100644 index 0000000..30a46c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_all_mixed.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_all_mixed.h" +// Function under test: +// double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_call_mixed_function.c new file mode 100644 index 0000000..a108985 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_call_mixed_function.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_call_mixed_function.h" +// Function under test: +// int helper_mixed_function(int i, int32x4_t v, float f) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vector_elements.c new file mode 100644 index 0000000..fe3aa71 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vector_elements.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_different_vector_elements.h" +// Function under test: +// int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec, +// int32x4_t int_vec, int64x2_t long_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v9 \[ short_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ int_vec \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v11 \[ long_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vectors_struct.c new file mode 100644 index 0000000..26ddf7d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_different_vectors_struct.h" +// Function under test: +// struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_width_vectors_struct.c new file mode 100644 index 0000000..30670f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_width_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_different_width_vectors_struct.h" +// Function under test: +// different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+\)[[:space:]]+\(reg:V8HI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_equivalent_struct.c new file mode 100644 index 0000000..943629a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_equivalent_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_equivalent_struct.h" +// Function under test: +// equivalent_struct_t test_equivalent_struct(equivalent_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_four_registers.c new file mode 100644 index 0000000..d98678b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_four_registers.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_four_registers.h" +// Function under test: +// int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_fp_vs_int_vectors.c new file mode 100644 index 0000000..8503f32 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_fp_vs_int_vectors.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_fp_vs_int_vectors.h" +// Function under test: +// float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec, +// double64x2_t double_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ float_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v10 \[ double_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_large_vector_small_abi_vlen.c new file mode 100644 index 0000000..ebebf6d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_large_vector_small_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_large_vector_small_abi_vlen.h" +// Function under test: +// int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_args.c new file mode 100644 index 0000000..ad0d837 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_args.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_mixed_args.h" +// Function under test: +// int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_float_vector.c new file mode 100644 index 0000000..2842f1b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_float_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_mixed_float_vector.h" +// Function under test: +// float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_int_vector.c new file mode 100644 index 0000000..4b774e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_int_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_mixed_int_vector.h" +// Function under test: +// int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct.c new file mode 100644 index 0000000..89a5e09 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_mixed_struct.h" +// Function under test: +// struct_mixed_t test_mixed_struct(struct_mixed_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct_advanced.c new file mode 100644 index 0000000..d8bdc98 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct_advanced.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_mixed_struct_advanced.h" +// Function under test: +// mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_vector_types_struct.c new file mode 100644 index 0000000..779a4dc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_vector_types_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_mixed_vector_types_struct.h" +// Function under test: +// mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+\)[[:space:]]+\(reg:V4SF \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_unions.c new file mode 100644 index 0000000..6974e22 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_unions.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_multiple_unions.h" +// Function under test: +// union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_vectors.c new file mode 100644 index 0000000..d0257af --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_vectors.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_multiple_vectors.h" +// Function under test: +// int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_with_small_abi_vlen.c new file mode 100644 index 0000000..5e566db --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_with_small_abi_vlen.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_multiple_with_small_abi_vlen.h" +// Function under test: +// int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2, +// int32x4_t v3, int32x4_t v4) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion.c new file mode 100644 index 0000000..5fe493b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_register_exhaustion.h" +// Function under test: +// int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, +// int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, +// int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, +// int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, +// int32x4_t v17) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion_mixed.c new file mode 100644 index 0000000..4b484d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion_mixed.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_register_exhaustion_mixed.h" +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_pressure_scenarios.c new file mode 100644 index 0000000..5bcd85c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_pressure_scenarios.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_register_pressure_scenarios.h" +// Function under test: +// void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2, +// int32x4_t medium1, int32x4_t medium2, +// int32x8_t large1) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ medium2 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ large1 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_same_vectors_struct.c new file mode 100644 index 0000000..eae391f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_same_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_same_vectors_struct.h" +// Function under test: +// struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_simple_union.c new file mode 100644 index 0000000..b3dcc28 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_simple_union.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_simple_union.h" +// Function under test: +// union_vector_t test_simple_union(union_vector_t u) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_register.c new file mode 100644 index 0000000..af8afb2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_register.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_single_register.h" +// Function under test: +// int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_vector_struct.c new file mode 100644 index 0000000..32c31920 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_vector_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_single_vector_struct.h" +// Function under test: +// struct_single_vector_t test_single_vector_struct(struct_single_vector_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_different_abi_vlen.c new file mode 100644 index 0000000..615ed1d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_different_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_struct_different_abi_vlen.h" +// Function under test: +// two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_eight_128bit_vectors.c new file mode 100644 index 0000000..0ceab39 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_eight_128bit_vectors.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_struct_eight_128bit_vectors.h" +// Function under test: +// eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v10 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v11 \[ s\+48 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v12 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v13 \[ s\+80 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v14 \[ s\+96 \]\)\)} "expand" } } */ +// Check argument 8 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v15 \[ s\+112 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_five_256bit_vectors.c new file mode 100644 index 0000000..d41c3de --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_five_256bit_vectors.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_struct_five_256bit_vectors.h" +// Function under test: +// five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v12 \[ s\+128 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_four_256bit_vectors.c new file mode 100644 index 0000000..50360c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_four_256bit_vectors.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_struct_four_256bit_vectors.h" +// Function under test: +// four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_nine_128bit_vectors.c new file mode 100644 index 0000000..7d75572 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_nine_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_struct_nine_128bit_vectors.h" +// Function under test: +// nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_two_registers.c new file mode 100644 index 0000000..8eda297 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_two_registers.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_two_registers.h" +// Function under test: +// int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_vector_array_struct.c new file mode 100644 index 0000000..e006469 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_vector_array_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_vector_array_struct.h" +// Function under test: +// struct_vector_array_t test_vector_array_struct(struct_vector_array_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_128bit_vector.c new file mode 100644 index 0000000..905a938 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_128bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_128bit_vector.h" +// Function under test: +// int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_256bit_vector.c new file mode 100644 index 0000000..ba3692d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_256bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_256bit_vector.h" +// Function under test: +// int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_32bit_vector.c new file mode 100644 index 0000000..09a3fa0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_32bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_32bit_vector.h" +// Function under test: +// int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_64bit_vector.c new file mode 100644 index 0000000..458541c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_64bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_64bit_vector.h" +// Function under test: +// int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_all_mixed.c new file mode 100644 index 0000000..89037c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_all_mixed.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_all_mixed.h" +// Function under test: +// double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_call_mixed_function.c new file mode 100644 index 0000000..8658b79 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_call_mixed_function.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_call_mixed_function.h" +// Function under test: +// int helper_mixed_function(int i, int32x4_t v, float f) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vector_elements.c new file mode 100644 index 0000000..662ce5c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vector_elements.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_different_vector_elements.h" +// Function under test: +// int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec, +// int32x4_t int_vec, int64x2_t long_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v9 \[ short_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ int_vec \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v11 \[ long_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vectors_struct.c new file mode 100644 index 0000000..66371f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_different_vectors_struct.h" +// Function under test: +// struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_width_vectors_struct.c new file mode 100644 index 0000000..2888f17 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_width_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_different_width_vectors_struct.h" +// Function under test: +// different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+\)[[:space:]]+\(reg:V8HI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_equivalent_struct.c new file mode 100644 index 0000000..4f7b64b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_equivalent_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_equivalent_struct.h" +// Function under test: +// equivalent_struct_t test_equivalent_struct(equivalent_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_four_registers.c new file mode 100644 index 0000000..4cbb415 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_four_registers.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_four_registers.h" +// Function under test: +// int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_fp_vs_int_vectors.c new file mode 100644 index 0000000..4a7d548 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_fp_vs_int_vectors.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_fp_vs_int_vectors.h" +// Function under test: +// float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec, +// double64x2_t double_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ float_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v10 \[ double_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_large_vector_small_abi_vlen.c new file mode 100644 index 0000000..adf003c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_large_vector_small_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_large_vector_small_abi_vlen.h" +// Function under test: +// int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_args.c new file mode 100644 index 0000000..7695777 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_args.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_mixed_args.h" +// Function under test: +// int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_float_vector.c new file mode 100644 index 0000000..8811b6f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_float_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_mixed_float_vector.h" +// Function under test: +// float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_int_vector.c new file mode 100644 index 0000000..29753e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_int_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_mixed_int_vector.h" +// Function under test: +// int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct.c new file mode 100644 index 0000000..113be1e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_mixed_struct.h" +// Function under test: +// struct_mixed_t test_mixed_struct(struct_mixed_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct_advanced.c new file mode 100644 index 0000000..be8fdca --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct_advanced.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_mixed_struct_advanced.h" +// Function under test: +// mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_vector_types_struct.c new file mode 100644 index 0000000..7ae31a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_vector_types_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_mixed_vector_types_struct.h" +// Function under test: +// mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+\)[[:space:]]+\(reg:V4SF \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_unions.c new file mode 100644 index 0000000..232afe4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_unions.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_multiple_unions.h" +// Function under test: +// union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_vectors.c new file mode 100644 index 0000000..bbc2b80 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_vectors.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_multiple_vectors.h" +// Function under test: +// int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_with_small_abi_vlen.c new file mode 100644 index 0000000..2fcc2d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_with_small_abi_vlen.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_multiple_with_small_abi_vlen.h" +// Function under test: +// int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2, +// int32x4_t v3, int32x4_t v4) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion.c new file mode 100644 index 0000000..489ea6f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_register_exhaustion.h" +// Function under test: +// int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, +// int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, +// int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, +// int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, +// int32x4_t v17) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion_mixed.c new file mode 100644 index 0000000..195d264 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion_mixed.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_register_exhaustion_mixed.h" +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_pressure_scenarios.c new file mode 100644 index 0000000..78f336d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_pressure_scenarios.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_register_pressure_scenarios.h" +// Function under test: +// void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2, +// int32x4_t medium1, int32x4_t medium2, +// int32x8_t large1) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ medium2 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ large1 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_same_vectors_struct.c new file mode 100644 index 0000000..9226884 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_same_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_same_vectors_struct.h" +// Function under test: +// struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_simple_union.c new file mode 100644 index 0000000..409b863 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_simple_union.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_simple_union.h" +// Function under test: +// union_vector_t test_simple_union(union_vector_t u) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_register.c new file mode 100644 index 0000000..1fb5c69 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_register.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_single_register.h" +// Function under test: +// int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_vector_struct.c new file mode 100644 index 0000000..68da0d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_vector_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_single_vector_struct.h" +// Function under test: +// struct_single_vector_t test_single_vector_struct(struct_single_vector_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_different_abi_vlen.c new file mode 100644 index 0000000..0306514 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_different_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_struct_different_abi_vlen.h" +// Function under test: +// two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_eight_128bit_vectors.c new file mode 100644 index 0000000..ae6da97 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_eight_128bit_vectors.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_struct_eight_128bit_vectors.h" +// Function under test: +// eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v10 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v11 \[ s\+48 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v12 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v13 \[ s\+80 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v14 \[ s\+96 \]\)\)} "expand" } } */ +// Check argument 8 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v15 \[ s\+112 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_five_256bit_vectors.c new file mode 100644 index 0000000..037f2ae --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_five_256bit_vectors.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_struct_five_256bit_vectors.h" +// Function under test: +// five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v12 \[ s\+128 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_four_256bit_vectors.c new file mode 100644 index 0000000..3027ab1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_four_256bit_vectors.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_struct_four_256bit_vectors.h" +// Function under test: +// four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_nine_128bit_vectors.c new file mode 100644 index 0000000..3032001 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_nine_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_struct_nine_128bit_vectors.h" +// Function under test: +// nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_two_registers.c new file mode 100644 index 0000000..698664a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_two_registers.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_two_registers.h" +// Function under test: +// int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_vector_array_struct.c new file mode 100644 index 0000000..c7663f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_vector_array_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_vector_array_struct.h" +// Function under test: +// struct_vector_array_t test_vector_array_struct(struct_vector_array_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_128bit_vector.c new file mode 100644 index 0000000..7a35b97 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_128bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_128bit_vector.h" +// Function under test: +// int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_256bit_vector.c new file mode 100644 index 0000000..b6acb4e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_256bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_256bit_vector.h" +// Function under test: +// int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_32bit_vector.c new file mode 100644 index 0000000..29a1542 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_32bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_32bit_vector.h" +// Function under test: +// int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_64bit_vector.c new file mode 100644 index 0000000..8dd0416 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_64bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_64bit_vector.h" +// Function under test: +// int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_all_mixed.c new file mode 100644 index 0000000..471ac7a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_all_mixed.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_all_mixed.h" +// Function under test: +// double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_call_mixed_function.c new file mode 100644 index 0000000..e0823a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_call_mixed_function.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_call_mixed_function.h" +// Function under test: +// int helper_mixed_function(int i, int32x4_t v, float f) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vector_elements.c new file mode 100644 index 0000000..e014d94 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vector_elements.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_different_vector_elements.h" +// Function under test: +// int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec, +// int32x4_t int_vec, int64x2_t long_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v10 \[ short_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ int_vec \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v14 \[ long_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vectors_struct.c new file mode 100644 index 0000000..3bfc462 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_different_vectors_struct.h" +// Function under test: +// struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_width_vectors_struct.c new file mode 100644 index 0000000..3d29761 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_width_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_different_width_vectors_struct.h" +// Function under test: +// different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_equivalent_struct.c new file mode 100644 index 0000000..cbef719 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_equivalent_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_equivalent_struct.h" +// Function under test: +// equivalent_struct_t test_equivalent_struct(equivalent_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_four_registers.c new file mode 100644 index 0000000..96d92ca --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_four_registers.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_four_registers.h" +// Function under test: +// int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_fp_vs_int_vectors.c new file mode 100644 index 0000000..4f508e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_fp_vs_int_vectors.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_fp_vs_int_vectors.h" +// Function under test: +// float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec, +// double64x2_t double_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v10 \[ float_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v12 \[ double_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_large_vector_small_abi_vlen.c new file mode 100644 index 0000000..7de41a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_large_vector_small_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_large_vector_small_abi_vlen.h" +// Function under test: +// int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_args.c new file mode 100644 index 0000000..dc83d6e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_args.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_mixed_args.h" +// Function under test: +// int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_float_vector.c new file mode 100644 index 0000000..86f7a14 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_float_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_mixed_float_vector.h" +// Function under test: +// float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_int_vector.c new file mode 100644 index 0000000..ca07249 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_int_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_mixed_int_vector.h" +// Function under test: +// int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct.c new file mode 100644 index 0000000..1247eed --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_mixed_struct.h" +// Function under test: +// struct_mixed_t test_mixed_struct(struct_mixed_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct_advanced.c new file mode 100644 index 0000000..99b5313 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct_advanced.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_mixed_struct_advanced.h" +// Function under test: +// mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_vector_types_struct.c new file mode 100644 index 0000000..a125bd8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_vector_types_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_mixed_vector_types_struct.h" +// Function under test: +// mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_unions.c new file mode 100644 index 0000000..e6af0c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_unions.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_multiple_unions.h" +// Function under test: +// union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_vectors.c new file mode 100644 index 0000000..403aee0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_multiple_vectors.h" +// Function under test: +// int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_with_small_abi_vlen.c new file mode 100644 index 0000000..91998a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_with_small_abi_vlen.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_multiple_with_small_abi_vlen.h" +// Function under test: +// int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2, +// int32x4_t v3, int32x4_t v4) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion.c new file mode 100644 index 0000000..6805d40 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_register_exhaustion.h" +// Function under test: +// int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, +// int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, +// int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, +// int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, +// int32x4_t v17) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v8 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion_mixed.c new file mode 100644 index 0000000..f15093d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion_mixed.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_register_exhaustion_mixed.h" +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v8 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_pressure_scenarios.c new file mode 100644 index 0000000..734b067 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_pressure_scenarios.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_register_pressure_scenarios.h" +// Function under test: +// void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2, +// int32x4_t medium1, int32x4_t medium2, +// int32x8_t large1) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ medium2 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v16 \[ large1 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_same_vectors_struct.c new file mode 100644 index 0000000..d28675d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_same_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_same_vectors_struct.h" +// Function under test: +// struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_simple_union.c new file mode 100644 index 0000000..134c809 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_simple_union.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_simple_union.h" +// Function under test: +// union_vector_t test_simple_union(union_vector_t u) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_register.c new file mode 100644 index 0000000..c2a5747b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_register.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_single_register.h" +// Function under test: +// int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_vector_struct.c new file mode 100644 index 0000000..892daa0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_vector_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_single_vector_struct.h" +// Function under test: +// struct_single_vector_t test_single_vector_struct(struct_single_vector_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_different_abi_vlen.c new file mode 100644 index 0000000..9b19e20 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_different_abi_vlen.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_struct_different_abi_vlen.h" +// Function under test: +// two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_eight_128bit_vectors.c new file mode 100644 index 0000000..9172575 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_eight_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_struct_eight_128bit_vectors.h" +// Function under test: +// eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_five_256bit_vectors.c new file mode 100644 index 0000000..bbf8033 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_five_256bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_struct_five_256bit_vectors.h" +// Function under test: +// five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_four_256bit_vectors.c new file mode 100644 index 0000000..980e363 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_four_256bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_struct_four_256bit_vectors.h" +// Function under test: +// four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_nine_128bit_vectors.c new file mode 100644 index 0000000..8b0e14c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_nine_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_struct_nine_128bit_vectors.h" +// Function under test: +// nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_two_registers.c new file mode 100644 index 0000000..61c7280 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_two_registers.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_two_registers.h" +// Function under test: +// int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_vector_array_struct.c new file mode 100644 index 0000000..22f7dc3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_vector_array_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_vector_array_struct.h" +// Function under test: +// struct_vector_array_t test_vector_array_struct(struct_vector_array_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_128bit_vector.c new file mode 100644 index 0000000..d61053a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_128bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_128bit_vector.h" +// Function under test: +// int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_256bit_vector.c new file mode 100644 index 0000000..59a97df --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_256bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_256bit_vector.h" +// Function under test: +// int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_32bit_vector.c new file mode 100644 index 0000000..71553f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_32bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_32bit_vector.h" +// Function under test: +// int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_64bit_vector.c new file mode 100644 index 0000000..8d46ab8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_64bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_64bit_vector.h" +// Function under test: +// int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_all_mixed.c new file mode 100644 index 0000000..00c3e18 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_all_mixed.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_all_mixed.h" +// Function under test: +// double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_call_mixed_function.c new file mode 100644 index 0000000..0f9a1f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_call_mixed_function.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_call_mixed_function.h" +// Function under test: +// int helper_mixed_function(int i, int32x4_t v, float f) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vector_elements.c new file mode 100644 index 0000000..f2c8506 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vector_elements.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_different_vector_elements.h" +// Function under test: +// int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec, +// int32x4_t int_vec, int64x2_t long_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v10 \[ short_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ int_vec \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v14 \[ long_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vectors_struct.c new file mode 100644 index 0000000..64f917f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_different_vectors_struct.h" +// Function under test: +// struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_width_vectors_struct.c new file mode 100644 index 0000000..6757c1f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_width_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_different_width_vectors_struct.h" +// Function under test: +// different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_equivalent_struct.c new file mode 100644 index 0000000..b30f25f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_equivalent_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_equivalent_struct.h" +// Function under test: +// equivalent_struct_t test_equivalent_struct(equivalent_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_four_registers.c new file mode 100644 index 0000000..2d0f69a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_four_registers.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_four_registers.h" +// Function under test: +// int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_fp_vs_int_vectors.c new file mode 100644 index 0000000..f9f846a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_fp_vs_int_vectors.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_fp_vs_int_vectors.h" +// Function under test: +// float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec, +// double64x2_t double_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v10 \[ float_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v12 \[ double_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_large_vector_small_abi_vlen.c new file mode 100644 index 0000000..3c76859 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_large_vector_small_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_large_vector_small_abi_vlen.h" +// Function under test: +// int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_args.c new file mode 100644 index 0000000..b596feb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_args.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_mixed_args.h" +// Function under test: +// int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_float_vector.c new file mode 100644 index 0000000..d68dcef --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_float_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_mixed_float_vector.h" +// Function under test: +// float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_int_vector.c new file mode 100644 index 0000000..69f03db --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_int_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_mixed_int_vector.h" +// Function under test: +// int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct.c new file mode 100644 index 0000000..c8523aa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_mixed_struct.h" +// Function under test: +// struct_mixed_t test_mixed_struct(struct_mixed_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct_advanced.c new file mode 100644 index 0000000..08466aa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct_advanced.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_mixed_struct_advanced.h" +// Function under test: +// mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_vector_types_struct.c new file mode 100644 index 0000000..70ad96e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_vector_types_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_mixed_vector_types_struct.h" +// Function under test: +// mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_unions.c new file mode 100644 index 0000000..44de280 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_unions.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_multiple_unions.h" +// Function under test: +// union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_vectors.c new file mode 100644 index 0000000..40c61aa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_multiple_vectors.h" +// Function under test: +// int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_with_small_abi_vlen.c new file mode 100644 index 0000000..e963bb0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_with_small_abi_vlen.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_multiple_with_small_abi_vlen.h" +// Function under test: +// int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2, +// int32x4_t v3, int32x4_t v4) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion.c new file mode 100644 index 0000000..71c2383 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_register_exhaustion.h" +// Function under test: +// int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, +// int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, +// int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, +// int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, +// int32x4_t v17) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v8 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion_mixed.c new file mode 100644 index 0000000..b209eac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion_mixed.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_register_exhaustion_mixed.h" +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v8 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_pressure_scenarios.c new file mode 100644 index 0000000..bd31c14 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_pressure_scenarios.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_register_pressure_scenarios.h" +// Function under test: +// void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2, +// int32x4_t medium1, int32x4_t medium2, +// int32x8_t large1) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ medium2 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v16 \[ large1 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_same_vectors_struct.c new file mode 100644 index 0000000..2fe18f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_same_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_same_vectors_struct.h" +// Function under test: +// struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_simple_union.c new file mode 100644 index 0000000..c5c3816 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_simple_union.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_simple_union.h" +// Function under test: +// union_vector_t test_simple_union(union_vector_t u) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_register.c new file mode 100644 index 0000000..9adf114 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_register.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_single_register.h" +// Function under test: +// int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_vector_struct.c new file mode 100644 index 0000000..acaf297 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_vector_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_single_vector_struct.h" +// Function under test: +// struct_single_vector_t test_single_vector_struct(struct_single_vector_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_different_abi_vlen.c new file mode 100644 index 0000000..3904243 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_different_abi_vlen.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_struct_different_abi_vlen.h" +// Function under test: +// two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_eight_128bit_vectors.c new file mode 100644 index 0000000..e017645 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_eight_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_struct_eight_128bit_vectors.h" +// Function under test: +// eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_five_256bit_vectors.c new file mode 100644 index 0000000..c36af06 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_five_256bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_struct_five_256bit_vectors.h" +// Function under test: +// five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_four_256bit_vectors.c new file mode 100644 index 0000000..c2e65cc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_four_256bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_struct_four_256bit_vectors.h" +// Function under test: +// four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_nine_128bit_vectors.c new file mode 100644 index 0000000..ba015a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_nine_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_struct_nine_128bit_vectors.h" +// Function under test: +// nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_two_registers.c new file mode 100644 index 0000000..a3a7cf9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_two_registers.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_two_registers.h" +// Function under test: +// int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_vector_array_struct.c new file mode 100644 index 0000000..66780fb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_vector_array_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_vector_array_struct.h" +// Function under test: +// struct_vector_array_t test_vector_array_struct(struct_vector_array_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_128bit_vector.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_128bit_vector.h new file mode 100644 index 0000000..0732cf5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_128bit_vector.h @@ -0,0 +1,13 @@ +// Test: Two 128-bit vectors behavior under different ABI_VLEN + +#include "../vls-cc-common.h" + +int32x4_t VLS_CC(ABI_VLEN) test_128bit_vector(int32x4_t vec1, int32x4_t vec2) { + // Two 128-bit vectors: + // - ABI_VLEN=128: each uses 1 vector register (2 total) + // - ABI_VLEN=64: each uses 2 vector registers (4 total) + // - ABI_VLEN=32: each uses 4 vector registers (8 total) + int32x4_t result; + result = vec1 + vec2; + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_256bit_vector.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_256bit_vector.h new file mode 100644 index 0000000..18b99bf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_256bit_vector.h @@ -0,0 +1,14 @@ +// Test: Two 256-bit vectors behavior under different ABI_VLEN + +#include "../vls-cc-common.h" + +int32x8_t VLS_CC(ABI_VLEN) test_256bit_vector(int32x8_t vec1, int32x8_t vec2) { + // Two 256-bit vectors: + // - ABI_VLEN=256: each uses 1 vector register (2 total) + // - ABI_VLEN=128: each uses 2 vector registers (4 total) + // - ABI_VLEN=64: each uses 4 vector registers (8 total) + // - ABI_VLEN=32: each uses 8 vector registers (16 total) + int32x8_t result; + result = vec1 + vec2; + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_32bit_vector.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_32bit_vector.h new file mode 100644 index 0000000..e18b8e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_32bit_vector.h @@ -0,0 +1,13 @@ +// Test: Two 32-bit vectors (very small vectors) + +#include "../vls-cc-common.h" + +int16x2_t VLS_CC(ABI_VLEN) test_32bit_vector(int16x2_t vec1, int16x2_t vec2) { + // Two 32-bit vectors: + // - Each always uses 1 vector register regardless of ABI_VLEN + // - Uses even smaller portion when ABI_VLEN > 32 + int16x2_t result; + result[0] = vec1[0] + vec2[0]; + result[1] = vec1[1] + vec2[1]; + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_64bit_vector.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_64bit_vector.h new file mode 100644 index 0000000..dc3a2c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_64bit_vector.h @@ -0,0 +1,13 @@ +// Test: Two 64-bit vectors (always fit in one register each) + +#include "../vls-cc-common.h" + +int32x2_t VLS_CC(ABI_VLEN) test_64bit_vector(int32x2_t vec1, int32x2_t vec2) { + // Two 64-bit vectors: + // - Each always uses 1 vector register regardless of ABI_VLEN + // - Only uses portion of the register when ABI_VLEN > 64 + int32x2_t result; + result[0] = vec1[0] + vec2[0]; + result[1] = vec1[1] + vec2[1]; + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_all_mixed.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_all_mixed.h new file mode 100644 index 0000000..6cc50b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_all_mixed.h @@ -0,0 +1,13 @@ +// Test: All three types mixed (int, float, vector) + +#include "../vls-cc-common.h" + +double VLS_CC(ABI_VLEN) test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j) { + // int i -> a0 (integer register) + // float f -> fa0 (FP register) + // int32x4_t vec1 -> v8 (vector register) + // double d -> fa1 (FP register) + // float32x4_t vec2 -> v9 (vector register) + // int j -> a1 (integer register) + return i + f + vec1[0] + d + vec2[0] + j; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_call_mixed_function.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_call_mixed_function.h new file mode 100644 index 0000000..e5cd837 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_call_mixed_function.h @@ -0,0 +1,14 @@ +// Test: Function pointers with mixed signatures + +#include "../vls-cc-common.h" + +typedef int (*mixed_func_ptr_t)(int, int32x4_t, float) VLS_CC(ABI_VLEN); + +// Helper function to be called via function pointer +int VLS_CC(ABI_VLEN) helper_mixed_function(int i, int32x4_t v, float f) { + return i + v[0] + (int)f; +} + +int VLS_CC(ABI_VLEN) test_call_mixed_function(mixed_func_ptr_t func, int i, int32x4_t v, float f) { + return func(i, v, f); +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_vector_elements.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_vector_elements.h new file mode 100644 index 0000000..3ef700b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_vector_elements.h @@ -0,0 +1,10 @@ +// Test: Vector types with different element types in same call + +#include "../vls-cc-common.h" + +int VLS_CC(ABI_VLEN) test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec, + int32x4_t int_vec, int64x2_t long_vec) { + // All are 128-bit vectors but with different element types + // Should all use same vector register allocation rules + return byte_vec[0] + short_vec[0] + int_vec[0] + (int)long_vec[0]; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_vectors_struct.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_vectors_struct.h new file mode 100644 index 0000000..b7c1e48 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_vectors_struct.h @@ -0,0 +1,9 @@ +// Test: Struct with different sized vectors - uses hardware FP calling convention + +#include "../vls-cc-common.h" + +struct_different_vectors_t VLS_CC(ABI_VLEN) test_different_vectors_struct(struct_different_vectors_t s) { + // Contains int32x2_t (64 bits) and int32x4_t (128 bits) - different lengths + // Should use hardware floating-point calling convention, not vector registers + return s; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_width_vectors_struct.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_width_vectors_struct.h new file mode 100644 index 0000000..a0b8e15 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_width_vectors_struct.h @@ -0,0 +1,27 @@ +// Test: Struct with two vectors of different widths but same total size +// int32x4_t (128 bits, 4 x 32-bit) and int16x8_t (128 bits, 8 x 16-bit) - both should be flattened + +#include "../vls-cc-common.h" + +typedef struct { + int32x4_t wide_vec; // 128-bit vector with 4 x 32-bit elements + int16x8_t narrow_vec; // 128-bit vector with 8 x 16-bit elements +} different_width_vectors_struct_t; + +different_width_vectors_struct_t VLS_CC(ABI_VLEN) test_different_width_vectors_struct(different_width_vectors_struct_t s) { + // Should be flattened and passed as two separate vector arguments + // wide_vec should use first vector register, narrow_vec should use second vector register + different_width_vectors_struct_t result; + + // Process wide vector: add 100 to each 32-bit element + for (int i = 0; i < 4; i++) { + result.wide_vec[i] = s.wide_vec[i] + 100; + } + + // Process narrow vector: add 10 to each 16-bit element + for (int i = 0; i < 8; i++) { + result.narrow_vec[i] = s.narrow_vec[i] + 10; + } + + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_equivalent_struct.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_equivalent_struct.h new file mode 100644 index 0000000..859fc10 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_equivalent_struct.h @@ -0,0 +1,14 @@ +// Test: Compare struct vs union behavior + +#include "../vls-cc-common.h" + +// Struct equivalent to union (should use vector calling convention) +typedef struct { + int32x4_t vec; +} equivalent_struct_t; + +equivalent_struct_t VLS_CC(ABI_VLEN) test_equivalent_struct(equivalent_struct_t s) { + // This struct should use vector calling convention (flattened) + // Compare behavior with the union version + return s; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_four_registers.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_four_registers.h new file mode 100644 index 0000000..e53d417 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_four_registers.h @@ -0,0 +1,11 @@ +// Test: Two vectors passed in eight registers (<= 4 * ABI_VLEN bits each) +// int32x16_t (512 bits) should use 4 registers each when ABI_VLEN = 128 + +#include "../vls-cc-common.h" + +int32x16_t VLS_CC(ABI_VLEN) test_four_registers(int32x16_t vec1, int32x16_t vec2) { + // Add vectors element-wise + int32x16_t result; + result = vec1 + vec2; + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_fp_vs_int_vectors.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_fp_vs_int_vectors.h new file mode 100644 index 0000000..649dc13 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_fp_vs_int_vectors.h @@ -0,0 +1,10 @@ +// Test: Floating-point vectors vs integer vectors + +#include "../vls-cc-common.h" + +float VLS_CC(ABI_VLEN) test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec, + double64x2_t double_vec) { + // All vectors should use vector registers, regardless of element type + // Element type shouldn't affect register allocation for fixed-length vectors + return int_vec[0] + float_vec[0] + (float)double_vec[0]; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_large_vector_small_abi_vlen.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_large_vector_small_abi_vlen.h new file mode 100644 index 0000000..90627cf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_large_vector_small_abi_vlen.h @@ -0,0 +1,13 @@ +// Test: Two large vectors that might be passed by reference with small ABI_VLEN + +#include "../vls-cc-common.h" + +int32x16_t VLS_CC(ABI_VLEN) test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2) { + // Two 512-bit vectors: + // - ABI_VLEN=128: each uses 4 registers (8 total, fits in available registers) + // - ABI_VLEN=64: each needs 8 registers (16 total, exceeds available, passed by reference) + // - ABI_VLEN=32: each needs 16 registers (32 total, far exceeds available, passed by reference) + int32x16_t result; + result = vec1 + vec2; + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_args.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_args.h new file mode 100644 index 0000000..c6d91e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_args.h @@ -0,0 +1,8 @@ +// Test: Mixed scalar and vector arguments + +#include "../vls-cc-common.h" + +int VLS_CC(ABI_VLEN) test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2) { + // scalars use integer/float registers, vectors use vector registers + return scalar1 + (int)scalar2 + vec1[0] + vec2[0]; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_float_vector.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_float_vector.h new file mode 100644 index 0000000..03ca452 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_float_vector.h @@ -0,0 +1,10 @@ +// Test: Mixed floating-point scalars and vectors + +#include "../vls-cc-common.h" + +float VLS_CC(ABI_VLEN) test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2) { + // Float scalars should use FP registers (fa0, fa1, ...) + // Vectors should use vector registers (v8, v9, ...) + // Different register classes should not interfere + return f1 + (float)d1 + vec[0] + vec2[0]; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_int_vector.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_int_vector.h new file mode 100644 index 0000000..f379534 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_int_vector.h @@ -0,0 +1,10 @@ +// Test: Mixed integer scalars and vectors + +#include "../vls-cc-common.h" + +int VLS_CC(ABI_VLEN) test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2) { + // Scalars should use integer registers (a0, a1, a2, ...) + // Vectors should use vector registers (v8, v9, ...) + // Should not interfere with each other's register allocation + return a + b + vec[0] + vec2[0]; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct.h new file mode 100644 index 0000000..fb289be --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct.h @@ -0,0 +1,8 @@ +// Test: Struct with mixed vector and scalar - uses hardware FP calling convention + +#include "../vls-cc-common.h" + +struct_mixed_t VLS_CC(ABI_VLEN) test_mixed_struct(struct_mixed_t s) { + // Contains vector and scalar - should use hardware FP calling convention + return s; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct_advanced.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct_advanced.h new file mode 100644 index 0000000..5660a16 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct_advanced.h @@ -0,0 +1,15 @@ +// Test: Vector and scalar struct members (advanced mixed struct) + +#include "../vls-cc-common.h" + +typedef struct { + int scalar; + int32x4_t vector; + float fp_scalar; +} mixed_struct_advanced_t; + +mixed_struct_advanced_t VLS_CC(ABI_VLEN) test_mixed_struct_advanced(mixed_struct_advanced_t s) { + // Should use hardware FP calling convention due to mixed types + // Vector part will be treated according to standard struct rules + return s; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_vector_types_struct.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_vector_types_struct.h new file mode 100644 index 0000000..d916423 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_vector_types_struct.h @@ -0,0 +1,23 @@ +// Test: Struct with two vectors of same width but different types +// int32x4_t (128 bits) and float32x4_t (128 bits) - both should be flattened + +#include "../vls-cc-common.h" + +typedef struct { + int32x4_t int_vec; // 128-bit integer vector + float32x4_t float_vec; // 128-bit float vector +} mixed_vector_types_struct_t; + +mixed_vector_types_struct_t VLS_CC(ABI_VLEN) test_mixed_vector_types_struct(mixed_vector_types_struct_t s) { + // Should be flattened and passed as two separate vector arguments + // int_vec should use first vector register, float_vec should use second vector register + mixed_vector_types_struct_t result; + + // Combine the vectors: add 10 to int elements, multiply float elements by 2.0 + for (int i = 0; i < 4; i++) { + result.int_vec[i] = s.int_vec[i] + 10; + result.float_vec[i] = s.float_vec[i] * 2.0f; + } + + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_unions.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_unions.h new file mode 100644 index 0000000..2205020 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_unions.h @@ -0,0 +1,14 @@ +// Test: Multiple union arguments + +#include "../vls-cc-common.h" + +union_vector_t VLS_CC(ABI_VLEN) test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3) { + // All should use integer calling convention + // Should consume integer registers, not vector registers + union_vector_t result; + result.scalars[0] = u1.scalars[0] + u2.scalars[0] + u3.scalars[0]; + result.scalars[1] = u1.scalars[1] + u2.scalars[1] + u3.scalars[1]; + result.scalars[2] = u1.scalars[2] + u2.scalars[2] + u3.scalars[2]; + result.scalars[3] = u1.scalars[3] + u2.scalars[3] + u3.scalars[3]; + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_vectors.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_vectors.h new file mode 100644 index 0000000..96c8009 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_vectors.h @@ -0,0 +1,12 @@ +// Test: Multiple vector arguments consuming available registers + +#include "../vls-cc-common.h" + +int32x4_t VLS_CC(ABI_VLEN) test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3) { + // Each vector uses 1 register, total 3 registers + int32x4_t result = {v1[0] + v2[0] + v3[0], + v1[1] + v2[1] + v3[1], + v1[2] + v2[2] + v3[2], + v1[3] + v2[3] + v3[3]}; + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_with_small_abi_vlen.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_with_small_abi_vlen.h new file mode 100644 index 0000000..39a957e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_with_small_abi_vlen.h @@ -0,0 +1,12 @@ +// Test: Multiple vectors that may exceed register count with small ABI_VLEN + +#include "../vls-cc-common.h" + +int32x4_t VLS_CC(ABI_VLEN) test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2, + int32x4_t v3, int32x4_t v4) { + // With ABI_VLEN=32, each 128-bit vector needs 4 registers + // 4 vectors * 4 registers = 16 registers needed + // Will exceed available vector registers, some passed by reference + int32x4_t result = {v1[0] + v2[0], v1[1] + v3[1], v1[2] + v4[2], v1[3] + v2[3]}; + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion.h new file mode 100644 index 0000000..6662185 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion.h @@ -0,0 +1,15 @@ +// Test: Vector register exhaustion - should fall back to reference passing + +#include "../vls-cc-common.h" + +int32x4_t VLS_CC(ABI_VLEN) test_register_exhaustion( + int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, + int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, + int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, + int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, + int32x4_t v17) { + // First 16 vectors (v1-v16) should use vector registers v8-v23 + // 17th vector (v17) should be passed by reference due to register exhaustion + int32x4_t result = {v1[0] + v17[0], v2[1] + v17[1], v3[2] + v17[2], v4[3] + v17[3]}; + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion_mixed.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion_mixed.h new file mode 100644 index 0000000..3825584 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion_mixed.h @@ -0,0 +1,21 @@ +// Test: Large number of mixed arguments to test register exhaustion + +#include "../vls-cc-common.h" + +int VLS_CC(ABI_VLEN) test_register_exhaustion_mixed( + // Integer arguments (use a0-a7) + int i1, int i2, int i3, int i4, int i5, int i6, int i7, int i8, int i9, + // FP arguments (use fa0-fa7) + float f1, float f2, float f3, float f4, float f5, float f6, float f7, float f8, float f9, + // Vector arguments (use v8-v23, 16 registers available) + int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, + int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, + int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, + int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, + int32x4_t v17 +) { + // i9, f9 should be passed via stack due to integer/FP register exhaustion + // v1-v16 should use vector registers v8-v23 + // v17 should be passed via stack/memory due to vector register exhaustion + return i1 + i9 + (int)f1 + (int)f9 + v1[0] + v17[0]; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_pressure_scenarios.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_pressure_scenarios.h new file mode 100644 index 0000000..e55c56b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_pressure_scenarios.h @@ -0,0 +1,15 @@ +// Test: Function demonstrating register pressure with different ABI_VLEN + +#include "../vls-cc-common.h" + +void VLS_CC(ABI_VLEN) test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2, + int32x4_t medium1, int32x4_t medium2, + int32x8_t large1) { + // Different register consumption based on ABI_VLEN: + // ABI_VLEN=128: 2 * 1 + 2 * 1 + 1 * 2 = 6 registers + // ABI_VLEN=64: 2 * 1 + 2 * 2 + 1 * 4 = 10 registers (exceeds 8, some by reference) + // ABI_VLEN=32: 2 * 2 + 2 * 4 + 1 * 8 = 20 registers (many by reference) + + // Just use the parameters to avoid warnings + (void)small1; (void)small2; (void)medium1; (void)medium2; (void)large1; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_same_vectors_struct.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_same_vectors_struct.h new file mode 100644 index 0000000..d5cd78d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_same_vectors_struct.h @@ -0,0 +1,10 @@ +// Test: Struct with two same-length vectors - should be passed as vector tuple + +#include "../vls-cc-common.h" + +struct_two_same_vectors_t VLS_CC(ABI_VLEN) test_same_vectors_struct(struct_two_same_vectors_t s) { + // Should be passed in vector registers like a vector tuple + // Both vectors are int32x4_t (128 bits each), total 256 bits + // Should use 2 vector registers when ABI_VLEN = 128 + return s; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_simple_union.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_simple_union.h new file mode 100644 index 0000000..09c57c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_simple_union.h @@ -0,0 +1,9 @@ +// Test: Simple union with vector - should use integer calling convention + +#include "../vls-cc-common.h" + +union_vector_t VLS_CC(ABI_VLEN) test_simple_union(union_vector_t u) { + // Union with fixed-length vector should always use integer calling convention + // Should NOT use vector registers, even though it contains a vector + return u; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_single_register.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_single_register.h new file mode 100644 index 0000000..b65a1e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_single_register.h @@ -0,0 +1,11 @@ +// Test: Two vectors passed in registers (<= ABI_VLEN bits each) +// int32x4_t (128 bits) should use 1 register per vector when ABI_VLEN >= 128 + +#include "../vls-cc-common.h" + +int32x4_t VLS_CC(ABI_VLEN) test_single_register(int32x4_t vec1, int32x4_t vec2) { + // Add vectors element-wise + int32x4_t result; + result = vec1 + vec2; + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_single_vector_struct.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_single_vector_struct.h new file mode 100644 index 0000000..7d1d2a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_single_vector_struct.h @@ -0,0 +1,8 @@ +// Test: Struct with single vector - should be flattened + +#include "../vls-cc-common.h" + +struct_single_vector_t VLS_CC(ABI_VLEN) test_single_vector_struct(struct_single_vector_t s) { + // Should be flattened and passed as single vector argument + return s; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_different_abi_vlen.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_different_abi_vlen.h new file mode 100644 index 0000000..b0b388e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_different_abi_vlen.h @@ -0,0 +1,17 @@ +// Test: Struct behavior under different ABI_VLEN + +#include "../vls-cc-common.h" + +typedef struct { + int32x4_t vec1; + int32x4_t vec2; +} two_medium_vectors_t; + +two_medium_vectors_t VLS_CC(ABI_VLEN) test_struct_different_abi_vlen(two_medium_vectors_t s) { + // Struct with 2 * 128-bit vectors (256 bits total): + // - ABI_VLEN=256: fits in single "vector tuple" concept, uses 2 registers + // - ABI_VLEN=128: each vector uses 1 register, total 2 registers + // - ABI_VLEN=64: each vector uses 2 registers, total 4 registers + // - ABI_VLEN=32: each vector uses 4 registers, total 8 registers + return s; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_eight_128bit_vectors.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_eight_128bit_vectors.h new file mode 100644 index 0000000..78b9d50 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_eight_128bit_vectors.h @@ -0,0 +1,38 @@ +// Test: Struct with eight 128-bit vectors +// Each int32x4_t is 128 bits (4 x 32-bit elements) +// Total: 8 vectors * 128 bits = 1024 bits +// With ABI_VLEN=128: 8 vectors * 1 register each = 8 registers (fits in 16 available) + +#include "../vls-cc-common.h" + +typedef struct { + int32x4_t vec1; // 128-bit vector + int32x4_t vec2; // 128-bit vector + int32x4_t vec3; // 128-bit vector + int32x4_t vec4; // 128-bit vector + int32x4_t vec5; // 128-bit vector + int32x4_t vec6; // 128-bit vector + int32x4_t vec7; // 128-bit vector + int32x4_t vec8; // 128-bit vector +} eight_128bit_vectors_struct_t; + +eight_128bit_vectors_struct_t VLS_CC(ABI_VLEN) test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s) { + // Should be flattened and passed as separate vector arguments + // With ABI_VLEN=128: vec1 uses v8, vec2 uses v9, ..., vec8 uses v15 + // Total uses 8 out of 16 available vector argument registers + eight_128bit_vectors_struct_t result; + + // Process each 128-bit vector: multiply by (index + 1) + for (int i = 0; i < 4; i++) { + result.vec1[i] = s.vec1[i] * 1; + result.vec2[i] = s.vec2[i] * 2; + result.vec3[i] = s.vec3[i] * 3; + result.vec4[i] = s.vec4[i] * 4; + result.vec5[i] = s.vec5[i] * 5; + result.vec6[i] = s.vec6[i] * 6; + result.vec7[i] = s.vec7[i] * 7; + result.vec8[i] = s.vec8[i] * 8; + } + + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_five_256bit_vectors.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_five_256bit_vectors.h new file mode 100644 index 0000000..190cafd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_five_256bit_vectors.h @@ -0,0 +1,33 @@ +// Test: Struct with five 256-bit vectors +// Each int32x8_t is 256 bits (8 x 32-bit elements) +// Total: 5 vectors * 256 bits = 1280 bits +// With ABI_VLEN=128: 5 vectors * 2 registers each = 10 registers (fits in 16 available) + +#include "../vls-cc-common.h" + +typedef struct { + int32x8_t vec1; // 256-bit vector + int32x8_t vec2; // 256-bit vector + int32x8_t vec3; // 256-bit vector + int32x8_t vec4; // 256-bit vector + int32x8_t vec5; // 256-bit vector +} five_256bit_vectors_struct_t; + +five_256bit_vectors_struct_t VLS_CC(ABI_VLEN) test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s) { + // Should be flattened and passed as separate vector arguments + // With ABI_VLEN=128: vec1 uses v8+v9, vec2 uses v10+v11, vec3 uses v12+v13, + // vec4 uses v14+v15, vec5 uses v16+v17 + // Total uses 10 out of 16 available vector argument registers + five_256bit_vectors_struct_t result; + + // Process each 256-bit vector: add different values to each vector + for (int i = 0; i < 8; i++) { + result.vec1[i] = s.vec1[i] + 1000; + result.vec2[i] = s.vec2[i] + 2000; + result.vec3[i] = s.vec3[i] + 3000; + result.vec4[i] = s.vec4[i] + 4000; + result.vec5[i] = s.vec5[i] + 5000; + } + + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_four_256bit_vectors.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_four_256bit_vectors.h new file mode 100644 index 0000000..02e9cfe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_four_256bit_vectors.h @@ -0,0 +1,30 @@ +// Test: Struct with four 256-bit vectors +// Each int32x8_t is 256 bits (8 x 32-bit elements) +// Total: 4 vectors * 256 bits = 1024 bits +// With ABI_VLEN=128: 4 vectors * 2 registers each = 8 registers (fits in 16 available) + +#include "../vls-cc-common.h" + +typedef struct { + int32x8_t vec1; // 256-bit vector + int32x8_t vec2; // 256-bit vector + int32x8_t vec3; // 256-bit vector + int32x8_t vec4; // 256-bit vector +} four_256bit_vectors_struct_t; + +four_256bit_vectors_struct_t VLS_CC(ABI_VLEN) test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s) { + // Should be flattened and passed as separate vector arguments + // With ABI_VLEN=128: vec1 uses v8+v9, vec2 uses v10+v11, vec3 uses v12+v13, vec4 uses v14+v15 + // With ABI_VLEN=256: vec1 uses v8, vec2 uses v9, vec3 uses v10, vec4 uses v11 + four_256bit_vectors_struct_t result; + + // Process each 256-bit vector: add 100 to first element, add 200 to second element, etc. + for (int i = 0; i < 8; i++) { + result.vec1[i] = s.vec1[i] + 100; + result.vec2[i] = s.vec2[i] + 200; + result.vec3[i] = s.vec3[i] + 300; + result.vec4[i] = s.vec4[i] + 400; + } + + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_nine_128bit_vectors.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_nine_128bit_vectors.h new file mode 100644 index 0000000..fe77bc8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_nine_128bit_vectors.h @@ -0,0 +1,40 @@ +// Test: Struct with nine 128-bit vectors +// Each int32x4_t is 128 bits (4 x 32-bit elements) +// Total: 9 vectors * 128 bits = 1152 bits +// With ABI_VLEN=128: 9 vectors * 1 register each = 9 registers (fits in 16 available) + +#include "../vls-cc-common.h" + +typedef struct { + int32x4_t vec1; // 128-bit vector + int32x4_t vec2; // 128-bit vector + int32x4_t vec3; // 128-bit vector + int32x4_t vec4; // 128-bit vector + int32x4_t vec5; // 128-bit vector + int32x4_t vec6; // 128-bit vector + int32x4_t vec7; // 128-bit vector + int32x4_t vec8; // 128-bit vector + int32x4_t vec9; // 128-bit vector +} nine_128bit_vectors_struct_t; + +nine_128bit_vectors_struct_t VLS_CC(ABI_VLEN) test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s) { + // Should be flattened and passed as separate vector arguments + // With ABI_VLEN=128: vec1 uses v8, vec2 uses v9, ..., vec9 uses v16 + // Total uses 9 out of 16 available vector argument registers + nine_128bit_vectors_struct_t result; + + // Process each 128-bit vector: add vector index * 100 to each element + for (int i = 0; i < 4; i++) { + result.vec1[i] = s.vec1[i] + 100; + result.vec2[i] = s.vec2[i] + 200; + result.vec3[i] = s.vec3[i] + 300; + result.vec4[i] = s.vec4[i] + 400; + result.vec5[i] = s.vec5[i] + 500; + result.vec6[i] = s.vec6[i] + 600; + result.vec7[i] = s.vec7[i] + 700; + result.vec8[i] = s.vec8[i] + 800; + result.vec9[i] = s.vec9[i] + 900; + } + + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_two_registers.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_two_registers.h new file mode 100644 index 0000000..b9fe523 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_two_registers.h @@ -0,0 +1,8 @@ +// Test: Vector passed in two registers (<= 2 * ABI_VLEN bits) +// int32x8_t (256 bits) should use 2 registers when ABI_VLEN = 128 + +#include "../vls-cc-common.h" + +int32x8_t VLS_CC(ABI_VLEN) test_two_registers(int32x8_t vec, int32x8_t vec2) { + return vec + vec2; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_vector_array_struct.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_vector_array_struct.h new file mode 100644 index 0000000..77a84d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_vector_array_struct.h @@ -0,0 +1,9 @@ +// Test: Struct with vector array - should be passed as vector tuple + +#include "../vls-cc-common.h" + +struct_vector_array_t VLS_CC(ABI_VLEN) test_vector_array_struct(struct_vector_array_t s) { + // Array of 2 int32x4_t vectors, should be passed as vector tuple + // Total size: 256 bits, should use 2 vector registers + return s; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/riscv-vls-cc.exp b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/riscv-vls-cc.exp new file mode 100644 index 0000000..68b4067 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/riscv-vls-cc.exp @@ -0,0 +1,63 @@ +# Copyright (C) 2025 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't a RISC-V target. +if ![istarget riscv*-*-*] then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# If a testcase doesn't have special options, use these. +global DEFAULT_CFLAGS +if ![info exists DEFAULT_CFLAGS] then { + set DEFAULT_CFLAGS " -ansi -pedantic-errors" +} + +# Initialize `dg'. +dg-init + +# Main loop. +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS + +# Test for specific XLEN and VLEN. +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-32-xlen-32/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-32-xlen-64/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-64-xlen-32/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-64-xlen-64/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-128-xlen-32/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-128-xlen-64/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-256-xlen-32/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-256-xlen-64/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-512-xlen-32/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-512-xlen-64/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS + +# All done. +dg-finish diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_large_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_large_vector.c new file mode 100644 index 0000000..69a47ad --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_large_vector.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +// Test: Large vector with ABI_VLEN=128 + +#include "vls-cc-common.h" + +int32x8_t __attribute__((riscv_vls_cc(128))) test_128_abi_vlen_large_vector(int32x8_t vec) { + // 256-bit vector with ABI_VLEN=128 -> uses 2 registers + return vec; +} +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_medium_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_medium_vector.c new file mode 100644 index 0000000..3c179d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_medium_vector.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +// Test: Medium vector with ABI_VLEN=128 + +#include "vls-cc-common.h" + +int32x4_t __attribute__((riscv_vls_cc(128))) test_128_abi_vlen_medium_vector(int32x4_t vec) { + // 128-bit vector with ABI_VLEN=128 -> uses 1 register + return vec; +} +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_large_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_large_vector.c new file mode 100644 index 0000000..ba0630d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_large_vector.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +// Test: Large vector with ABI_VLEN=256 + +#include "vls-cc-common.h" + +int32x8_t __attribute__((riscv_vls_cc(256))) test_256_abi_vlen_large_vector(int32x8_t vec) { + // 256-bit vector with ABI_VLEN=256 -> uses 1 register + return vec; +} +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_very_large_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_very_large_vector.c new file mode 100644 index 0000000..503f9ce --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_very_large_vector.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +// Test: Very large vector with ABI_VLEN=256 + +#include "vls-cc-common.h" + +int32x16_t __attribute__((riscv_vls_cc(256))) test_256_abi_vlen_very_large_vector(int32x16_t vec) { + // 512-bit vector with ABI_VLEN=256 -> uses 2 registers + return vec; +} +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ v8\)[[:space:]]+\(reg.*:V16SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_medium_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_medium_vector.c new file mode 100644 index 0000000..496b77c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_medium_vector.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +// Test: Medium vector with ABI_VLEN=32 + +#include "vls-cc-common.h" + +int32x4_t __attribute__((riscv_vls_cc(32))) test_32_abi_vlen_medium_vector(int32x4_t vec) { + // 128-bit vector with ABI_VLEN=32 -> uses 4 registers + return vec; +} +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_small_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_small_vector.c new file mode 100644 index 0000000..1b44a09 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_small_vector.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +// Test: Small vector with ABI_VLEN=32 + +#include "vls-cc-common.h" + +int32x2_t __attribute__((riscv_vls_cc(32))) test_32_abi_vlen_small_vector(int32x2_t vec) { + // 64-bit vector with ABI_VLEN=32 -> uses 2 registers + return vec; +} +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_medium_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_medium_vector.c new file mode 100644 index 0000000..c1f3673 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_medium_vector.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +// Test: Medium vector with ABI_VLEN=64 + +#include "vls-cc-common.h" + +int32x4_t __attribute__((riscv_vls_cc(64))) test_64_abi_vlen_medium_vector(int32x4_t vec) { + // 128-bit vector with ABI_VLEN=64 -> uses 2 registers + return vec; +} +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_small_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_small_vector.c new file mode 100644 index 0000000..241e897 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_small_vector.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +// Test: Small vector with ABI_VLEN=64 + +#include "vls-cc-common.h" + +int32x2_t __attribute__((riscv_vls_cc(64))) test_64_abi_vlen_small_vector(int32x2_t vec) { + // 64-bit vector with ABI_VLEN=64 -> uses 1 register + return vec; +} +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/vls-cc-common.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/vls-cc-common.h new file mode 100644 index 0000000..105f5a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/vls-cc-common.h @@ -0,0 +1,125 @@ +#ifndef VLS_CC_COMMON_H +#define VLS_CC_COMMON_H + +#include <stdint-gcc.h> + +// Check if ABI_VLEN is defined +#ifndef ABI_VLEN +#define ABI_VLEN 128 // Default fallback value +#endif + +// VLS Calling Convention attribute macro +#define VLS_CC(ABI_VLEN) \ + __attribute__((riscv_vls_cc(ABI_VLEN))) + +// Fixed-length vector type definitions following <basetype><width>x<num>_t naming convention +// These use GCC/Clang __attribute__((vector_size(N))) extension + +// 8-bit integer vectors +typedef int8_t int8x2_t __attribute__((vector_size(2))); +typedef int8_t int8x4_t __attribute__((vector_size(4))); +typedef int8_t int8x8_t __attribute__((vector_size(8))); +typedef int8_t int8x16_t __attribute__((vector_size(16))); +typedef int8_t int8x32_t __attribute__((vector_size(32))); +typedef int8_t int8x64_t __attribute__((vector_size(64))); + +typedef uint8_t uint8x2_t __attribute__((vector_size(2))); +typedef uint8_t uint8x4_t __attribute__((vector_size(4))); +typedef uint8_t uint8x8_t __attribute__((vector_size(8))); +typedef uint8_t uint8x16_t __attribute__((vector_size(16))); +typedef uint8_t uint8x32_t __attribute__((vector_size(32))); +typedef uint8_t uint8x64_t __attribute__((vector_size(64))); + +// 16-bit integer vectors +typedef int16_t int16x2_t __attribute__((vector_size(4))); +typedef int16_t int16x4_t __attribute__((vector_size(8))); +typedef int16_t int16x8_t __attribute__((vector_size(16))); +typedef int16_t int16x16_t __attribute__((vector_size(32))); +typedef int16_t int16x32_t __attribute__((vector_size(64))); + +typedef uint16_t uint16x2_t __attribute__((vector_size(4))); +typedef uint16_t uint16x4_t __attribute__((vector_size(8))); +typedef uint16_t uint16x8_t __attribute__((vector_size(16))); +typedef uint16_t uint16x16_t __attribute__((vector_size(32))); +typedef uint16_t uint16x32_t __attribute__((vector_size(64))); + +// 32-bit integer vectors +typedef int32_t int32x2_t __attribute__((vector_size(8))); +typedef int32_t int32x4_t __attribute__((vector_size(16))); +typedef int32_t int32x8_t __attribute__((vector_size(32))); +typedef int32_t int32x16_t __attribute__((vector_size(64))); + +typedef uint32_t uint32x2_t __attribute__((vector_size(8))); +typedef uint32_t uint32x4_t __attribute__((vector_size(16))); +typedef uint32_t uint32x8_t __attribute__((vector_size(32))); +typedef uint32_t uint32x16_t __attribute__((vector_size(64))); + +// 64-bit integer vectors +typedef int64_t int64x2_t __attribute__((vector_size(16))); +typedef int64_t int64x4_t __attribute__((vector_size(32))); +typedef int64_t int64x8_t __attribute__((vector_size(64))); + +typedef uint64_t uint64x2_t __attribute__((vector_size(16))); +typedef uint64_t uint64x4_t __attribute__((vector_size(32))); +typedef uint64_t uint64x8_t __attribute__((vector_size(64))); + +// Floating-point vectors (following the same pattern) +typedef float float32x2_t __attribute__((vector_size(8))); +typedef float float32x4_t __attribute__((vector_size(16))); +typedef float float32x8_t __attribute__((vector_size(32))); +typedef float float32x16_t __attribute__((vector_size(64))); + +typedef double double64x2_t __attribute__((vector_size(16))); +typedef double double64x4_t __attribute__((vector_size(32))); +typedef double double64x8_t __attribute__((vector_size(64))); + +// Test structures containing fixed-length vectors +typedef struct { + int32x4_t vec1; + int32x4_t vec2; +} struct_two_same_vectors_t; + +typedef struct { + int32x4_t vec; +} struct_single_vector_t; + +typedef struct { + int32x4_t vec_array[2]; +} struct_vector_array_t; + +typedef struct { + int32x2_t vec1; + int32x4_t vec2; // Different sizes +} struct_different_vectors_t; + +typedef struct { + int32x4_t vec; + int scalar; +} struct_mixed_t; + +// Union containing fixed-length vectors (always uses integer calling convention) +typedef union { + int32x4_t vec; + int32_t scalars[4]; +} union_vector_t; + +// Function pointer types for testing +typedef int32x4_t (*func_return_vector_t)(int32x4_t); +typedef void (*func_pass_vector_t)(int32x4_t); +typedef struct_single_vector_t (*func_return_struct_t)(struct_single_vector_t); + +// Test constants for initialization +#define INIT_INT32X4(a, b, c, d) (int32x4_t){a, b, c, d} +#define INIT_FLOAT32X4(a, b, c, d) (float32x4_t){a, b, c, d} +#define INIT_INT16X8(a, b, c, d, e, f, g, h) (int16x8_t){a, b, c, d, e, f, g, h} + +#ifdef SUPPORT_NON_POWER_OF_2_VEC +#define INIT_INT32X3(a, b, c) (int32x3_t){a, b, c} +#define INIT_FLOAT32X3(a, b, c) (float32x3_t){a, b, c} +#endif + +// Utility macros for vector operations testing +#define VEC_SIZE_BYTES(type) sizeof(type) +#define VEC_ELEMENT_COUNT(type, element_type) (sizeof(type) / sizeof(element_type)) + +#endif // VLS_CC_COMMON_H diff --git a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-01.c b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-01.c index f9f3222..9d8a772 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-01.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-01.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-g" "-Oz" "-Os" } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-g" "-O1" "-Oz" "-Os" } } */ int foo1(int rs1) { diff --git a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-02.c b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-02.c index 112c0fa..430d998 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-02.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-02.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gc_zbb -mabi=ilp32" } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-g" "-Oz" "-Os" } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-g" "-O1" "-Oz" "-Os" } } */ int foo1(int rs1) { diff --git a/gcc/testsuite/gcc.target/xtensa/one_cmpl_abs.c b/gcc/testsuite/gcc.target/xtensa/one_cmpl_abs.c deleted file mode 100644 index 608f65f..0000000 --- a/gcc/testsuite/gcc.target/xtensa/one_cmpl_abs.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O1" } */ - -int one_cmpl_abs(int a) -{ - return a < 0 ? ~a : a; -} - -/* { dg-final { scan-assembler-not "bgez" } } */ diff --git a/gcc/testsuite/gfortran.dg/is_contiguous_5.f90 b/gcc/testsuite/gfortran.dg/is_contiguous_5.f90 new file mode 100644 index 0000000..091e43b5 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/is_contiguous_5.f90 @@ -0,0 +1,126 @@ +! { dg-do run } +! PR fortran/114023 - IS_CONTIGUOUS and pointers to non-contiguous targets +! +! Based on testcase by Federico Perini + +program main + implicit none + complex, parameter :: cvals(*) = [(1,-1),(2,-2),(3,-3)] + complex , target :: cref(size(cvals)) = cvals ! Reference + complex, allocatable, target :: carr(:) ! Test + + type cx + real :: re, im + end type cx + type(cx), parameter :: tvals(*) = [cx(1,-1),cx(2,-2),cx(3,-3)] + real, parameter :: expect(*) = tvals% re + type(cx) , target :: tref(size(cvals)) = tvals ! Reference + type(cx), allocatable, target :: tarr(:) + + real, pointer :: rr1(:), rr2(:), rr3(:), rr4(:) + class(*), pointer :: cp1(:), cp2(:), cp3(:), cp4(:) + + carr = cvals + tarr = tvals + + if (any (expect /= [1,2,3])) error stop 90 + + ! REAL pointer to non-contiguous effective target + rr1(1:3) => cref%re + rr2 => cref%re + rr3(1:3) => carr%re + rr4 => carr%re + + if (is_contiguous (rr1)) stop 1 + if (my_contiguous_real (rr1)) stop 2 + if (is_contiguous (cref(1:3)%re)) stop 3 +! if (my_contiguous_real (cref(1:3)%re)) stop 4 ! pr122397 + + if (is_contiguous (rr3)) stop 6 + if (my_contiguous_real (rr3)) stop 7 + if (is_contiguous (carr(1:3)%re)) stop 8 +! if (my_contiguous_real (carr(1:3)%re)) stop 9 + + if (is_contiguous (rr2)) stop 11 + if (my_contiguous_real (rr2)) stop 12 + if (is_contiguous (cref%re)) stop 13 +! if (my_contiguous_real (cref%re)) stop 14 + + if (is_contiguous (rr4)) stop 16 + if (my_contiguous_real (rr4)) stop 17 + if (is_contiguous (carr%re)) stop 18 +! if (my_contiguous_real (carr%re)) stop 19 + + rr1(1:3) => tref%re + rr2 => tref%re + rr3(1:3) => tarr%re + rr4 => tarr%re + + if (is_contiguous (rr1)) stop 21 + if (my_contiguous_real (rr1)) stop 22 + if (is_contiguous (tref(1:3)%re)) stop 23 +! if (my_contiguous_real (tref(1:3)%re)) stop 24 + + if (is_contiguous (rr3)) stop 26 + if (my_contiguous_real (rr3)) stop 27 + if (is_contiguous (tarr(1:3)%re)) stop 28 +! if (my_contiguous_real (tarr(1:3)%re)) stop 29 + + if (is_contiguous (rr2)) stop 31 + if (my_contiguous_real (rr2)) stop 32 + if (is_contiguous (tref%re)) stop 33 +! if (my_contiguous_real (tref%re)) stop 34 + + if (is_contiguous (rr4)) stop 36 + if (my_contiguous_real (rr4)) stop 37 + if (is_contiguous (tarr%re)) stop 38 +! if (my_contiguous_real (tarr%re)) stop 39 + + ! Unlimited polymorphic pointer to non-contiguous effective target + cp1(1:3) => cref%re + cp2 => cref%re + cp3(1:3) => carr%re + cp4 => carr%re + + if (is_contiguous (cp1)) stop 41 + if (my_contiguous_poly (cp1)) stop 42 + if (is_contiguous (cp2)) stop 43 + if (my_contiguous_poly (cp2)) stop 44 + if (is_contiguous (cp3)) stop 45 + if (my_contiguous_poly (cp3)) stop 46 + if (is_contiguous (cp4)) stop 47 + if (my_contiguous_poly (cp4)) stop 48 + + cp1(1:3) => tref%re + cp2 => tref%re + cp3(1:3) => tarr%re + cp4 => tarr%re + + if (is_contiguous (cp1)) stop 51 + if (my_contiguous_poly (cp1)) stop 52 + if (is_contiguous (cp2)) stop 53 + if (my_contiguous_poly (cp2)) stop 54 + if (is_contiguous (cp3)) stop 55 + if (my_contiguous_poly (cp3)) stop 56 + if (is_contiguous (cp4)) stop 57 + if (my_contiguous_poly (cp4)) stop 58 + + deallocate (carr, tarr) +contains + pure logical function my_contiguous_real (x) result (res) + real, pointer, intent(in) :: x(:) + res = is_contiguous (x) + if (any (x /= expect)) error stop 97 + end function my_contiguous_real + + pure logical function my_contiguous_poly (x) result (res) + class(*), pointer, intent(in) :: x(:) + res = is_contiguous (x) + select type (x) + type is (real) + if (any (x /= expect)) error stop 98 + class default + error stop 99 + end select + end function my_contiguous_poly +end diff --git a/gcc/testsuite/gfortran.dg/pdt_60.f03 b/gcc/testsuite/gfortran.dg/pdt_60.f03 new file mode 100644 index 0000000..dc9f7f2 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pdt_60.f03 @@ -0,0 +1,65 @@ +! { dg-do compile } +! { dg-options "-fdump-tree-original" } +! +! Test the fix for PR122290. +! +! Contributed by Damian Rouson <damian@archaeologic.codes> +! +module hyperparameters_m + implicit none + + type hyperparameters_t(k) + integer, kind :: k = kind(1.) + real(k) :: learning_rate_ = real(1.5,k) ! Gave "Invalid kind for REAL" + contains + generic :: operator(==) => default_real_equals, real8_equals ! Gave "Entity ‘default_real_equals’ at (1) + ! is already present in the interface" + generic :: g => default_real_equals, real8_equals ! Make sure that ordinary generic is OK + procedure default_real_equals + procedure real8_equals + end type + + interface + logical module function default_real_equals(lhs, rhs) + implicit none + class(hyperparameters_t), intent(in) :: lhs, rhs + end function + logical module function real8_equals(lhs, rhs) + implicit none + class(hyperparameters_t(kind(1d0))), intent(in) :: lhs, rhs + end function + end interface +end module + +! Added to test generic procedures are the correct ones. +submodule(hyperparameters_m) hyperparameters_s +contains + logical module function default_real_equals(lhs, rhs) + implicit none + class(hyperparameters_t), intent(in) :: lhs, rhs + default_real_equals = (lhs%learning_rate_ == rhs%learning_rate_) + end function + logical module function real8_equals(lhs, rhs) + implicit none + class(hyperparameters_t(kind(1d0))), intent(in) :: lhs, rhs + real8_equals = (lhs%learning_rate_ == rhs%learning_rate_) + end function +end submodule + + use hyperparameters_m + type (hyperparameters_t) :: a, b + type (hyperparameters_t(kind(1d0))) :: c, d + if (.not.(a == b)) stop 1 + if (.not.a%g(b)) stop 2 + a%learning_rate_ = real(2.5,a%k) + if (a == b) stop 3 + if (a%g(b)) stop 4 + + if (.not.(c == d)) stop 5 + if (.not.c%g(d)) stop 6 + c%learning_rate_ = real(2.5,c%k) + if (c == d) stop 7 + if (c%g(d)) stop 8 +end +! { dg-final { scan-tree-dump-times "default_real_equals" 8 "original" } } +! { dg-final { scan-tree-dump-times "real8_equals" 8 "original" } } diff --git a/gcc/testsuite/gfortran.dg/pdt_61.f03 b/gcc/testsuite/gfortran.dg/pdt_61.f03 new file mode 100644 index 0000000..20b97b0 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pdt_61.f03 @@ -0,0 +1,35 @@ +! { dg-do run } +! +! Test the fix for PR95541, in which parameterized array and string components +! of PDT arrays caused an ICE in the ASSOCIATE selector expressions below. +! +! Contributed by Gerhard Steinmetz <gscfq@t-online.de> +! +program p + type t(n) + integer, len :: n + integer :: a(n) + character(len = n) :: chr + end type + type(t(3)) :: x(2) + integer :: tgt(2) + x(1)%a = [1, 2, 3] + x(1)%chr = "abc" + x(2)%a = [4, 5, 6] + x(2)%chr = "def" + associate (y => x(:)%a(3)) + if (any (y /= [3,6])) stop 1 + y = -y + end associate + associate (y => x%a(3)) + if (any (y /= [-3,-6])) stop 2 + y = -y * 10 + end associate + if (any (x%a(3) /= [30,60])) stop 3 + if (any (x%a(2) /= [2,5])) stop 4 + associate (y => x%chr(2:2)) + if (any (y /= ["b","e"])) stop 5 + y = ["x", "y"] + end associate + if (any (x%chr /= ["axc","dyf"])) stop 6 +end diff --git a/gcc/testsuite/gfortran.target/aarch64/pr122408_1.f90 b/gcc/testsuite/gfortran.target/aarch64/pr122408_1.f90 new file mode 100644 index 0000000..8a34162 --- /dev/null +++ b/gcc/testsuite/gfortran.target/aarch64/pr122408_1.f90 @@ -0,0 +1,61 @@ +! { dg-do compile } +! { dg-additional-options "-O2 -march=armv8.3-a" } + +subroutine c_add_ab(n, a, c, b) ! C += A * B + use iso_fortran_env, only: real64 + implicit none + !GCC$ ATTRIBUTES noinline :: c_add_ab + integer, intent(in) :: n + complex(real64), intent(in) :: a + complex(real64), intent(inout) :: c(*) + complex(real64), intent(in) :: b(*) + integer :: k + do k = 1, n + c(k) = c(k) + a * b(k) + end do +end subroutine c_add_ab + +subroutine c_sub_ab(n, a, c, b) ! C -= A * B + use iso_fortran_env, only: real64 + implicit none + !GCC$ ATTRIBUTES noinline :: c_sub_ab + integer, intent(in) :: n + complex(real64), intent(in) :: a + complex(real64), intent(inout) :: c(*) + complex(real64), intent(in) :: b(*) + integer :: k + do k = 1, n + c(k) = c(k) - a * b(k) + end do +end subroutine c_sub_ab + +subroutine c_add_a_conjb(n, a, c, b) ! C += A * conj(B) + use iso_fortran_env, only: real64 + implicit none + !GCC$ ATTRIBUTES noinline :: c_add_a_conjb + integer, intent(in) :: n + complex(real64), intent(in) :: a + complex(real64), intent(inout) :: c(*) + complex(real64), intent(in) :: b(*) + integer :: k + do k = 1, n + c(k) = c(k) + a * conjg(b(k)) + end do +end subroutine c_add_a_conjb + +subroutine c_sub_a_conjb(n, a, c, b) ! C -= A * conj(B) + use iso_fortran_env, only: real64 + implicit none + !GCC$ ATTRIBUTES noinline :: c_sub_a_conjb + integer, intent(in) :: n + complex(real64), intent(in) :: a + complex(real64), intent(inout) :: c(*) + complex(real64), intent(in) :: b(*) + integer :: k + do k = 1, n + c(k) = c(k) - a * conjg(b(k)) + end do +end subroutine c_sub_a_conjb + +! { dg-final { scan-assembler-times {fcmla\s+v[0-9]+.2d, v[0-9]+.2d, v[0-9]+.2d, #0} 2 } } +! { dg-final { scan-assembler-times {fcmla\s+v[0-9]+.2d, v[0-9]+.2d, v[0-9]+.2d, #270} 2 } } diff --git a/gcc/testsuite/gfortran.target/aarch64/pr122408_2.f90 b/gcc/testsuite/gfortran.target/aarch64/pr122408_2.f90 new file mode 100644 index 0000000..feb6dc1 --- /dev/null +++ b/gcc/testsuite/gfortran.target/aarch64/pr122408_2.f90 @@ -0,0 +1,140 @@ +! { dg-do run } +! { dg-additional-options "-O2" } +! { dg-additional-options "-O2 -march=armv8.3-a" { target arm_v8_3a_complex_neon_hw } } + +module util + use iso_fortran_env, only: real64, int64 + implicit none +contains + pure logical function bitwise_eq(x, y) + complex(real64), intent(in) :: x, y + integer(int64) :: xr, xi, yr, yi + xr = transfer(real(x,kind=real64), 0_int64) + xi = transfer(aimag(x), 0_int64) + yr = transfer(real(y,kind=real64), 0_int64) + yi = transfer(aimag(y), 0_int64) + bitwise_eq = (xr == yr) .and. (xi == yi) + end function bitwise_eq + + subroutine check_equal(tag, got, ref, nfail) + character(*), intent(in) :: tag + complex(real64), intent(in) :: got(:), ref(:) + integer, intent(inout) :: nfail + integer :: i + do i = 1, size(got) + if (.not. bitwise_eq(got(i), ref(i))) then + nfail = nfail + 1 + write(*,'(A,": mismatch at i=",I0, " got=",2ES16.8," ref=",2ES16.8)') & + trim(tag), i, real(got(i)), aimag(got(i)), real(ref(i)), aimag(ref(i)) + end if + end do + end subroutine check_equal +end module util + +module fcmla_ops + use iso_fortran_env, only: real64 + implicit none +contains + subroutine c_add_ab(n, a, c, b) ! C += A * B + !GCC$ ATTRIBUTES noinline :: c_add_ab + integer, intent(in) :: n + complex(real64), intent(in) :: a + complex(real64), intent(inout) :: c(*) + complex(real64), intent(in) :: b(*) + integer :: k + do k = 1, n + c(k) = c(k) + a * b(k) + end do + end subroutine c_add_ab + + subroutine c_sub_ab(n, a, c, b) ! C -= A * B + !GCC$ ATTRIBUTES noinline :: c_sub_ab + integer, intent(in) :: n + complex(real64), intent(in) :: a + complex(real64), intent(inout) :: c(*) + complex(real64), intent(in) :: b(*) + integer :: k + do k = 1, n + c(k) = c(k) - a * b(k) + end do + end subroutine c_sub_ab + + subroutine c_add_a_conjb(n, a, c, b) ! C += A * conj(B) + !GCC$ ATTRIBUTES noinline :: c_add_a_conjb + integer, intent(in) :: n + complex(real64), intent(in) :: a + complex(real64), intent(inout) :: c(*) + complex(real64), intent(in) :: b(*) + integer :: k + do k = 1, n + c(k) = c(k) + a * conjg(b(k)) + end do + end subroutine c_add_a_conjb + + subroutine c_sub_a_conjb(n, a, c, b) ! C -= A * conj(B) + !GCC$ ATTRIBUTES noinline :: c_sub_a_conjb + integer, intent(in) :: n + complex(real64), intent(in) :: a + complex(real64), intent(inout) :: c(*) + complex(real64), intent(in) :: b(*) + integer :: k + do k = 1, n + c(k) = c(k) - a * conjg(b(k)) + end do + end subroutine c_sub_a_conjb +end module fcmla_ops + +program fcmla_accum_pairs + use iso_fortran_env, only: real64 + use util + use fcmla_ops + implicit none + + integer, parameter :: n = 4 + complex(real64) :: a, b(n), c0(n) + complex(real64) :: c_add_ab_got(n), c_add_ab_ref(n) + complex(real64) :: c_sub_ab_got(n), c_sub_ab_ref(n) + complex(real64) :: c_add_conjb_got(n), c_add_conjb_ref(n) + complex(real64) :: c_sub_conjb_got(n), c_sub_conjb_ref(n) + integer :: i, fails + + ! Constants (include a signed-zero lane) + a = cmplx( 2.0_real64, -3.0_real64, kind=real64) + b(1) = cmplx( 1.5_real64, -2.0_real64, kind=real64) + b(2) = cmplx(-4.0_real64, 5.0_real64, kind=real64) + b(3) = cmplx(-0.0_real64, 0.0_real64, kind=real64) + b(4) = cmplx( 0.25_real64, 3.0_real64, kind=real64) + + c0(1) = cmplx( 1.0_real64, -2.0_real64, kind=real64) + c0(2) = cmplx( 3.0_real64, -4.0_real64, kind=real64) + c0(3) = cmplx(-5.0_real64, 6.0_real64, kind=real64) + c0(4) = cmplx( 0.0_real64, 0.0_real64, kind=real64) + + ! Run each form + c_add_ab_got = c0; call c_add_ab (n, a, c_add_ab_got, b) + c_sub_ab_got = c0; call c_sub_ab (n, a, c_sub_ab_got, b) + c_add_conjb_got = c0; call c_add_a_conjb(n, a, c_add_conjb_got, b) + c_sub_conjb_got = c0; call c_sub_a_conjb(n, a, c_sub_conjb_got, b) + + ! Scalar references + do i = 1, n + c_add_ab_ref(i) = c0(i) + a * b(i) + c_sub_ab_ref(i) = c0(i) - a * b(i) + c_add_conjb_ref(i) = c0(i) + a * conjg(b(i)) + c_sub_conjb_ref(i) = c0(i) - a * conjg(b(i)) + end do + + ! Bitwise checks + fails = 0 + call check_equal("C += A*B ", c_add_ab_got, c_add_ab_ref, fails) + call check_equal("C -= A*B ", c_sub_ab_got, c_sub_ab_ref, fails) + call check_equal("C += A*conj(B) ", c_add_conjb_got, c_add_conjb_ref, fails) + call check_equal("C -= A*conj(B) ", c_sub_conjb_got, c_sub_conjb_ref, fails) + + if (fails == 0) then + stop 0 + else + stop 1 + end if +end program fcmla_accum_pairs + diff --git a/gcc/testsuite/gnat.dg/machine_attr3.adb b/gcc/testsuite/gnat.dg/machine_attr3.adb new file mode 100644 index 0000000..68a9c77 --- /dev/null +++ b/gcc/testsuite/gnat.dg/machine_attr3.adb @@ -0,0 +1,7 @@ +-- { dg-do compile } + +package body Machine_Attr3 is + + procedure Proc is null; + +end Machine_Attr3; diff --git a/gcc/testsuite/gnat.dg/machine_attr3.ads b/gcc/testsuite/gnat.dg/machine_attr3.ads new file mode 100644 index 0000000..edb7b7d --- /dev/null +++ b/gcc/testsuite/gnat.dg/machine_attr3.ads @@ -0,0 +1,10 @@ +package Machine_Attr3 is + + procedure Proc; + +private + + Attr : constant String := "nothrow"; + pragma Machine_Attribute (Proc, Attr); + +end Machine_Attr3; diff --git a/gcc/testsuite/gnat.dg/specs/generic_inst3.ads b/gcc/testsuite/gnat.dg/specs/generic_inst3.ads new file mode 100644 index 0000000..4f31d61 --- /dev/null +++ b/gcc/testsuite/gnat.dg/specs/generic_inst3.ads @@ -0,0 +1,3 @@ +with Generic_Inst3_Pkg1; + +package Generic_Inst3 is new Generic_Inst3_Pkg1; diff --git a/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg1.adb b/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg1.adb new file mode 100644 index 0000000..02294c2 --- /dev/null +++ b/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg1.adb @@ -0,0 +1,14 @@ +with Generic_Inst3_Pkg2; use Generic_Inst3_Pkg2; +with Generic_Inst3_Pkg3, Generic_Inst3_Pkg3.Child; + +package body Generic_Inst3_Pkg1 is + + package Pkg3 is new Generic_Inst3_Pkg3 (T); + + use Pkg3; + + package Child is new Pkg3.Child; + + procedure Proc is null; + +end Generic_Inst3_Pkg1; diff --git a/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg1.ads b/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg1.ads new file mode 100644 index 0000000..3fc9c76 --- /dev/null +++ b/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg1.ads @@ -0,0 +1,8 @@ +-- { dg-excess-errors "no code generated" } + +generic +package Generic_Inst3_Pkg1 is + + procedure Proc; + +end Generic_Inst3_Pkg1; diff --git a/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg2.ads b/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg2.ads new file mode 100644 index 0000000..9187adb --- /dev/null +++ b/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg2.ads @@ -0,0 +1,9 @@ +package Generic_Inst3_Pkg2 is + + type T is new Integer; + + procedure S_One (N: in out T) is null; + + procedure S_Two (N: in out T) is null; + +end Generic_Inst3_Pkg2; diff --git a/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg3-child.ads b/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg3-child.ads new file mode 100644 index 0000000..dd028431 --- /dev/null +++ b/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg3-child.ads @@ -0,0 +1,9 @@ +generic + + with procedure S_Two (N: in out Number) is <>; + +package Generic_Inst3_Pkg3.Child is + + procedure Two (N: in out Number) renames S_Two; + +end Generic_Inst3_Pkg3.Child; diff --git a/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg3.ads b/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg3.ads new file mode 100644 index 0000000..29cf00f --- /dev/null +++ b/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg3.ads @@ -0,0 +1,11 @@ +generic + + type Number is private; + + with procedure S_One (N: in out Number) is <>; + +package Generic_Inst3_Pkg3 is + + procedure One (N: in out Number) renames S_One; + +end Generic_Inst3_Pkg3; diff --git a/gcc/testsuite/gnat.dg/specs/private3-child.ads b/gcc/testsuite/gnat.dg/specs/private3-child.ads new file mode 100644 index 0000000..0367302 --- /dev/null +++ b/gcc/testsuite/gnat.dg/specs/private3-child.ads @@ -0,0 +1,11 @@ +-- { dg-do compile } + +generic + + type Ext is new T with private; + +package Private3.Child is + + procedure P_Private (X : in out Ext) is null; + +end Private3.Child; diff --git a/gcc/testsuite/gnat.dg/specs/private3.ads b/gcc/testsuite/gnat.dg/specs/private3.ads new file mode 100644 index 0000000..558246c --- /dev/null +++ b/gcc/testsuite/gnat.dg/specs/private3.ads @@ -0,0 +1,9 @@ +package Private3 is + + type T is tagged null record; + +private + + procedure P_Private (X : in out T) is null; + +end Private3; diff --git a/gcc/tree-ssa-forwprop.cc b/gcc/tree-ssa-forwprop.cc index 68e80ba..79ac25f 100644 --- a/gcc/tree-ssa-forwprop.cc +++ b/gcc/tree-ssa-forwprop.cc @@ -216,6 +216,31 @@ static bitmap to_purge; /* Const-and-copy lattice. */ static vec<tree> lattice; +/* forwprop_may_propagate_copy is like may_propagate_copy except + after the final folding, don't allow propagating of pointer ORIG + that have a lower alignment than the DEST name. + This is to prevent losing alignment information from + __builtin_assume_aligned for expand (See also PR 122086). */ +static bool +forwprop_may_propagate_copy (tree dest, tree orig, + bool dest_not_abnormal_phi_edge_p = false) +{ + if (!may_propagate_copy (dest, orig, dest_not_abnormal_phi_edge_p)) + return false; + + /* Only check alignment for the final folding. */ + if (!(cfun->curr_properties & PROP_last_full_fold)) + return true; + + /* Alignment only matters for pointer types. */ + if (!POINTER_TYPE_P (TREE_TYPE (dest)) || !POINTER_TYPE_P (TREE_TYPE (orig))) + return true; + + unsigned aligndest = get_pointer_alignment (dest); + unsigned alignorig = get_pointer_alignment (orig); + return aligndest <= alignorig; +} + /* Set the lattice entry for NAME to VAL. */ static void fwprop_set_lattice_val (tree name, tree val) @@ -5177,7 +5202,7 @@ pass_forwprop::execute (function *fun) } if (all_same) { - if (may_propagate_copy (res, first)) + if (forwprop_may_propagate_copy (res, first)) to_remove_defs.safe_push (SSA_NAME_VERSION (res)); fwprop_set_lattice_val (res, first); } @@ -5532,7 +5557,7 @@ pass_forwprop::execute (function *fun) { if (!is_gimple_debug (stmt)) bitmap_set_bit (simple_dce_worklist, SSA_NAME_VERSION (use)); - if (may_propagate_copy (use, val)) + if (forwprop_may_propagate_copy (use, val)) { propagate_value (usep, val); substituted_p = true; @@ -5695,7 +5720,7 @@ pass_forwprop::execute (function *fun) /* If we can propagate the lattice-value mark the stmt for removal. */ if (val != lhs - && may_propagate_copy (lhs, val)) + && forwprop_may_propagate_copy (lhs, val)) to_remove_defs.safe_push (SSA_NAME_VERSION (lhs)); fwprop_set_lattice_val (lhs, val); } @@ -5717,7 +5742,7 @@ pass_forwprop::execute (function *fun) continue; tree val = fwprop_ssa_val (arg); if (val != arg - && may_propagate_copy (arg, val, !(e->flags & EDGE_ABNORMAL))) + && forwprop_may_propagate_copy (arg, val, !(e->flags & EDGE_ABNORMAL))) propagate_value (use_p, val); } diff --git a/gcc/tree-ssa-sccvn.cc b/gcc/tree-ssa-sccvn.cc index 246fa08..09f92b2 100644 --- a/gcc/tree-ssa-sccvn.cc +++ b/gcc/tree-ssa-sccvn.cc @@ -7356,13 +7356,14 @@ eliminate_dom_walker::eliminate_stmt (basic_block b, gimple_stmt_iterator *gsi) else lookup_lhs = NULL_TREE; } - tree val = NULL_TREE; + tree val = NULL_TREE, tem; if (lookup_lhs) val = vn_reference_lookup (lookup_lhs, gimple_vuse (stmt), VN_WALKREWRITE, &vnresult, false, NULL, NULL_TREE, true); if (TREE_CODE (rhs) == SSA_NAME) rhs = VN_INFO (rhs)->valnum; + gassign *ass; if (val && (operand_equal_p (val, rhs, 0) /* Due to the bitfield lookups above we can get bit @@ -7370,9 +7371,14 @@ eliminate_dom_walker::eliminate_stmt (basic_block b, gimple_stmt_iterator *gsi) are redundant as well. */ || (TREE_CODE (val) == SSA_NAME && gimple_assign_single_p (SSA_NAME_DEF_STMT (val)) - && (val = gimple_assign_rhs1 (SSA_NAME_DEF_STMT (val))) - && TREE_CODE (val) == VIEW_CONVERT_EXPR - && TREE_OPERAND (val, 0) == rhs))) + && (tem = gimple_assign_rhs1 (SSA_NAME_DEF_STMT (val))) + && TREE_CODE (tem) == VIEW_CONVERT_EXPR + && TREE_OPERAND (tem, 0) == rhs) + || (TREE_CODE (rhs) == SSA_NAME + && (ass = dyn_cast <gassign *> (SSA_NAME_DEF_STMT (rhs))) + && gimple_assign_rhs1 (ass) == val + && CONVERT_EXPR_CODE_P (gimple_assign_rhs_code (ass)) + && tree_nop_conversion_p (TREE_TYPE (rhs), TREE_TYPE (val))))) { /* We can only remove the later store if the former aliases at least all accesses the later one does or if the store diff --git a/gcc/tree-vect-slp-patterns.cc b/gcc/tree-vect-slp-patterns.cc index 46d8b94..23b8afd 100644 --- a/gcc/tree-vect-slp-patterns.cc +++ b/gcc/tree-vect-slp-patterns.cc @@ -852,15 +852,23 @@ compatible_complex_nodes_p (slp_compat_nodes_map_t *compat_cache, return true; } + +/* Check to see if the oprands to two multiplies, 2 each in LEFT_OP and + RIGHT_OP match a complex multiplication or complex multiply-and-accumulate + or complex multiply-and-subtract pattern. Do this using the permute cache + PERM_CACHE and the combination compatibility list COMPAT_CACHE. If + the operation is successful the macthing operands are returned in OPS and + _STATUS indicates if the operation matched includes a conjugate of one of the + operands. If the operation succeeds True is returned, otherwise False and + the values in ops are meaningless. */ static inline bool vect_validate_multiplication (slp_tree_to_load_perm_map_t *perm_cache, slp_compat_nodes_map_t *compat_cache, - vec<slp_tree> &left_op, - vec<slp_tree> &right_op, - bool subtract, + const vec<slp_tree> &left_op, + const vec<slp_tree> &right_op, + bool subtract, vec<slp_tree> &ops, enum _conj_status *_status) { - auto_vec<slp_tree> ops; enum _conj_status stats = CONJ_NONE; /* The complex operations can occur in two layouts and two permute sequences @@ -891,31 +899,31 @@ vect_validate_multiplication (slp_tree_to_load_perm_map_t *perm_cache, bool neg0 = vect_match_expression_p (right_op[0], NEGATE_EXPR); bool neg1 = vect_match_expression_p (right_op[1], NEGATE_EXPR); + /* Create the combined inputs after remapping and flattening. */ + ops.create (4); + ops.safe_splice (left_op); + ops.safe_splice (right_op); + /* Determine which style we're looking at. We only have different ones whenever a conjugate is involved. */ if (neg0 && neg1) ; else if (neg0) { - right_op[0] = SLP_TREE_CHILDREN (right_op[0])[0]; + ops[2] = SLP_TREE_CHILDREN (right_op[0])[0]; stats = CONJ_FST; if (subtract) perm = 0; } else if (neg1) { - right_op[1] = SLP_TREE_CHILDREN (right_op[1])[0]; + ops[3] = SLP_TREE_CHILDREN (right_op[1])[0]; stats = CONJ_SND; perm = 1; } *_status = stats; - /* Flatten the inputs after we've remapped them. */ - ops.create (4); - ops.safe_splice (left_op); - ops.safe_splice (right_op); - /* Extract out the elements to check. */ slp_tree op0 = ops[styles[style][0]]; slp_tree op1 = ops[styles[style][1]]; @@ -1078,15 +1086,16 @@ complex_mul_pattern::matches (complex_operation_t op, return IFN_LAST; enum _conj_status status; + auto_vec<slp_tree> res_ops; if (!vect_validate_multiplication (perm_cache, compat_cache, left_op, - right_op, false, &status)) + right_op, false, res_ops, &status)) { /* Try swapping the order and re-trying since multiplication is commutative. */ std::swap (left_op[0], left_op[1]); std::swap (right_op[0], right_op[1]); if (!vect_validate_multiplication (perm_cache, compat_cache, left_op, - right_op, false, &status)) + right_op, false, res_ops, &status)) return IFN_LAST; } @@ -1114,24 +1123,24 @@ complex_mul_pattern::matches (complex_operation_t op, if (add0) ops->quick_push (add0); - complex_perm_kinds_t kind = linear_loads_p (perm_cache, left_op[0]); + complex_perm_kinds_t kind = linear_loads_p (perm_cache, res_ops[0]); if (kind == PERM_EVENODD || kind == PERM_TOP) { - ops->quick_push (left_op[1]); - ops->quick_push (right_op[1]); - ops->quick_push (left_op[0]); + ops->quick_push (res_ops[1]); + ops->quick_push (res_ops[3]); + ops->quick_push (res_ops[0]); } else if (kind == PERM_EVENEVEN && status != CONJ_SND) { - ops->quick_push (left_op[0]); - ops->quick_push (right_op[0]); - ops->quick_push (left_op[1]); + ops->quick_push (res_ops[0]); + ops->quick_push (res_ops[2]); + ops->quick_push (res_ops[1]); } else { - ops->quick_push (left_op[0]); - ops->quick_push (right_op[1]); - ops->quick_push (left_op[1]); + ops->quick_push (res_ops[0]); + ops->quick_push (res_ops[3]); + ops->quick_push (res_ops[1]); } return ifn; @@ -1303,15 +1312,17 @@ complex_fms_pattern::matches (complex_operation_t op, return IFN_LAST; enum _conj_status status; + auto_vec<slp_tree> res_ops; if (!vect_validate_multiplication (perm_cache, compat_cache, right_op, - left_op, true, &status)) + left_op, true, res_ops, &status)) { /* Try swapping the order and re-trying since multiplication is commutative. */ std::swap (left_op[0], left_op[1]); std::swap (right_op[0], right_op[1]); + auto_vec<slp_tree> res_ops; if (!vect_validate_multiplication (perm_cache, compat_cache, right_op, - left_op, true, &status)) + left_op, true, res_ops, &status)) return IFN_LAST; } @@ -1326,20 +1337,20 @@ complex_fms_pattern::matches (complex_operation_t op, ops->truncate (0); ops->create (4); - complex_perm_kinds_t kind = linear_loads_p (perm_cache, right_op[0]); + complex_perm_kinds_t kind = linear_loads_p (perm_cache, res_ops[2]); if (kind == PERM_EVENODD) { ops->quick_push (l0node[0]); - ops->quick_push (right_op[0]); - ops->quick_push (right_op[1]); - ops->quick_push (left_op[1]); + ops->quick_push (res_ops[2]); + ops->quick_push (res_ops[3]); + ops->quick_push (res_ops[1]); } else { ops->quick_push (l0node[0]); - ops->quick_push (right_op[1]); - ops->quick_push (right_op[0]); - ops->quick_push (left_op[0]); + ops->quick_push (res_ops[3]); + ops->quick_push (res_ops[2]); + ops->quick_push (res_ops[0]); } return ifn; diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect-slp.cc index 31d8485..e02b337 100644 --- a/gcc/tree-vect-slp.cc +++ b/gcc/tree-vect-slp.cc @@ -4217,6 +4217,7 @@ vect_analyze_slp_reduc_chain (loop_vec_info vinfo, if (!gimple_extract_op (STMT_VINFO_STMT (vect_orig_stmt (stmt)), &op)) gcc_unreachable (); if (CONVERT_EXPR_CODE_P (op.code) + && tree_nop_conversion_p (op.type, TREE_TYPE (op.ops[0])) && (first || is_a <gphi *> (STMT_VINFO_STMT (next_stmt)))) ; diff --git a/gcc/tree-vectorizer.h b/gcc/tree-vectorizer.h index 56b3a5a..359c994 100644 --- a/gcc/tree-vectorizer.h +++ b/gcc/tree-vectorizer.h @@ -2143,7 +2143,7 @@ dr_safe_speculative_read_required (stmt_vec_info stmt_info) return dr_info->safe_speculative_read_required; } -/* Set the safe_speculative_read_required for the the stmt_vec_info, if group +/* Set the safe_speculative_read_required for the stmt_vec_info, if group access then set on the fist element otherwise set on DR directly. */ inline void dr_set_safe_speculative_read_required (stmt_vec_info stmt_info, diff --git a/gcc/value-range-storage.h b/gcc/value-range-storage.h index 191e00f..60da730 100644 --- a/gcc/value-range-storage.h +++ b/gcc/value-range-storage.h @@ -87,7 +87,7 @@ private: enum value_range_kind m_kind : 3; - // The length of this is m_num_ranges * 2 + 2 to accomodate the bitmask. + // The length of this is m_num_ranges * 2 + 2 to accommodate the bitmask. HOST_WIDE_INT m_val[1]; // Another variable-length part of the structure following the HWIs. diff --git a/gcc/wide-int.h b/gcc/wide-int.h index 1814818..37b575c 100644 --- a/gcc/wide-int.h +++ b/gcc/wide-int.h @@ -235,7 +235,7 @@ along with GCC; see the file COPYING3. If not see /* The MAX_BITSIZE_MODE_ANY_INT is automatically generated by a very early examination of the target's mode file. The WIDE_INT_MAX_INL_ELTS - can accomodate at least 1 more bit so that unsigned numbers of that + can accommodate at least 1 more bit so that unsigned numbers of that mode can be represented as a signed value. Note that it is still possible to create fixed_wide_ints that have precisions greater than MAX_BITSIZE_MODE_ANY_INT. This can be useful when representing a diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog index 4c4e14b..3973653 100644 --- a/libgcc/ChangeLog +++ b/libgcc/ChangeLog @@ -1,3 +1,8 @@ +2025-10-25 Olivier Hainque <hainque@adacore.com> + + * config/t-vxworks (LIBGCC2_INCLUDES): Replace $(VSB_DIR) + by sysroot references. + 2025-10-20 Olivier Hainque <hainque@adacore.com> Ashley Gay <gay@adacore.com> diff --git a/libgcobol/ChangeLog b/libgcobol/ChangeLog index 1858e80..67b25fe 100644 --- a/libgcobol/ChangeLog +++ b/libgcobol/ChangeLog @@ -1,3 +1,8 @@ +2025-10-25 Sam James <sam@gentoo.org> + + PR cobol/122398 + * xmlparse.cc (__gg__xml_parse): Make 'msg' const. + 2025-10-23 Robert Dubner <rdubner@symas.com> * charmaps.cc: Encoding. diff --git a/libgcobol/xmlparse.cc b/libgcobol/xmlparse.cc index 69849e3..edaf124 100644 --- a/libgcobol/xmlparse.cc +++ b/libgcobol/xmlparse.cc @@ -46,6 +46,8 @@ #include <libxml/SAX2.h> #include <libxml/parser.h> +#include <syslog.h> + #include "config.h" #include "libgcobol-fp.h" #include "ec.h" @@ -76,118 +78,120 @@ void sayso( const char func[], int line, #define SAYSO_DATAZ(S) sayso(__func__, __LINE__, -1, S) #define SAYSO_DATA(N, S) sayso(__func__, __LINE__, N, S) +#define CTX ctx __attribute__ ((unused)) + struct xml_ec_value_t { int ibm_code; const char msg[80]; -} xml_ec_values[] = { +} xml_ec_values[] = { // Table 73. XML PARSE exceptions that allow continuation - { 1, "invalid character between elements" }, - { 2, "invalid start before element content" }, - { 3, "duplicate attribute" }, - { 4, "markup character '<' in an attribute value" }, - { 5, "start/end tag mismatch" }, - { 6, "invalid character in element" }, - { 7, "invalid start in element content. " }, - { 8, "CDATA closing character sequence ']]>' not opened" }, - { 10, "comment the character sequence '--' without '>'" }, - { 11, "invalid character in a processing instruction" }, - { 12, "XML declaration was not start of document" }, - { 13, "invalid digit in a hexadecimal character reference" }, - { 14, "invalid digit in a decimal character reference" }, - { 15, "encoding declaration value name must start with [a-zA-Z] character" }, - { 16, "character reference did not refer to a legal XML character" }, - { 17, "invalid character in an entity reference name" }, - { 70, "EBCDIC document, supported EBCDIC page, unsupported declaration" }, - { 71, "EBCDIC document, unsupported EBCDIC page " }, - { 72, "EBCDIC document, unsupported EBCDIC page, unsupported declaration" }, - { 73, "EBCDIC document, unsupported EBCDIC page and declaration " }, - { 80, "ASCII document, supported ASCII page, unsupported declaration" }, - { 81, "ASCII document, unsupported ASCII page " }, - { 82, "ASCII document, unsupported ASCII page, unsupported declaration" }, - { 83, "ASCII document, unsupported ASCII page and declaration " }, - { 84, "ASCII document, invalid UTF-8, external UTF-8, no declaration. " }, - { 85, "ASCII document, invalid UTF-8, external UTF-8, invalid declaration" }, - { 86, "ASCII document, invalid UTF-8, external ASCII" }, - { 87, "ASCII document, invalid UTF-8, external and document UTF-8" }, - { 88, "ASCII document, invalid UTF-8, unsupported ASCII/UTF-8, UTF-8 declaration" }, - { 89, "ASCII document, invalid UTF-8, external UTF-8, ASCII declaration" }, - { 92, "alphanumeric document expected, document is UTF-16. " }, - - // XML PARSE exceptions that allow continuation (continued) + { 1, "invalid character between elements" }, + { 2, "invalid start before element content" }, + { 3, "duplicate attribute" }, + { 4, "markup character '<' in an attribute value" }, + { 5, "start/end tag mismatch" }, + { 6, "invalid character in element" }, + { 7, "invalid start in element content. " }, + { 8, "CDATA closing character sequence ']]>' not opened" }, + { 10, "comment the character sequence '--' without '>'" }, + { 11, "invalid character in a processing instruction" }, + { 12, "XML declaration was not start of document" }, + { 13, "invalid digit in a hexadecimal character reference" }, + { 14, "invalid digit in a decimal character reference" }, + { 15, "encoding declaration value name must start with [a-zA-Z] character" }, + { 16, "character reference did not refer to a legal XML character" }, + { 17, "invalid character in an entity reference name" }, + { 70, "EBCDIC document, supported EBCDIC page, unsupported declaration" }, + { 71, "EBCDIC document, unsupported EBCDIC page " }, + { 72, "EBCDIC document, unsupported EBCDIC page, unsupported declaration" }, + { 73, "EBCDIC document, unsupported EBCDIC page and declaration " }, + { 80, "ASCII document, supported ASCII page, unsupported declaration" }, + { 81, "ASCII document, unsupported ASCII page " }, + { 82, "ASCII document, unsupported ASCII page, unsupported declaration" }, + { 83, "ASCII document, unsupported ASCII page and declaration " }, + { 84, "ASCII document, invalid UTF-8, external UTF-8, no declaration. " }, + { 85, "ASCII document, invalid UTF-8, external UTF-8, invalid declaration" }, + { 86, "ASCII document, invalid UTF-8, external ASCII" }, + { 87, "ASCII document, invalid UTF-8, external and document UTF-8" }, + { 88, "ASCII document, invalid UTF-8, unsupported ASCII/UTF-8, UTF-8 declaration" }, + { 89, "ASCII document, invalid UTF-8, external UTF-8, ASCII declaration" }, + { 92, "alphanumeric document expected, document is UTF-16. " }, + + // XML PARSE exceptions that allow continuation (continued) //// 100,001 - 165,535 EBCDIC document encoding does not match code page //// 200,001 - 265,535 ASCII document encoding does not match code page - // XML PARSE exceptions that do not allow continuation - { 100, "end of document before start of XML declaration" }, - { 101, "end of document before end of XML declaration" }, - { 102, "end of document before root element" }, - { 103, "end of document before version information in XML declaration" }, - { 104, "end of document before version information value in XML declaration" }, - { 106, "end of document before encoding declaration value in XML declaration" }, - { 108, "end of document before standalone declaration value in XML declaration" }, - { 109, "end of document before attribute name" }, - { 110, "end of document before attribute value" }, - { 111, "end of document before character/entity reference in attribute value" }, - { 112, "end of document before empty element tag" }, - { 113, "end of document before root element name" }, - { 114, "end of document before element name" }, - { 115, "end of document before character data in element content" }, - { 116, "end of document before processing instruction in element content" }, - { 117, "end of document before comment or CDATA section in element content" }, - { 118, "end of document before comment in element content" }, - { 119, "end of document before CDATA section in element content" }, - { 120, "end of document before character/entity reference in element content" }, - { 121, "end of document before after close of root element" }, - { 122, "possible invalid start of a document type" }, - { 123, "duplicate document type" }, - { 124, "root element name must start with [A-Za-z_:]" }, - { 125, "first attribute name must start with [A-Za-z_:]" }, - { 126, "invalid character in or after element name" }, - { 127, "attribute name not followed by '=' " }, - { 128, "invalid attribute value delimiter" }, - { 130, "attribute name must start with [A-Za-z_:]" }, - { 131, "invalid character in or after attribute name" }, - { 132, "empty element tag not terminated with '/>'" }, - { 133, "element end tag name name must start with [A-Za-z_:]" }, - { 134, "element end tag not terminated with '>'" }, - { 135, "element name must start with [A-Za-z_:]" }, - { 136, "invalid start of comment/CDATA in element" }, - { 137, "invalid start of comment" }, - { 138, "processing instruction target name must start with [A-Za-z_:]" }, - { 139, "invalid character in/afterprocessing instruction target name" }, - { 140, "processing instruction not terminated with '?>'" }, - { 141, "invalid character following '&' in a character/entity reference" }, - { 142, "missing version information in XML declaration" }, - { 143, "missing '=' after 'version' in XML declaration " }, - { 144, "missing XML version declaration " }, - { 145, "invalid character in XML version information" }, - { 146, "invalid character following XML version information value " }, - { 147, "invalid attribute in XML declaration" }, - { 148, "missing '=' after 'encoding' in XML declaration" }, - { 149, "missing XML encoding declaration value" }, - { 150, "invalid XML encoding declaration value" }, - { 151, "invalid character afer XML declaration" }, - { 152, "invalid attribute XML declaration" }, - { 153, "missing '=' after standalone XML declaration" }, - { 154, "missing standalone XML declaration value" }, - { 155, "standalone declaration must be 'yes' or 'no'" }, - { 156, "invalid standalone XML declaration value" }, - { 157, "invalid character following XML standalone declaration value" }, - { 158, "unterminated XML declaration " }, - { 159, "start of document type declaration after end of root element" }, - { 160, "start of element after end of root element" }, - { 161, "invalid UTF-8 byte sequence" }, - { 162, "UTF-8 character that has a Unicode code point above x'FFFF'" }, - { 315, "UTF-16 document little-endian unsupported" }, - { 316, "UCS4 document unsupported" }, - { 317, "unrecognized document encoding" }, - { 318, "UTF-8 document unsupported " }, - { 320, "mismatched national document data item to document encoding EBCDIC" }, - { 321, "mismatched national document data item to document encoding ASCII" }, - { 322, "mismatched native alphanumeric document data item to document encoding EBCDIC" }, - { 323, "mismatched host alphanumeric document data item to document encoding ASCII" }, - { 324, "mismatched national document data item to document encoding UTF-8" }, - { 325, "mismatched host alphanumeric document datat to document encoding UTF-8" }, + // XML PARSE exceptions that do not allow continuation + { 100, "end of document before start of XML declaration" }, + { 101, "end of document before end of XML declaration" }, + { 102, "end of document before root element" }, + { 103, "end of document before version information in XML declaration" }, + { 104, "end of document before version information value in XML declaration" }, + { 106, "end of document before encoding declaration value in XML declaration" }, + { 108, "end of document before standalone declaration value in XML declaration" }, + { 109, "end of document before attribute name" }, + { 110, "end of document before attribute value" }, + { 111, "end of document before character/entity reference in attribute value" }, + { 112, "end of document before empty element tag" }, + { 113, "end of document before root element name" }, + { 114, "end of document before element name" }, + { 115, "end of document before character data in element content" }, + { 116, "end of document before processing instruction in element content" }, + { 117, "end of document before comment or CDATA section in element content" }, + { 118, "end of document before comment in element content" }, + { 119, "end of document before CDATA section in element content" }, + { 120, "end of document before character/entity reference in element content" }, + { 121, "end of document before after close of root element" }, + { 122, "possible invalid start of a document type" }, + { 123, "duplicate document type" }, + { 124, "root element name must start with [A-Za-z_:]" }, + { 125, "first attribute name must start with [A-Za-z_:]" }, + { 126, "invalid character in or after element name" }, + { 127, "attribute name not followed by '=' " }, + { 128, "invalid attribute value delimiter" }, + { 130, "attribute name must start with [A-Za-z_:]" }, + { 131, "invalid character in or after attribute name" }, + { 132, "empty element tag not terminated with '/>'" }, + { 133, "element end tag name name must start with [A-Za-z_:]" }, + { 134, "element end tag not terminated with '>'" }, + { 135, "element name must start with [A-Za-z_:]" }, + { 136, "invalid start of comment/CDATA in element" }, + { 137, "invalid start of comment" }, + { 138, "processing instruction target name must start with [A-Za-z_:]" }, + { 139, "invalid character in/afterprocessing instruction target name" }, + { 140, "processing instruction not terminated with '?>'" }, + { 141, "invalid character following '&' in a character/entity reference" }, + { 142, "missing version information in XML declaration" }, + { 143, "missing '=' after 'version' in XML declaration " }, + { 144, "missing XML version declaration " }, + { 145, "invalid character in XML version information" }, + { 146, "invalid character following XML version information value " }, + { 147, "invalid attribute in XML declaration" }, + { 148, "missing '=' after 'encoding' in XML declaration" }, + { 149, "missing XML encoding declaration value" }, + { 150, "invalid XML encoding declaration value" }, + { 151, "invalid character afer XML declaration" }, + { 152, "invalid attribute XML declaration" }, + { 153, "missing '=' after standalone XML declaration" }, + { 154, "missing standalone XML declaration value" }, + { 155, "standalone declaration must be 'yes' or 'no'" }, + { 156, "invalid standalone XML declaration value" }, + { 157, "invalid character following XML standalone declaration value" }, + { 158, "unterminated XML declaration " }, + { 159, "start of document type declaration after end of root element" }, + { 160, "start of element after end of root element" }, + { 161, "invalid UTF-8 byte sequence" }, + { 162, "UTF-8 character that has a Unicode code point above x'FFFF'" }, + { 315, "UTF-16 document little-endian unsupported" }, + { 316, "UCS4 document unsupported" }, + { 317, "unrecognized document encoding" }, + { 318, "UTF-8 document unsupported " }, + { 320, "mismatched national document data item to document encoding EBCDIC" }, + { 321, "mismatched national document data item to document encoding ASCII" }, + { 322, "mismatched native alphanumeric document data item to document encoding EBCDIC" }, + { 323, "mismatched host alphanumeric document data item to document encoding ASCII" }, + { 324, "mismatched national document data item to document encoding UTF-8" }, + { 325, "mismatched host alphanumeric document datat to document encoding UTF-8" }, { 500, "internal error" }, }, *eoxml_ec_values = xml_ec_values + COUNT_OF(xml_ec_values); @@ -240,17 +244,17 @@ ATTRIBUTE-CHARACTER The single character that corresponds with the predefined en ATTRIBUTE-CHARACTERS The value within quotation marks or apostrophes. This can be a substring of the attribute value if the value includes an entity reference. ATTRIBUTE-NAME The attribute name; the string to the left of the equal sign ATTRIBUTE-NATIONAL-CHARACTER Regardless of the type of the XML document specified by identifier-1 in the XML PARSE statement, XML-TEXT is empty with length zero and XML-NTEXT contains the single national character that corresponds with the numeric character reference. - + CONTENT-CHARACTER The single character that corresponds with the predefined entity reference in the element content - + CONTENT-NATIONAL-CHARACTER Regardless of the type of the XML document specified by identifier-1 in the XML PARSE statement, XML-TEXT is empty with length zero and XML-NTEXT contains the single national character that corresponds with the numeric character reference.1 DOCUMENT-TYPE-DECLARATION The entire document type declaration, including the opening and closing character sequences "<!DOCTYPE" and ">" ENCODING-DECLARATION The value, between quotes or apostrophes, of the encoding declaration in the XML declaration END-OF-CDATA-SECTION The string "]]>" END-OF-DOCUMENT Empty with length zero - + EXCEPTION The part of the document that was successfully scanned, up to and including the point at which the exception was detected.2 Special register XML-CODE contains the unique error code that identifies the exception. - + PROCESSING-INSTRUCTION-TARGET The processing instruction target name, which occurs immediately after the processing instruction opening sequence, "<?" STANDALONE-DECLARATION The value, between quotation marks or apostrophes ("yes" or "no"), of the stand-alone declaration in the XML declaration START-OF-CDATA-SECTION The string "<![CDATA[" @@ -276,7 +280,7 @@ xml_event( const char event_name[], size_t len, char text[] ) { auto p = std::copy( event_name, event_name + strlen(event_name), PTRCAST(char, __ggsr__xml_event.data) ); std::fill(PTRCAST(unsigned char, p), pend, 0x20); - + __ggsr__xml_text.data = reinterpret_cast<unsigned char*>(text); __ggsr__xml_text.capacity = __ggsr__xml_text.allocated = len; __ggsr__xml_code.data = 0; @@ -300,70 +304,80 @@ xml_event( const char event_name[], const xmlChar * value ) { xml_event(event_name, strlen(text), text); } -static void attributeDecl(void * ctx, - const xmlChar * elem, - const xmlChar * fullname, - int type, - int def, - const xmlChar * defaultValue, - xmlEnumerationPtr tree) +/* + * Many static handler functions are defined but not used while we learn what + * is needed. + */ +#pragma GCC diagnostic ignored "-Wunused-function" + +static void attributeDecl(void * CTX, + const xmlChar * elem, + const xmlChar * fullname, + int type __attribute__ ((unused)), + int def __attribute__ ((unused)), + const xmlChar * defaultValue, + xmlEnumerationPtr tree __attribute__ ((unused)) ) { fprintf(stderr, "%s:%d: elem=%s, name=%s, default=%s\n", __func__, __LINE__, elem, fullname, defaultValue); } -static void cdataBlock(void * ctx, - const xmlChar * data, +static void cdataBlock(void * CTX, + const xmlChar * data, int len) -{ +{ SAYSO_DATA(len, data); xml_event("CONTENT-CHARACTERS", len, data); } -static void characters(void * ctx, - const xmlChar * data, +static void characters(void * CTX, + const xmlChar * data, int len) { SAYSO_DATA(len, data); xml_event("CONTENT-CHARACTERS", len, data); } -static void comment(void * ctx, const xmlChar * value) { +static void comment(void * CTX, const xmlChar * value) { SAYSO_DATAZ(value); xml_event("COMMENT", value); } -static void elementDecl(void * ctx, - const xmlChar * name, - int type, - xmlElementContentPtr content) +static void elementDecl(void * CTX, + const xmlChar * name, + int type __attribute__ ((unused)), + xmlElementContentPtr content __attribute__ ((unused)) ) { SAYSO_DATAZ(name); } -static void endDocument(void * ctx) +static void endDocument(void * CTX) { SAYSO(); } -static void endElementNs(void * ctx, - const xmlChar * localname, - const xmlChar * prefix, - const xmlChar * URI) +static void endElementNs(void * CTX, + const xmlChar * localname, + const xmlChar * prefix, + const xmlChar * URI __attribute__ ((unused)) ) { + SAYSO_DATAZ(prefix); SAYSO_DATAZ(localname); xml_event("END-OF-ELEMENT", localname); } -static void endElement(void * ctx, +static void endElement(void * CTX, const xmlChar * name) { SAYSO_DATAZ(name); } -static void entityDecl(void * ctx, - const xmlChar * name, - int type, - const xmlChar * publicId, - const xmlChar * systemId, - xmlChar * content) -{ SAYSO_DATAZ(name); } +static void entityDecl(void * CTX, + const xmlChar * name, + int type __attribute__ ((unused)), + const xmlChar * publicId __attribute__ ((unused)), + const xmlChar * systemId __attribute__ ((unused)), + xmlChar * content ) +{ + SAYSO_DATAZ(name); + SAYSO_DATAZ(content); +} -static void error(void * ctx, const char * msg, ...) +static void error(void * CTX, const char * msg, ...) { va_list ap; va_start (ap, msg); @@ -373,13 +387,17 @@ static void error(void * ctx, const char * msg, ...) va_end (ap); } -static void externalSubset(void * ctx, - const xmlChar * name, - const xmlChar * ExternalID, +static void externalSubset(void * CTX, + const xmlChar * name, + const xmlChar * ExternalID, const xmlChar * SystemID) -{ SAYSO_DATAZ(name); } +{ + SAYSO_DATAZ(name); + SAYSO_DATAZ(ExternalID); + SAYSO_DATAZ(SystemID); +} -static void fatalError(void * ctx, const char * msg, ...) +static void fatalError(void * CTX, const char * msg, ...) { va_list ap; va_start (ap, msg); @@ -389,43 +407,54 @@ static void fatalError(void * ctx, const char * msg, ...) va_end (ap); } -static xmlEntityPtr getEntity(void * ctx, +#if 0 +static xmlEntityPtr getEntity(void * CTX, const xmlChar * name) { SAYSO_DATAZ(name); } -static xmlEntityPtr getParameterEntity(void * ctx, +static xmlEntityPtr getParameterEntity(void * CTX, const xmlChar * name) { SAYSO_DATAZ(name); } +#endif -static int hasExternalSubset(void * ctx) -{ SAYSO(); } +static int hasExternalSubset(void * CTX) +{ SAYSO(); return 0; } -static int hasInternalSubset(void * ctx) -{ SAYSO(); } +static int hasInternalSubset(void * CTX) +{ SAYSO(); return 0; } -static void ignorableWhitespace(void * ctx, - const xmlChar * ch, +static void ignorableWhitespace(void * CTX, + const xmlChar * ch, int len) { SAYSO_DATA(len, ch); } -static void internalSubset(void * ctx, - const xmlChar * name, - const xmlChar * ExternalID, +static void internalSubset(void * CTX, + const xmlChar * name, + const xmlChar * ExternalID, const xmlChar * SystemID) -{ SAYSO_DATAZ(name); } +{ + SAYSO_DATAZ(name); + SAYSO_DATAZ(ExternalID); + SAYSO_DATAZ(SystemID); +} -static int isStandalone (void * ctx) +#if 0 +static int isStandalone (void * CTX) { SAYSO(); } +#endif - -static void notationDecl(void * ctx, - const xmlChar * name, - const xmlChar * publicId, +static void notationDecl(void * CTX, + const xmlChar * name, + const xmlChar * publicId, const xmlChar * systemId) -{ SAYSO_DATAZ(name); } +{ + SAYSO_DATAZ(name); + SAYSO_DATAZ(publicId); + SAYSO_DATAZ(systemId); +} -static void processingInstruction(void * ctx, - const xmlChar * target, +static void processingInstruction(void * CTX, + const xmlChar * target, const xmlChar * data) { SAYSO_DATAZ(target); @@ -434,17 +463,19 @@ static void processingInstruction(void * ctx, xml_event("PROCESSING-INSTRUCTION-DATA", data); } -static void reference(void * ctx, +static void reference(void * CTX, const xmlChar * name) { SAYSO_DATAZ(name); } -static xmlParserInputPtr resolveEntity( void * ctx, - const xmlChar * publicId, +#if 0 +static xmlParserInputPtr resolveEntity( void * CTX, + const xmlChar * publicId, const xmlChar * systemId) { SAYSO(); } +#endif -static void setDocumentLocator(void * ctx, - xmlSAXLocatorPtr loc) +static void setDocumentLocator(void * CTX, + xmlSAXLocatorPtr loc __attribute__ ((unused)) ) { SAYSO(); } /* @@ -452,36 +483,48 @@ static void setDocumentLocator(void * ctx, * Use xmlCtxtGetVersion(), xmlCtxtGetDeclaredEncoding() and * xmlCtxtGetStandalone() to get data from the XML declaration. */ -static void startDocument(void * ctx) -{ SAYSO(); } +static void startDocument(void * CTX) +{ + SAYSO(); +} -static void startElementNs(void * ctx, - const xmlChar * localname, - const xmlChar * prefix, - const xmlChar * URI, - int nb_namespaces, - const xmlChar ** namespaces, - int nb_attributes, - int nb_defaulted, - const xmlChar ** attributes) +static void startElementNs(void * CTX, + const xmlChar * localname, + const xmlChar * prefix, + const xmlChar * URI, + int nb_namespaces __attribute__ ((unused)), + const xmlChar ** namespaces __attribute__ ((unused)), + int nb_attributes __attribute__ ((unused)), + int nb_defaulted __attribute__ ((unused)), + const xmlChar ** attributes __attribute__ ((unused))) { + SAYSO_DATAZ(prefix); + SAYSO_DATAZ(URI); SAYSO_DATAZ(localname); xml_event("START-OF-ELEMENT", localname); } -static void startElement(void * ctx, - const xmlChar * name, +static void startElement(void * CTX, + const xmlChar * name, const xmlChar ** atts) -{ SAYSO_DATAZ(name); } +{ + SAYSO_DATAZ(name); + for( int i=0; atts[i]; i++ ) SAYSO_DATAZ(atts[i]); +} -static void unparsedEntityDecl(void * ctx, - const xmlChar * name, - const xmlChar * publicId, - const xmlChar * systemId, +static void unparsedEntityDecl(void * CTX, + const xmlChar * name, + const xmlChar * publicId, + const xmlChar * systemId, const xmlChar * notationName) -{ SAYSO_DATAZ(name); } +{ + SAYSO_DATAZ(name); + SAYSO_DATAZ(publicId); + SAYSO_DATAZ(systemId); + SAYSO_DATAZ(notationName); +} -static void warning(void * ctx, const char * msg, ... ) +static void warning(void * CTX, const char * msg, ... ) { va_list ap; va_start (ap, msg); @@ -494,15 +537,15 @@ static void warning(void * ctx, const char * msg, ... ) /* * xmlSAXHandler is a structure of function pointers that the SAX parser calls * as it encounters XML elements in the input. Each pointer is a callback - * function, locally defined in this file. These we term "handlers". - * + * function, locally defined in this file. These we term "handlers". + * * Each handler sets the XML registers per IBM, and then calls * cobol_callback(), which is a function pointer supplied by the COBOL program - * to be the processing procedure for XML PARSE. - * + * to be the processing procedure for XML PARSE. + * * There is no obvious way to abort parsing at the C level. See: * http://veillard.com/XML/messages/0540.html - * + * * > The simplest to implement this would not be to add a new SAX * > callback but rather modify the xmlParserCtxtPtr passed to the * > callbacks. The best seems to be: @@ -512,7 +555,7 @@ static void warning(void * ctx, const char * msg, ... ) * > Doing both should led to a quick termination of parsing * > (but endElement(s)/endDocument will certainly be called anyway). * - * Another hack might be to set the input to all blanks in cobol_callback. + * Another hack might be to set the input to all blanks in cobol_callback. */ static xmlSAXHandler handlers; @@ -548,7 +591,7 @@ initialize_handlers( callback_t *callback ) { //// Everything is available on the context, so this is useless in our case handlers.setDocumentLocator = setDocumentLocator; -#endif +#endif handlers.cdataBlock = cdataBlock; handlers.characters = characters; @@ -565,14 +608,158 @@ initialize_handlers( callback_t *callback ) { handlers.warning = warning; } +static xmlChar * +xmlchar_of( const char input[] ) { + return const_cast<xmlChar*>( reinterpret_cast<const xmlChar*>(input) ); +} + +static const char * +xmlParserErrors_str( xmlParserErrors erc, const char name[] ) { + const char *msg = "???"; + + switch( erc ) { + case XML_ERR_OK: + msg = "Success"; + break; + case XML_ERR_INTERNAL_ERROR: + msg = "Internal assertion failure"; + break; + case XML_ERR_NO_MEMORY: + msg = "Out of memory"; + break; + case XML_ERR_UNSUPPORTED_ENCODING: + msg = "Unsupported character encoding"; + break; +#if LIBXML_VERSION >= 21400 + case XML_ERR_RESOURCE_LIMIT: + msg = "Internal resource limit like maximum amplification factor exceeded"; + break; + case XML_ERR_ARGUMENT: + msg = "Invalid argument"; + break; + case XML_ERR_SYSTEM: + msg = "Unexpected error from the OS or an external library"; + break; +#endif + case XML_IO_ENOENT: + msg = "File not found"; + break; + default: + msg = strdup(name); + if( ! msg ) msg = "unknown XML error"; + break; + } + return msg; +} + +#define xmlerror_str(E) xmlParserErrors_str( (E), #E ) + +/* + * The global context is NULL if XML PARSE is not in progress. + */ +static class context_t { + xmlParserCtxt * ctxt; + const int priority; + public: + context_t() : ctxt(nullptr), priority(LOG_INFO) { + const int option = LOG_PERROR, facility = LOG_USER; +#if HAVE_DECL_PROGRAM_INVOCATION_SHORT_NAME + /* Declared in errno.h, when available. */ + static const char * const ident = program_invocation_short_name; +#elif defined (HAVE_GETPROGNAME) + /* Declared in stdlib.h. */ + static const char * const ident = getprogname(); +#else + /* Avoid a NULL entry. */ + static const char * const ident = "unnamed_COBOL_program"; +#endif + // TODO: Program to set option in library via command-line and/or environment. + // Library listens to program, not to the environment. + openlog(ident, option, facility); + + initialize_handlers(nullptr); + } + + void + push( cblc_field_t *input_field, size_t input_offset, size_t len, bool done ) { + if( ! ctxt ) { + init(); + } + assert(cobol_callback); // caller must set + + if( input_offset < len ) { + int size = len - input_offset; + const char *chunk = PTRCAST(char, input_field->data + input_offset); + int terminate = done? 1 : 0; + + auto erc = (xmlParserErrors )xmlParseChunk( ctxt, chunk, size, terminate ); + if( erc != 0 ) { + auto msg = xmlerror_str(erc); + syslog(priority, "XML PARSE: XML error: %s", msg); + } + + if( done ) this->done(); + + } + } + + void done() { + if( ctxt ) { + xmlFreeParserCtxt( ctxt ); + ctxt = nullptr; + } + } + + protected: + void init() { + const char *external_entities = nullptr; + void * const user_data = nullptr; + + ctxt = xmlCreatePushParserCtxt( &handlers, user_data, + nullptr, 0, external_entities); + } +} context; + +static int +xml_push_parse( cblc_field_t *input_field, + size_t input_offset, + size_t len, + cblc_field_t *encoding __attribute__ ((unused)), + cblc_field_t *validating __attribute__ ((unused)), + int returns_national __attribute__ ((unused)), + void (*callback)(void) ) +{ + ::cobol_callback = callback; + + context.push( input_field, input_offset, len, false); + +#if LIBXML_VERSION >= 21400 + const xmlChar * version = xmlCtxtGetVersion( ctxt ); +#else + const xmlChar * version = xmlchar_of("requires version 2.14"); +#endif + assert(version); + assert(nullptr == "function not ready and not called"); + return 0; +} + + +extern "C" // Parser calls via parser_xml_parse_end, probabably. +int +__gg__xml_parse_done() { + context.done(); + return 0; +} + + extern "C" -int +int __gg__xml_parse( const cblc_field_t *input_field, size_t input_offset, size_t len, - cblc_field_t *encoding, - cblc_field_t *validating, - int returns_national, + cblc_field_t *encoding __attribute__ ((unused)), + cblc_field_t *validating __attribute__ ((unused)), + int returns_national __attribute__ ((unused)), void (*callback)(void) ) { initialize_handlers(callback); @@ -582,7 +769,7 @@ __gg__xml_parse( const cblc_field_t *input_field, int erc = xmlSAXUserParseMemory(&handlers, nullptr, input, len); if( erc ) { - xmlErrorPtr msg = xmlCtxtGetLastError(nullptr); + const xmlError *msg = xmlCtxtGetLastError(nullptr); fprintf(stderr, "XML PARSE: error: line %d: %s (%d: %d.%d.%d)\n", msg->line, msg->message, erc, msg->domain, msg->level, msg->code); } diff --git a/libstdc++-v3/include/bits/utility.h b/libstdc++-v3/include/bits/utility.h index 4e57465..96ac698 100644 --- a/libstdc++-v3/include/bits/utility.h +++ b/libstdc++-v3/include/bits/utility.h @@ -172,6 +172,22 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION using index_sequence_for = make_index_sequence<sizeof...(_Types)>; #endif // __glibcxx_integer_sequence +#if __cpp_structured_bindings >= 202411L +#if __has_builtin(__integer_pack) + template <auto _Num, typename _Tp = decltype(_Num)> + inline constexpr _Tp + _IotaArray[_Num] = {__integer_pack(_Tp(_Num))...}; +#elif defined __glibcxx_integer_sequence + template <auto _Num, typename _Tp = decltype(_Num), typename = make_integer_sequence<_Tp, _Num>> + inline constexpr _Tp + _IotaArray[_Num]; + + template <auto _Num, typename _Tp, _Tp... _Is> + inline constexpr _Tp + _IotaArray<_Num, _Tp, integer_sequence<_Tp, _Is...>>[_Num] = {_Is...}; +#endif // __integer_pack +#endif // __cpp_structured_bindings >= 202411L + #if __cplusplus >= 201703L struct in_place_t { diff --git a/libstdc++-v3/include/bits/valarray_array.h b/libstdc++-v3/include/bits/valarray_array.h index b5c02b7..d1b712c 100644 --- a/libstdc++-v3/include/bits/valarray_array.h +++ b/libstdc++-v3/include/bits/valarray_array.h @@ -38,6 +38,7 @@ #include <bits/c++config.h> #include <bits/cpp_type_traits.h> +#include <bits/new_allocator.h> #include <cstdlib> #include <new> @@ -57,12 +58,13 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION template<typename _Tp> inline _Tp* __valarray_get_storage(size_t __n) - { return static_cast<_Tp*>(operator new(__n * sizeof(_Tp))); } + { return std::__new_allocator<_Tp>().allocate(__n); } // Return memory to the system - inline void - __valarray_release_memory(void* __p) - { operator delete(__p); } + template<typename _Tp> + inline void + __valarray_release_memory(_Tp* __p, size_t __n) + { std::__new_allocator<_Tp>().deallocate(__p, __n); } #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wc++17-extensions" // if constexpr diff --git a/libstdc++-v3/include/std/valarray b/libstdc++-v3/include/std/valarray index 82b58ef..ac15e79 100644 --- a/libstdc++-v3/include/std/valarray +++ b/libstdc++-v3/include/std/valarray @@ -720,7 +720,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION valarray<_Tp>::~valarray() _GLIBCXX_NOEXCEPT { std::__valarray_destroy_elements(_M_data, _M_data + _M_size); - std::__valarray_release_memory(_M_data); + std::__valarray_release_memory(_M_data, _M_size); } template<typename _Tp> @@ -736,7 +736,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION if (_M_data) { std::__valarray_destroy_elements(_M_data, _M_data + _M_size); - std::__valarray_release_memory(_M_data); + std::__valarray_release_memory(_M_data, _M_size); } _M_size = __v._M_size; _M_data = __valarray_get_storage<_Tp>(_M_size); @@ -754,7 +754,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION if (_M_data) { std::__valarray_destroy_elements(_M_data, _M_data + _M_size); - std::__valarray_release_memory(_M_data); + std::__valarray_release_memory(_M_data, _M_size); } _M_size = __v._M_size; _M_data = __v._M_data; @@ -776,7 +776,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION if (_M_data) { std::__valarray_destroy_elements(_M_data, _M_data + _M_size); - std::__valarray_release_memory(_M_data); + std::__valarray_release_memory(_M_data, _M_size); } _M_size = __l.size(); _M_data = __valarray_get_storage<_Tp>(_M_size); @@ -854,7 +854,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION if (_M_data) { std::__valarray_destroy_elements(_M_data, _M_data + _M_size); - std::__valarray_release_memory(_M_data); + std::__valarray_release_memory(_M_data, _M_size); } _M_size = __e.size(); _M_data = __valarray_get_storage<_Tp>(_M_size); @@ -1049,7 +1049,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION std::__valarray_destroy_elements(_M_data, _M_data + _M_size); if (_M_size != __n) { - std::__valarray_release_memory(_M_data); + std::__valarray_release_memory(_M_data, _M_size); _M_size = __n; _M_data = __valarray_get_storage<_Tp>(__n); } diff --git a/libstdc++-v3/testsuite/20_util/shared_ptr/atomic/pr118757.cc b/libstdc++-v3/testsuite/20_util/shared_ptr/atomic/pr118757.cc index d54abd8..f49ae38 100644 --- a/libstdc++-v3/testsuite/20_util/shared_ptr/atomic/pr118757.cc +++ b/libstdc++-v3/testsuite/20_util/shared_ptr/atomic/pr118757.cc @@ -1,4 +1,5 @@ // { dg-do run { target c++20 } } +// { dg-additional-options "-pthread" { target pthread } } // { dg-require-gthreads "" } // { dg-require-effective-target hosted } diff --git a/libstdc++-v3/testsuite/20_util/weak_ptr/pr118757.cc b/libstdc++-v3/testsuite/20_util/weak_ptr/pr118757.cc index f048f13..77757f3 100644 --- a/libstdc++-v3/testsuite/20_util/weak_ptr/pr118757.cc +++ b/libstdc++-v3/testsuite/20_util/weak_ptr/pr118757.cc @@ -1,4 +1,5 @@ // { dg-do run { target c++20 } } +// { dg-additional-options "-pthread" { target pthread } } // { dg-require-gthreads "" } // { dg-require-effective-target hosted } diff --git a/libstdc++-v3/testsuite/26_numerics/valarray/108951.cc b/libstdc++-v3/testsuite/26_numerics/valarray/108951.cc new file mode 100644 index 0000000..929a1d4 --- /dev/null +++ b/libstdc++-v3/testsuite/26_numerics/valarray/108951.cc @@ -0,0 +1,22 @@ +// { dg-do run { target c++11 } } +// { dg-additional-options "-faligned-new" { target c++14_down } } + +#include <valarray> +#include <cstdint> +#include <testsuite_hooks.h> + +struct alignas(64) Num +{ + Num() + { + VERIFY(reinterpret_cast<std::uintptr_t>(this) % alignof(*this) == 0); + } + + double val{}; +}; + +int main() +{ + std::valarray<Num> v(2); + v.resize(4, {}); +} diff --git a/libstdc++-v3/testsuite/30_threads/condition_variable/members/116586.cc b/libstdc++-v3/testsuite/30_threads/condition_variable/members/116586.cc index 7114007..e8c3e16 100644 --- a/libstdc++-v3/testsuite/30_threads/condition_variable/members/116586.cc +++ b/libstdc++-v3/testsuite/30_threads/condition_variable/members/116586.cc @@ -1,4 +1,7 @@ // { dg-do run { target c++11 } } +// { dg-additional-options "-pthread" { target pthread } } +// { dg-require-gthreads "" } +// { dg-require-effective-target hosted } #include <condition_variable> #include <chrono> diff --git a/libstdc++-v3/testsuite/30_threads/future/members/116586.cc b/libstdc++-v3/testsuite/30_threads/future/members/116586.cc index b7cd12c..82f1e5c 100644 --- a/libstdc++-v3/testsuite/30_threads/future/members/116586.cc +++ b/libstdc++-v3/testsuite/30_threads/future/members/116586.cc @@ -1,4 +1,7 @@ // { dg-do run { target c++11 } } +// { dg-additional-options "-pthread" { target pthread } } +// { dg-require-gthreads "" } +// { dg-require-effective-target hosted } #include <future> #include <chrono> diff --git a/libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_until/116586.cc b/libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_until/116586.cc index 941f3af..25a78e7 100644 --- a/libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_until/116586.cc +++ b/libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_until/116586.cc @@ -1,4 +1,7 @@ // { dg-do run { target c++11 } } +// { dg-additional-options "-pthread" { target pthread } } +// { dg-require-gthreads "" } +// { dg-require-effective-target hosted } #include <mutex> #include <chrono> diff --git a/libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_until/116586.cc b/libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_until/116586.cc index dcba7aa..1566228 100644 --- a/libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_until/116586.cc +++ b/libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_until/116586.cc @@ -1,4 +1,7 @@ // { dg-do run { target c++11 } } +// { dg-additional-options "-pthread" { target pthread } } +// { dg-require-gthreads "" } +// { dg-require-effective-target hosted } #include <chrono> #include <mutex> diff --git a/libstdc++-v3/testsuite/ext/iotaarray.cc b/libstdc++-v3/testsuite/ext/iotaarray.cc new file mode 100644 index 0000000..b259602 --- /dev/null +++ b/libstdc++-v3/testsuite/ext/iotaarray.cc @@ -0,0 +1,20 @@ +// { dg-do compile { target c++26 } } + +#include <utility> +#include <type_traits> + +template<auto N> +void test() +{ + constexpr auto [id0, ...ids] = std::_IotaArray<N>; + static_assert( std::is_same_v<decltype(id0), const decltype(N)> ); + static_assert( sizeof...(ids) == N - 1 ); + static_assert( (id0 + ... + ids) == N*(N-1)/2 ); +} + +int main() +{ + test<1>(); + test<4u>(); + test<8ull>(); +} diff --git a/libstdc++-v3/testsuite/util/testsuite_iterators.h b/libstdc++-v3/testsuite/util/testsuite_iterators.h index 5bf2e70..41fbcaa 100644 --- a/libstdc++-v3/testsuite/util/testsuite_iterators.h +++ b/libstdc++-v3/testsuite/util/testsuite_iterators.h @@ -674,6 +674,9 @@ namespace __gnu_test template <class T, template<class TT> class ItType> struct test_container { + typedef ItType<T> iterator; + typedef typename iterator::value_type value_type; + typename ItType<T>::ContainerType bounds; _GLIBCXX_CONSTEXPR |