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authorJakub Jelinek <jakub@redhat.com>2024-04-20 00:13:49 +0200
committerJakub Jelinek <jakub@redhat.com>2024-04-20 00:13:49 +0200
commitc23db3ebb65ba357155be85ef56d037403eaee36 (patch)
tree2d78760a06873455df4d48f4eaa83698e5728c6c /libstdc++-v3
parent2afdecccbaf5c5b1c7a235509b37092540906c02 (diff)
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i386: Fix up *avx2_eq<mode>3 constraints [PR114783]
The r14-4456 change (part of APX EGPR support) seems to have mistakenly changed in the @@ -16831,7 +16831,7 @@ (define_insn "*avx2_eq<mode>3" [(set (match_operand:VI_256 0 "register_operand" "=x") (eq:VI_256 (match_operand:VI_256 1 "nonimmediate_operand" "%x") - (match_operand:VI_256 2 "nonimmediate_operand" "xm")))] + (match_operand:VI_256 2 "nonimmediate_operand" "jm")))] "TARGET_AVX2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "vpcmpeq<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "ssecmp") hunk the xm constraint to jm, while in many other spots it changed correctly xm to xjm. The instruction doesn't require the last operand to be in memory, it can handle 3 256-bit registers just fine, just it is a VEX only encoded instruction and so can't allow APX EGPR regs in the memory operand. The following patch fixes it, so that we don't force one of the == operands into memory all the time. 2024-04-20 Jakub Jelinek <jakub@redhat.com> PR target/114783 * config/i386/sse.md (*avx2_eq<mode>3): Change last operand's constraint from "jm" to "xjm". * gcc.target/i386/avx2-pr114783.c: New test.
Diffstat (limited to 'libstdc++-v3')
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